drm/i915: preserve the PBC bits of TRANS_CHICKEN2

[linux-imx.git] / drivers / gpu / drm / i915 / intel_pm.c

diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c
index 17f157a7b640109b1db6af7a157cdf6eae6863ce..e34ad964251952a4cb967946b80d82c77cc7f940 100644 (file)
--- a/drivers/gpu/drm/i915/intel_pm.c
+++ b/drivers/gpu/drm/i915/intel_pm.c
@@ -2558,8 +2558,8 @@ static void gen6_enable_rps(struct drm_device *dev)
        rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
        gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
 
-       /* In units of 100MHz */
-       dev_priv->rps.max_delay = rp_state_cap & 0xff;
+       /* In units of 50MHz */
+       dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
        dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
        dev_priv->rps.cur_delay = 0;
 
@@ -2643,10 +2643,10 @@ static void gen6_enable_rps(struct drm_device *dev)
                pcu_mbox = 0;
                ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
                if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
-                       DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max from %dMHz to %dMHz\n",
+                       DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
                                         (dev_priv->rps.max_delay & 0xff) * 50,
                                         (pcu_mbox & 0xff) * 50);
-                       dev_priv->rps.max_delay = pcu_mbox & 0xff;
+                       dev_priv->rps.hw_max = pcu_mbox & 0xff;
                }
        } else {
                DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
@@ -2684,8 +2684,8 @@ static void gen6_update_ring_freq(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        int min_freq = 15;
-       int gpu_freq;
-       unsigned int ia_freq, max_ia_freq;
+       unsigned int gpu_freq;
+       unsigned int max_ia_freq, min_ring_freq;
        int scaling_factor = 180;
 
        WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
@@ -2701,6 +2701,10 @@ static void gen6_update_ring_freq(struct drm_device *dev)
        /* Convert from kHz to MHz */
        max_ia_freq /= 1000;
 
+       min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
+       /* convert DDR frequency from units of 133.3MHz to bandwidth */
+       min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
+
        /*
         * For each potential GPU frequency, load a ring frequency we'd like
         * to use for memory access.  We do this by specifying the IA frequency
@@ -2709,21 +2713,32 @@ static void gen6_update_ring_freq(struct drm_device *dev)
        for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
             gpu_freq--) {
                int diff = dev_priv->rps.max_delay - gpu_freq;
-
-               /*
-                * For GPU frequencies less than 750MHz, just use the lowest
-                * ring freq.
-                */
-               if (gpu_freq < min_freq)
-                       ia_freq = 800;
-               else
-                       ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
-               ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
-               ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
+               unsigned int ia_freq = 0, ring_freq = 0;
+
+               if (IS_HASWELL(dev)) {
+                       ring_freq = (gpu_freq * 5 + 3) / 4;
+                       ring_freq = max(min_ring_freq, ring_freq);
+                       /* leave ia_freq as the default, chosen by cpufreq */
+               } else {
+                       /* On older processors, there is no separate ring
+                        * clock domain, so in order to boost the bandwidth
+                        * of the ring, we need to upclock the CPU (ia_freq).
+                        *
+                        * For GPU frequencies less than 750MHz,
+                        * just use the lowest ring freq.
+                        */
+                       if (gpu_freq < min_freq)
+                               ia_freq = 800;
+                       else
+                               ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
+                       ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
+               }
 
                sandybridge_pcode_write(dev_priv,
                                        GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
-                                       ia_freq | gpu_freq);
+                                       ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
+                                       ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
+                                       gpu_freq);
        }
 }
 
@@ -3575,6 +3590,7 @@ static void cpt_init_clock_gating(struct drm_device *dev)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
        int pipe;
+       uint32_t val;
 
        /*
         * On Ibex Peak and Cougar Point, we need to disable clock
@@ -3587,8 +3603,17 @@ static void cpt_init_clock_gating(struct drm_device *dev)
        /* The below fixes the weird display corruption, a few pixels shifted
         * downward, on (only) LVDS of some HP laptops with IVY.
         */
-       for_each_pipe(pipe)
-               I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
+       for_each_pipe(pipe) {
+               val = I915_READ(TRANS_CHICKEN2(pipe));
+               val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
+               val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+               if (dev_priv->fdi_rx_polarity_inverted)
+                       val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
+               val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
+               val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
+               val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
+               I915_WRITE(TRANS_CHICKEN2(pipe), val);
+       }
        /* WADP0ClockGatingDisable */
        for_each_pipe(pipe) {
                I915_WRITE(TRANS_CHICKEN1(pipe),
@@ -4085,6 +4110,22 @@ void intel_init_clock_gating(struct drm_device *dev)
        dev_priv->display.init_clock_gating(dev);
 }
 
+/**
+ * We should only use the power well if we explicitly asked the hardware to
+ * enable it, so check if it's enabled and also check if we've requested it to
+ * be enabled.
+ */
+bool intel_using_power_well(struct drm_device *dev)
+{
+       struct drm_i915_private *dev_priv = dev->dev_private;
+
+       if (IS_HASWELL(dev))
+               return I915_READ(HSW_PWR_WELL_DRIVER) ==
+                      (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
+       else
+               return true;
+}
+
 void intel_set_power_well(struct drm_device *dev, bool enable)
 {
        struct drm_i915_private *dev_priv = dev->dev_private;
@@ -4191,7 +4232,6 @@ void intel_init_pm(struct drm_device *dev)
                        }
                        dev_priv->display.init_clock_gating = gen6_init_clock_gating;
                } else if (IS_IVYBRIDGE(dev)) {
-                       /* FIXME: detect B0+ stepping and use auto training */
                        if (SNB_READ_WM0_LATENCY()) {
                                dev_priv->display.update_wm = ivybridge_update_wm;
                                dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;