drm/i915: clarify confusion between SDVO and HDMI registers

[linux-imx.git] / drivers / gpu / drm / i915 / i915_reg.h

diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h
index 527b664d343490238aded9ce08d42e2f4e4549a6..448e13c26c876c37fe27ac0f7b716607665695d3 100644 (file)
--- a/drivers/gpu/drm/i915/i915_reg.h
+++ b/drivers/gpu/drm/i915/i915_reg.h
@@ -522,6 +522,9 @@
 #define GEN7_ERR_INT   0x44040
 #define   ERR_INT_MMIO_UNCLAIMED (1<<13)
 
+#define FPGA_DBG               0x42300
+#define   FPGA_DBG_RM_NOCLAIM  (1<<31)
+
 #define DERRMR         0x44050
 
 /* GM45+ chicken bits -- debug workaround bits that may be required
@@ -591,6 +594,7 @@
 #define   I915_USER_INTERRUPT                          (1<<1)
 #define   I915_ASLE_INTERRUPT                          (1<<0)
 #define   I915_BSD_USER_INTERRUPT                      (1<<25)
+#define   DISPLAY_PLANE_FLIP_PENDING(plane) (1<<(11-(plane))) /* A and B only */
 #define EIR            0x020b0
 #define EMR            0x020b4
 #define ESR            0x020b8
@@ -1677,8 +1681,9 @@
 #define   SDVOB_HOTPLUG_INT_STATUS_I915                (1 << 6)
 
 /* SDVO port control */
-#define SDVOB                  0x61140
-#define SDVOC                  0x61160
+#define GEN3_SDVOB             0x61140
+#define GEN3_SDVOC             0x61160
+#define PCH_SDVOB              0xe1140
 #define   SDVO_ENABLE          (1 << 31)
 #define   SDVO_PIPE_B_SELECT   (1 << 30)
 #define   SDVO_STALL_SELECT    (1 << 29)
@@ -3754,14 +3759,16 @@
 #define HSW_VIDEO_DIP_VSC_ECC_B                0x61344
 #define HSW_VIDEO_DIP_GCP_B            0x61210
 
-#define HSW_TVIDEO_DIP_CTL(pipe) \
-        _PIPE(pipe, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
-#define HSW_TVIDEO_DIP_AVI_DATA(pipe) \
-        _PIPE(pipe, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
-#define HSW_TVIDEO_DIP_SPD_DATA(pipe) \
-        _PIPE(pipe, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
-#define HSW_TVIDEO_DIP_GCP(pipe) \
-       _PIPE(pipe, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
+#define HSW_TVIDEO_DIP_CTL(trans) \
+        _TRANSCODER(trans, HSW_VIDEO_DIP_CTL_A, HSW_VIDEO_DIP_CTL_B)
+#define HSW_TVIDEO_DIP_AVI_DATA(trans) \
+        _TRANSCODER(trans, HSW_VIDEO_DIP_AVI_DATA_A, HSW_VIDEO_DIP_AVI_DATA_B)
+#define HSW_TVIDEO_DIP_SPD_DATA(trans) \
+        _TRANSCODER(trans, HSW_VIDEO_DIP_SPD_DATA_A, HSW_VIDEO_DIP_SPD_DATA_B)
+#define HSW_TVIDEO_DIP_GCP(trans) \
+       _TRANSCODER(trans, HSW_VIDEO_DIP_GCP_A, HSW_VIDEO_DIP_GCP_B)
+#define HSW_TVIDEO_DIP_VSC_DATA(trans) \
+        _TRANSCODER(trans, HSW_VIDEO_DIP_VSC_DATA_A, HSW_VIDEO_DIP_VSC_DATA_B)
 
 #define _TRANS_HTOTAL_B          0xe1000
 #define _TRANS_HBLANK_B          0xe1004
@@ -3976,8 +3983,12 @@
 #define FDI_PLL_CTL_1           0xfe000
 #define FDI_PLL_CTL_2           0xfe004
 
-/* or SDVOB */
-#define HDMIB   0xe1140
+/* The same register may be used for SDVO or HDMI */
+#define GEN4_HDMIB     GEN3_SDVOB
+#define GEN4_HDMIC     GEN3_SDVOC
+#define PCH_HDMIB      PCH_SDVOB
+#define PCH_HDMIC      0xe1150
+#define PCH_HDMID      0xe1160
 #define  PORT_ENABLE    (1 << 31)
 #define  TRANSCODER(pipe)       ((pipe) << 30)
 #define  TRANSCODER_CPT(pipe)   ((pipe) << 29)
@@ -3998,12 +4009,6 @@
 #define  HSYNC_ACTIVE_HIGH      (1 << 3)
 #define  PORT_DETECTED          (1 << 2)
 
-/* PCH SDVOB multiplex with HDMIB */
-#define PCH_SDVOB      HDMIB
-
-#define HDMIC   0xe1150
-#define HDMID   0xe1160
-
 #define PCH_LVDS       0xe1180
 #define  LVDS_DETECTED (1 << 1)