drm/radeon/dpm: fix a typo in the rv6xx mclk setup

[linux-imx.git] / drivers / gpu / drm / radeon / rv6xx_dpm.c

diff --git a/drivers/gpu/drm/radeon/rv6xx_dpm.c b/drivers/gpu/drm/radeon/rv6xx_dpm.c
index 33705c5c83690a1e888bd31f6eb45905b2a9cdad..b1c2a62df950582e4337129063cda5baf2442da5 100644 (file)
--- a/drivers/gpu/drm/radeon/rv6xx_dpm.c
+++ b/drivers/gpu/drm/radeon/rv6xx_dpm.c
@@ -28,6 +28,7 @@
 #include "r600_dpm.h"
 #include "rv6xx_dpm.h"
 #include "atom.h"
+#include <linux/seq_file.h>
 
 static u32 rv6xx_scale_count_given_unit(struct radeon_device *rdev,
                                        u32 unscaled_count, u32 unit);
@@ -818,7 +819,7 @@ static void rv6xx_program_memory_timing_parameters(struct radeon_device *rdev)
                 POWERMODE1(calculate_memory_refresh_rate(rdev,
                                                          pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
                 POWERMODE2(calculate_memory_refresh_rate(rdev,
-                                                         pi->hw.sclks[R600_POWER_LEVEL_MEDIUM])) |
+                                                         pi->hw.sclks[R600_POWER_LEVEL_HIGH])) |
                 POWERMODE3(calculate_memory_refresh_rate(rdev,
                                                          pi->hw.sclks[R600_POWER_LEVEL_HIGH])));
        WREG32(ARB_RFSH_RATE, arb_refresh_rate);
@@ -1762,12 +1763,14 @@ void rv6xx_setup_asic(struct radeon_device *rdev)
 {
        r600_enable_acpi_pm(rdev);
 
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
-               rv6xx_enable_l0s(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
-               rv6xx_enable_l1(rdev);
-       if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
-               rv6xx_enable_pll_sleep_in_l1(rdev);
+       if (radeon_aspm != 0) {
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L0s)
+                       rv6xx_enable_l0s(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_ASPM_L1)
+                       rv6xx_enable_l1(rdev);
+               if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_TURNOFFPLL_ASPML1)
+                       rv6xx_enable_pll_sleep_in_l1(rdev);
+       }
 }
 
 void rv6xx_dpm_display_configuration_changed(struct radeon_device *rdev)