u32 pasi;
u32 vrc;
u32 restricted_levels;
+ u32 rlp;
+ u32 rmp;
+ u32 lhp;
+ u32 lmp;
/* smc offsets */
u16 state_table_start;
u16 soft_regs_start;
u16 vddc;
u16 vddci; /* eg+ only */
u32 flags;
+ enum radeon_pcie_gen pcie_gen; /* si+ only */
};
struct rv7xx_ps {
void r7xx_stop_smc(struct radeon_device *rdev);
void rv770_reset_smio_status(struct radeon_device *rdev);
int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev);
-int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev);
+int rv770_dpm_force_performance_level(struct radeon_device *rdev,
+ enum radeon_dpm_forced_level level);
int rv770_halt_smc(struct radeon_device *rdev);
int rv770_resume_smc(struct radeon_device *rdev);
int rv770_set_sw_state(struct radeon_device *rdev);
int rv770_set_boot_state(struct radeon_device *rdev);
int rv7xx_parse_power_table(struct radeon_device *rdev);
+void rv770_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps);
+void rv770_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
+ struct radeon_ps *new_ps,
+ struct radeon_ps *old_ps);
+void rv770_get_engine_memory_ss(struct radeon_device *rdev);
/* smc */
int rv770_read_smc_soft_register(struct radeon_device *rdev,
int rv770_write_smc_soft_register(struct radeon_device *rdev,
u16 reg_offset, u32 value);
+/* thermal */
+int rv770_set_thermal_temperature_range(struct radeon_device *rdev,
+ int min_temp, int max_temp);
+
#endif