drm/i915: add HAS_POWER_WELL

[linux-imx.git] / drivers / gpu / drm / i915 / i915_drv.h

diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h
index bffe222e1616d258b0d343790746cc64e256df59..71f285c56f1ea5eb049567ac589c5c8bc6807aef 100644 (file)
--- a/drivers/gpu/drm/i915/i915_drv.h
+++ b/drivers/gpu/drm/i915/i915_drv.h
@@ -209,10 +209,13 @@ struct drm_i915_error_state {
        u32 pgtbl_er;
        u32 ier;
        u32 ccid;
+       u32 derrmr;
+       u32 forcewake;
        bool waiting[I915_NUM_RINGS];
        u32 pipestat[I915_MAX_PIPES];
        u32 tail[I915_NUM_RINGS];
        u32 head[I915_NUM_RINGS];
+       u32 ctl[I915_NUM_RINGS];
        u32 ipeir[I915_NUM_RINGS];
        u32 ipehr[I915_NUM_RINGS];
        u32 instdone[I915_NUM_RINGS];
@@ -240,7 +243,7 @@ struct drm_i915_error_state {
                        int page_count;
                        u32 gtt_offset;
                        u32 *pages[0];
-               } *ringbuffer, *batchbuffer;
+               } *ringbuffer, *batchbuffer, *ctx;
                struct drm_i915_error_request {
                        long jiffies;
                        u32 seqno;
@@ -365,6 +368,12 @@ struct intel_device_info {
        u8 has_llc:1;
 };
 
+enum i915_cache_level {
+       I915_CACHE_NONE = 0,
+       I915_CACHE_LLC,
+       I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
+};
+
 /* The Graphics Translation Table is the way in which GEN hardware translates a
  * Graphics Virtual Address into a Physical Address. In addition to the normal
  * collateral associated with any va->pa translations GEN hardware also has a
@@ -375,6 +384,7 @@ struct intel_device_info {
 struct i915_gtt {
        unsigned long start;            /* Start offset of used GTT */
        size_t total;                   /* Total size GTT can map */
+       size_t stolen_size;             /* Total size of stolen memory */
 
        unsigned long mappable_end;     /* End offset that we can CPU map */
        struct io_mapping *mappable;    /* Mapping to our CPU mappable region */
@@ -386,7 +396,21 @@ struct i915_gtt {
        bool do_idle_maps;
        dma_addr_t scratch_page_dma;
        struct page *scratch_page;
+
+       /* global gtt ops */
+       int (*gtt_probe)(struct drm_device *dev, size_t *gtt_total,
+                         size_t *stolen, phys_addr_t *mappable_base,
+                         unsigned long *mappable_end);
+       void (*gtt_remove)(struct drm_device *dev);
+       void (*gtt_clear_range)(struct drm_device *dev,
+                               unsigned int first_entry,
+                               unsigned int num_entries);
+       void (*gtt_insert_entries)(struct drm_device *dev,
+                                  struct sg_table *st,
+                                  unsigned int pg_start,
+                                  enum i915_cache_level cache_level);
 };
+#define gtt_total_entries(gtt) ((gtt).total >> PAGE_SHIFT)
 
 #define I915_PPGTT_PD_ENTRIES 512
 #define I915_PPGTT_PT_ENTRIES 1024
@@ -397,6 +421,16 @@ struct i915_hw_ppgtt {
        uint32_t pd_offset;
        dma_addr_t *pt_dma_addr;
        dma_addr_t scratch_page_dma_addr;
+
+       /* pte functions, mirroring the interface of the global gtt. */
+       void (*clear_range)(struct i915_hw_ppgtt *ppgtt,
+                           unsigned int first_entry,
+                           unsigned int num_entries);
+       void (*insert_entries)(struct i915_hw_ppgtt *ppgtt,
+                              struct sg_table *st,
+                              unsigned int pg_start,
+                              enum i915_cache_level cache_level);
+       void (*cleanup)(struct i915_hw_ppgtt *ppgtt);
 };
 
 
@@ -667,8 +701,6 @@ struct intel_l3_parity {
 };
 
 struct i915_gem_mm {
-       /** Bridge to intel-gtt-ko */
-       struct intel_gtt *gtt;
        /** Memory allocator for GTT stolen memory */
        struct drm_mm stolen;
        /** Memory allocator for GTT */
@@ -815,6 +847,12 @@ struct i915_gpu_error {
        unsigned int stop_rings;
 };
 
+enum modeset_restore {
+       MODESET_ON_LID_OPEN,
+       MODESET_DONE,
+       MODESET_SUSPENDED,
+};
+
 typedef struct drm_i915_private {
        struct drm_device *dev;
        struct kmem_cache *slab;
@@ -867,7 +905,6 @@ typedef struct drm_i915_private {
        struct mutex dpio_lock;
 
        /** Cached value of IMR to avoid reads in updating the bitfield */
-       u32 pipestat[2];
        u32 irq_mask;
        u32 gt_irq_mask;
 
@@ -888,7 +925,7 @@ typedef struct drm_i915_private {
 
        /* overlay */
        struct intel_overlay *overlay;
-       bool sprite_scaling_enabled;
+       unsigned int sprite_scaling_enabled;
 
        /* LVDS info */
        int backlight_level;  /* restore backlight to this value */
@@ -936,8 +973,8 @@ typedef struct drm_i915_private {
 
        unsigned long quirks;
 
-       /* Register state */
-       bool modeset_on_lid;
+       enum modeset_restore modeset_restore;
+       struct mutex modeset_restore_lock;
 
        struct i915_gtt gtt;
 
@@ -1002,7 +1039,7 @@ typedef struct drm_i915_private {
        bool hw_contexts_disabled;
        uint32_t hw_context_size;
 
-       bool fdi_rx_polarity_reversed;
+       u32 fdi_rx_config;
 
        struct i915_suspend_saved_registers regfile;
 
@@ -1023,12 +1060,6 @@ enum hdmi_force_audio {
        HDMI_AUDIO_ON,                  /* force turn on HDMI audio */
 };
 
-enum i915_cache_level {
-       I915_CACHE_NONE = 0,
-       I915_CACHE_LLC,
-       I915_CACHE_LLC_MLC, /* gen6+, in docs at least! */
-};
-
 #define I915_GTT_RESERVED ((struct drm_mm_node *)0x1)
 
 struct drm_i915_gem_object_ops {
@@ -1183,13 +1214,6 @@ struct drm_i915_gem_object {
 
        /** for phy allocated objects */
        struct drm_i915_gem_phys_object *phys_obj;
-
-       /**
-        * Number of crtcs where this object is currently the fb, but
-        * will be page flipped away on the next vblank.  When it
-        * reaches 0, dev_priv->pending_flip_queue will be woken up.
-        */
-       atomic_t pending_flip;
 };
 #define to_gem_object(obj) (&((struct drm_i915_gem_object *)(obj))->base)
 
@@ -1315,6 +1339,7 @@ struct drm_i915_file_private {
 #define HAS_PIPE_CONTROL(dev) (INTEL_INFO(dev)->gen >= 5)
 
 #define HAS_DDI(dev)           (IS_HASWELL(dev))
+#define HAS_POWER_WELL(dev)    (IS_HASWELL(dev))
 
 #define INTEL_PCH_DEVICE_ID_MASK               0xff00
 #define INTEL_PCH_IBX_DEVICE_ID_TYPE           0x3b00
@@ -1653,7 +1678,6 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data,
                                   struct drm_file *file);
 
 /* i915_gem_gtt.c */
-int __must_check i915_gem_init_aliasing_ppgtt(struct drm_device *dev);
 void i915_gem_cleanup_aliasing_ppgtt(struct drm_device *dev);
 void i915_ppgtt_bind_object(struct i915_hw_ppgtt *ppgtt,
                            struct drm_i915_gem_object *obj,
@@ -1671,7 +1695,6 @@ void i915_gem_init_global_gtt(struct drm_device *dev);
 void i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
                               unsigned long mappable_end, unsigned long end);
 int i915_gem_gtt_init(struct drm_device *dev);
-void i915_gem_gtt_fini(struct drm_device *dev);
 static inline void i915_gem_chipset_flush(struct drm_device *dev)
 {
        if (INTEL_INFO(dev)->gen < 6)
@@ -1867,4 +1890,19 @@ __i915_write(64, q)
 #define INTEL_BROADCAST_RGB_FULL 1
 #define INTEL_BROADCAST_RGB_LIMITED 2
 
+static inline uint32_t i915_vgacntrl_reg(struct drm_device *dev)
+{
+       if (HAS_PCH_SPLIT(dev))
+               return CPU_VGACNTRL;
+       else if (IS_VALLEYVIEW(dev))
+               return VLV_VGACNTRL;
+       else
+               return VGACNTRL;
+}
+
+static inline void __user *to_user_ptr(u64 address)
+{
+       return (void __user *)(uintptr_t)address;
+}
+
 #endif