drm/radeon/dpm: re-enable state transitions for Cayman

[linux-imx.git] / drivers / gpu / drm / radeon / ni_dpm.c

diff --git a/drivers/gpu/drm/radeon/ni_dpm.c b/drivers/gpu/drm/radeon/ni_dpm.c
index ebde8d01c76dd5151c2651badafff3a933d1ead1..4712851808a3e13cec4d5485b8836041e503fe0c 100644 (file)
--- a/drivers/gpu/drm/radeon/ni_dpm.c
+++ b/drivers/gpu/drm/radeon/ni_dpm.c
@@ -1036,7 +1036,6 @@ static int ni_restrict_performance_levels_before_switch(struct radeon_device *rd
                0 : -EINVAL;
 }
 
-#if 0
 static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *rdev)
 {
        if (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
@@ -1045,7 +1044,6 @@ static int ni_unrestrict_performance_levels_after_switch(struct radeon_device *r
        return (ni_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) == PPSMC_Result_OK) ?
                0 : -EINVAL;
 }
-#endif
 
 static void ni_stop_smc(struct radeon_device *rdev)
 {
@@ -3475,6 +3473,42 @@ static void ni_enable_dynamic_pcie_gen2(struct radeon_device *rdev,
                 WREG32_P(GENERAL_PWRMGT, 0, ~ENABLE_GEN2PCIE);
 }
 
+void ni_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
+                                          struct radeon_ps *new_ps,
+                                          struct radeon_ps *old_ps)
+{
+       struct ni_ps *new_state = ni_get_ps(new_ps);
+       struct ni_ps *current_state = ni_get_ps(old_ps);
+
+       if ((new_ps->vclk == old_ps->vclk) &&
+           (new_ps->dclk == old_ps->dclk))
+               return;
+
+       if (new_state->performance_levels[new_state->performance_level_count - 1].sclk >=
+           current_state->performance_levels[current_state->performance_level_count - 1].sclk)
+               return;
+
+       radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
+}
+
+void ni_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
+                                         struct radeon_ps *new_ps,
+                                         struct radeon_ps *old_ps)
+{
+       struct ni_ps *new_state = ni_get_ps(new_ps);
+       struct ni_ps *current_state = ni_get_ps(old_ps);
+
+       if ((new_ps->vclk == old_ps->vclk) &&
+           (new_ps->dclk == old_ps->dclk))
+               return;
+
+       if (new_state->performance_levels[new_state->performance_level_count - 1].sclk <
+           current_state->performance_levels[current_state->performance_level_count - 1].sclk)
+               return;
+
+       radeon_set_uvd_clocks(rdev, new_ps->vclk, new_ps->dclk);
+}
+
 void ni_dpm_setup_asic(struct radeon_device *rdev)
 {
        struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
@@ -3683,7 +3717,7 @@ void ni_dpm_disable(struct radeon_device *rdev)
        ni_update_current_ps(rdev, boot_ps);
 }
 
-int ni_power_control_set_level(struct radeon_device *rdev)
+static int ni_power_control_set_level(struct radeon_device *rdev)
 {
        struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
        int ret;
@@ -3700,7 +3734,9 @@ int ni_power_control_set_level(struct radeon_device *rdev)
        ret = rv770_resume_smc(rdev);
        if (ret)
                return ret;
-       rv770_set_sw_state(rdev);
+       ret = rv770_set_sw_state(rdev);
+       if (ret)
+               return ret;
 
        return 0;
 }
@@ -3730,7 +3766,7 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
                DRM_ERROR("ni_restrict_performance_levels_before_switch failed\n");
                return ret;
        }
-       rv770_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
+       ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
        ret = ni_enable_power_containment(rdev, new_ps, false);
        if (ret) {
                DRM_ERROR("ni_enable_power_containment failed\n");
@@ -3765,11 +3801,6 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
                DRM_ERROR("ni_program_memory_timing_parameters failed\n");
                return ret;
        }
-       ret = ni_populate_smc_tdp_limits(rdev, new_ps);
-       if (ret) {
-               DRM_ERROR("ni_populate_smc_tdp_limits failed\n");
-               return ret;
-       }
        ret = rv770_resume_smc(rdev);
        if (ret) {
                DRM_ERROR("rv770_resume_smc failed\n");
@@ -3780,7 +3811,7 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
                DRM_ERROR("rv770_set_sw_state failed\n");
                return ret;
        }
-       rv770_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
+       ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
        ret = ni_enable_smc_cac(rdev, new_ps, true);
        if (ret) {
                DRM_ERROR("ni_enable_smc_cac failed\n");
@@ -3792,14 +3823,18 @@ int ni_dpm_set_power_state(struct radeon_device *rdev)
                return ret;
        }
 
-#if 0
-       /* XXX */
+       /* update tdp */
+       ret = ni_power_control_set_level(rdev);
+       if (ret) {
+               DRM_ERROR("ni_power_control_set_level failed\n");
+               return ret;
+       }
+
        ret = ni_unrestrict_performance_levels_after_switch(rdev);
        if (ret) {
                DRM_ERROR("ni_unrestrict_performance_levels_after_switch failed\n");
                return ret;
        }
-#endif
 
        return 0;
 }
@@ -4243,11 +4278,11 @@ void ni_dpm_print_power_state(struct radeon_device *rdev,
        for (i = 0; i < ps->performance_level_count; i++) {
                pl = &ps->performance_levels[i];
                if (rdev->family >= CHIP_TAHITI)
-                       printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
-                              pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
+                       printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
+                              i, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
                else
-                       printk("\t\tpower level 0    sclk: %u mclk: %u vddc: %u vddci: %u\n",
-                              pl->sclk, pl->mclk, pl->vddc, pl->vddci);
+                       printk("\t\tpower level %d    sclk: %u mclk: %u vddc: %u vddci: %u\n",
+                              i, pl->sclk, pl->mclk, pl->vddc, pl->vddci);
        }
        r600_dpm_print_ps_status(rdev, rps);
 }