arch/arm/mach-omap2/cpuidle34xx.c

   1 /*
   2  * linux/arch/arm/mach-omap2/cpuidle34xx.c
   3  *
   4  * OMAP3 CPU IDLE Routines
   5  *
   6  * Copyright (C) 2008 Texas Instruments, Inc.
   7  * Rajendra Nayak <rnayak@ti.com>
   8  *
   9  * Copyright (C) 2007 Texas Instruments, Inc.
  10  * Karthik Dasu <karthik-dp@ti.com>
  11  *
  12  * Copyright (C) 2006 Nokia Corporation
  13  * Tony Lindgren <tony@atomide.com>
  14  *
  15  * Copyright (C) 2005 Texas Instruments, Inc.
  16  * Richard Woodruff <r-woodruff2@ti.com>
  17  *
  18  * Based on pm.c for omap2
  19  *
  20  * This program is free software; you can redistribute it and/or modify
  21  * it under the terms of the GNU General Public License version 2 as
  22  * published by the Free Software Foundation.
  23  */
  24
  25 #include <linux/sched.h>
  26 #include <linux/cpuidle.h>
  27 #include <linux/export.h>
  28 #include <linux/cpu_pm.h>
  29
  30 #include <plat/prcm.h>
  31 #include <plat/irqs.h>
  32 #include "powerdomain.h"
  33 #include "clockdomain.h"
  34
  35 #include "pm.h"
  36 #include "control.h"
  37 #include "common.h"
  38
  39 #ifdef CONFIG_CPU_IDLE
  40
  41 /* Mach specific information to be recorded in the C-state driver_data */
  42 struct omap3_idle_statedata {
  43         u32 mpu_state;
  44         u32 core_state;
  45 };
  46
  47 static struct omap3_idle_statedata omap3_idle_data[] = {
  48         {
  49                 .mpu_state = PWRDM_POWER_ON,
  50                 .core_state = PWRDM_POWER_ON,
  51         },
  52         {
  53                 .mpu_state = PWRDM_POWER_ON,
  54                 .core_state = PWRDM_POWER_ON,
  55         },
  56         {
  57                 .mpu_state = PWRDM_POWER_RET,
  58                 .core_state = PWRDM_POWER_ON,
  59         },
  60         {
  61                 .mpu_state = PWRDM_POWER_OFF,
  62                 .core_state = PWRDM_POWER_ON,
  63         },
  64         {
  65                 .mpu_state = PWRDM_POWER_RET,
  66                 .core_state = PWRDM_POWER_RET,
  67         },
  68         {
  69                 .mpu_state = PWRDM_POWER_OFF,
  70                 .core_state = PWRDM_POWER_RET,
  71         },
  72         {
  73                 .mpu_state = PWRDM_POWER_OFF,
  74                 .core_state = PWRDM_POWER_OFF,
  75         },
  76 };
  77
  78 static struct powerdomain *mpu_pd, *core_pd, *per_pd, *cam_pd;
  79
  80 static int _cpuidle_allow_idle(struct powerdomain *pwrdm,
  81                                 struct clockdomain *clkdm)
  82 {
  83         clkdm_allow_idle(clkdm);
  84         return 0;
  85 }
  86
  87 static int _cpuidle_deny_idle(struct powerdomain *pwrdm,
  88                                 struct clockdomain *clkdm)
  89 {
  90         clkdm_deny_idle(clkdm);
  91         return 0;
  92 }
  93
  94 static int __omap3_enter_idle(struct cpuidle_device *dev,
  95                                 struct cpuidle_driver *drv,
  96                                 int index)
  97 {
  98         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
  99         u32 mpu_state = cx->mpu_state, core_state = cx->core_state;
 100
 101         local_fiq_disable();
 102
 103         pwrdm_set_next_pwrst(mpu_pd, mpu_state);
 104         pwrdm_set_next_pwrst(core_pd, core_state);
 105
 106         if (omap_irq_pending() || need_resched())
 107                 goto return_sleep_time;
 108
 109         /* Deny idle for C1 */
 110         if (index == 0) {
 111                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_deny_idle);
 112                 pwrdm_for_each_clkdm(core_pd, _cpuidle_deny_idle);
 113         }
 114
 115         /*
 116          * Call idle CPU PM enter notifier chain so that
 117          * VFP context is saved.
 118          */
 119         if (mpu_state == PWRDM_POWER_OFF)
 120                 cpu_pm_enter();
 121
 122         /* Execute ARM wfi */
 123         omap_sram_idle();
 124
 125         /*
 126          * Call idle CPU PM enter notifier chain to restore
 127          * VFP context.
 128          */
 129         if (pwrdm_read_prev_pwrst(mpu_pd) == PWRDM_POWER_OFF)
 130                 cpu_pm_exit();
 131
 132         /* Re-allow idle for C1 */
 133         if (index == 0) {
 134                 pwrdm_for_each_clkdm(mpu_pd, _cpuidle_allow_idle);
 135                 pwrdm_for_each_clkdm(core_pd, _cpuidle_allow_idle);
 136         }
 137
 138 return_sleep_time:
 139
 140         local_fiq_enable();
 141
 142         return index;
 143 }
 144
 145 /**
 146  * omap3_enter_idle - Programs OMAP3 to enter the specified state
 147  * @dev: cpuidle device
 148  * @drv: cpuidle driver
 149  * @index: the index of state to be entered
 150  *
 151  * Called from the CPUidle framework to program the device to the
 152  * specified target state selected by the governor.
 153  */
 154 static inline int omap3_enter_idle(struct cpuidle_device *dev,
 155                                 struct cpuidle_driver *drv,
 156                                 int index)
 157 {
 158         return cpuidle_wrap_enter(dev, drv, index, __omap3_enter_idle);
 159 }
 160
 161 /**
 162  * next_valid_state - Find next valid C-state
 163  * @dev: cpuidle device
 164  * @drv: cpuidle driver
 165  * @index: Index of currently selected c-state
 166  *
 167  * If the state corresponding to index is valid, index is returned back
 168  * to the caller. Else, this function searches for a lower c-state which is
 169  * still valid (as defined in omap3_power_states[]) and returns its index.
 170  *
 171  * A state is valid if the 'valid' field is enabled and
 172  * if it satisfies the enable_off_mode condition.
 173  */
 174 static int next_valid_state(struct cpuidle_device *dev,
 175                             struct cpuidle_driver *drv, int index)
 176 {
 177         struct omap3_idle_statedata *cx = &omap3_idle_data[index];
 178         u32 mpu_deepest_state = PWRDM_POWER_RET;
 179         u32 core_deepest_state = PWRDM_POWER_RET;
 180         int idx;
 181         int next_index = 0; /* C1 is the default value */
 182
 183         if (enable_off_mode) {
 184                 mpu_deepest_state = PWRDM_POWER_OFF;
 185                 /*
 186                  * Erratum i583: valable for ES rev < Es1.2 on 3630.
 187                  * CORE OFF mode is not supported in a stable form, restrict
 188                  * instead the CORE state to RET.
 189                  */
 190                 if (!IS_PM34XX_ERRATUM(PM_SDRC_WAKEUP_ERRATUM_i583))
 191                         core_deepest_state = PWRDM_POWER_OFF;
 192         }
 193
 194         /* Check if current state is valid */
 195         if ((cx->mpu_state >= mpu_deepest_state) &&
 196             (cx->core_state >= core_deepest_state))
 197                 return index;
 198
 199         /*
 200          * Drop to next valid state.
 201          * Start search from the next (lower) state.
 202          */
 203         for (idx = index - 1; idx >= 0; idx--) {
 204                 cx =  &omap3_idle_data[idx];
 205                 if ((cx->mpu_state >= mpu_deepest_state) &&
 206                     (cx->core_state >= core_deepest_state)) {
 207                         next_index = idx;
 208                         break;
 209                 }
 210         }
 211
 212         return next_index;
 213 }
 214
 215 /**
 216  * omap3_enter_idle_bm - Checks for any bus activity
 217  * @dev: cpuidle device
 218  * @drv: cpuidle driver
 219  * @index: array index of target state to be programmed
 220  *
 221  * This function checks for any pending activity and then programs
 222  * the device to the specified or a safer state.
 223  */
 224 static int omap3_enter_idle_bm(struct cpuidle_device *dev,
 225                                 struct cpuidle_driver *drv,
 226                                int index)
 227 {
 228         int new_state_idx;
 229         u32 core_next_state, per_next_state = 0, per_saved_state = 0, cam_state;
 230         struct omap3_idle_statedata *cx;
 231         int ret;
 232
 233         /*
 234          * Prevent idle completely if CAM is active.
 235          * CAM does not have wakeup capability in OMAP3.
 236          */
 237         cam_state = pwrdm_read_pwrst(cam_pd);
 238         if (cam_state == PWRDM_POWER_ON) {
 239                 new_state_idx = drv->safe_state_index;
 240                 goto select_state;
 241         }
 242
 243         /*
 244          * FIXME: we currently manage device-specific idle states
 245          *        for PER and CORE in combination with CPU-specific
 246          *        idle states.  This is wrong, and device-specific
 247          *        idle management needs to be separated out into
 248          *        its own code.
 249          */
 250
 251         /*
 252          * Prevent PER off if CORE is not in retention or off as this
 253          * would disable PER wakeups completely.
 254          */
 255         cx = &omap3_idle_data[index];
 256         core_next_state = cx->core_state;
 257         per_next_state = per_saved_state = pwrdm_read_next_pwrst(per_pd);
 258         if ((per_next_state == PWRDM_POWER_OFF) &&
 259             (core_next_state > PWRDM_POWER_RET))
 260                 per_next_state = PWRDM_POWER_RET;
 261
 262         /* Are we changing PER target state? */
 263         if (per_next_state != per_saved_state)
 264                 pwrdm_set_next_pwrst(per_pd, per_next_state);
 265
 266         new_state_idx = next_valid_state(dev, drv, index);
 267
 268 select_state:
 269         ret = omap3_enter_idle(dev, drv, new_state_idx);
 270
 271         /* Restore original PER state if it was modified */
 272         if (per_next_state != per_saved_state)
 273                 pwrdm_set_next_pwrst(per_pd, per_saved_state);
 274
 275         return ret;
 276 }
 277
 278 DEFINE_PER_CPU(struct cpuidle_device, omap3_idle_dev);
 279
 280 struct cpuidle_driver omap3_idle_driver = {
 281         .name =         "omap3_idle",
 282         .owner =        THIS_MODULE,
 283         .states = {
 284                 {
 285                         .enter            = omap3_enter_idle,
 286                         .exit_latency     = 2 + 2,
 287                         .target_residency = 5,
 288                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 289                         .name             = "C1",
 290                         .desc             = "MPU ON + CORE ON",
 291                 },
 292                 {
 293                         .enter            = omap3_enter_idle_bm,
 294                         .exit_latency     = 10 + 10,
 295                         .target_residency = 30,
 296                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 297                         .name             = "C2",
 298                         .desc             = "MPU ON + CORE ON",
 299                 },
 300                 {
 301                         .enter            = omap3_enter_idle_bm,
 302                         .exit_latency     = 50 + 50,
 303                         .target_residency = 300,
 304                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 305                         .name             = "C3",
 306                         .desc             = "MPU RET + CORE ON",
 307                 },
 308                 {
 309                         .enter            = omap3_enter_idle_bm,
 310                         .exit_latency     = 1500 + 1800,
 311                         .target_residency = 4000,
 312                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 313                         .name             = "C4",
 314                         .desc             = "MPU OFF + CORE ON",
 315                 },
 316                 {
 317                         .enter            = omap3_enter_idle_bm,
 318                         .exit_latency     = 2500 + 7500,
 319                         .target_residency = 12000,
 320                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 321                         .name             = "C5",
 322                         .desc             = "MPU RET + CORE RET",
 323                 },
 324                 {
 325                         .enter            = omap3_enter_idle_bm,
 326                         .exit_latency     = 3000 + 8500,
 327                         .target_residency = 15000,
 328                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 329                         .name             = "C6",
 330                         .desc             = "MPU OFF + CORE RET",
 331                 },
 332                 {
 333                         .enter            = omap3_enter_idle_bm,
 334                         .exit_latency     = 10000 + 30000,
 335                         .target_residency = 30000,
 336                         .flags            = CPUIDLE_FLAG_TIME_VALID,
 337                         .name             = "C7",
 338                         .desc             = "MPU OFF + CORE OFF",
 339                 },
 340         },
 341         .state_count = ARRAY_SIZE(omap3_idle_data),
 342         .safe_state_index = 0,
 343 };
 344
 345 /**
 346  * omap3_idle_init - Init routine for OMAP3 idle
 347  *
 348  * Registers the OMAP3 specific cpuidle driver to the cpuidle
 349  * framework with the valid set of states.
 350  */
 351 int __init omap3_idle_init(void)
 352 {
 353         struct cpuidle_device *dev;
 354
 355         mpu_pd = pwrdm_lookup("mpu_pwrdm");
 356         core_pd = pwrdm_lookup("core_pwrdm");
 357         per_pd = pwrdm_lookup("per_pwrdm");
 358         cam_pd = pwrdm_lookup("cam_pwrdm");
 359
 360         if (!mpu_pd || !core_pd || !per_pd || !cam_pd)
 361                 return -ENODEV;
 362
 363         cpuidle_register_driver(&omap3_idle_driver);
 364
 365         dev = &per_cpu(omap3_idle_dev, smp_processor_id());
 366         dev->cpu = 0;
 367
 368         if (cpuidle_register_device(dev)) {
 369                 printk(KERN_ERR "%s: CPUidle register device failed\n",
 370                        __func__);
 371                 return -EIO;
 372         }
 373
 374         return 0;
 375 }
 376 #else
 377 int __init omap3_idle_init(void)
 378 {
 379         return 0;
 380 }
 381 #endif /* CONFIG_CPU_IDLE */