drivers/gpu/drm/radeon/radeon_kms.c

   1 /*
   2  * Copyright 2008 Advanced Micro Devices, Inc.
   3  * Copyright 2008 Red Hat Inc.
   4  * Copyright 2009 Jerome Glisse.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the "Software"),
   8  * to deal in the Software without restriction, including without limitation
   9  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10  * and/or sell copies of the Software, and to permit persons to whom the
  11  * Software is furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  19  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22  * OTHER DEALINGS IN THE SOFTWARE.
  23  *
  24  * Authors: Dave Airlie
  25  *          Alex Deucher
  26  *          Jerome Glisse
  27  */
  28 #include <drm/drmP.h>
  29 #include "radeon.h"
  30 #include <drm/radeon_drm.h>
  31 #include "radeon_asic.h"
  32
  33 #include <linux/vga_switcheroo.h>
  34 #include <linux/slab.h>
  35
  36 /**
  37  * radeon_driver_unload_kms - Main unload function for KMS.
  38  *
  39  * @dev: drm dev pointer
  40  *
  41  * This is the main unload function for KMS (all asics).
  42  * It calls radeon_modeset_fini() to tear down the
  43  * displays, and radeon_device_fini() to tear down
  44  * the rest of the device (CP, writeback, etc.).
  45  * Returns 0 on success.
  46  */
  47 int radeon_driver_unload_kms(struct drm_device *dev)
  48 {
  49         struct radeon_device *rdev = dev->dev_private;
  50
  51         if (rdev == NULL)
  52                 return 0;
  53         radeon_acpi_fini(rdev);
  54         radeon_modeset_fini(rdev);
  55         radeon_device_fini(rdev);
  56         kfree(rdev);
  57         dev->dev_private = NULL;
  58         return 0;
  59 }
  60
  61 /**
  62  * radeon_driver_load_kms - Main load function for KMS.
  63  *
  64  * @dev: drm dev pointer
  65  * @flags: device flags
  66  *
  67  * This is the main load function for KMS (all asics).
  68  * It calls radeon_device_init() to set up the non-display
  69  * parts of the chip (asic init, CP, writeback, etc.), and
  70  * radeon_modeset_init() to set up the display parts
  71  * (crtcs, encoders, hotplug detect, etc.).
  72  * Returns 0 on success, error on failure.
  73  */
  74 int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags)
  75 {
  76         struct radeon_device *rdev;
  77         int r, acpi_status;
  78
  79         rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL);
  80         if (rdev == NULL) {
  81                 return -ENOMEM;
  82         }
  83         dev->dev_private = (void *)rdev;
  84
  85         /* update BUS flag */
  86         if (drm_pci_device_is_agp(dev)) {
  87                 flags |= RADEON_IS_AGP;
  88         } else if (pci_is_pcie(dev->pdev)) {
  89                 flags |= RADEON_IS_PCIE;
  90         } else {
  91                 flags |= RADEON_IS_PCI;
  92         }
  93
  94         /* radeon_device_init should report only fatal error
  95          * like memory allocation failure or iomapping failure,
  96          * or memory manager initialization failure, it must
  97          * properly initialize the GPU MC controller and permit
  98          * VRAM allocation
  99          */
 100         r = radeon_device_init(rdev, dev, dev->pdev, flags);
 101         if (r) {
 102                 dev_err(&dev->pdev->dev, "Fatal error during GPU init\n");
 103                 goto out;
 104         }
 105
 106         /* Again modeset_init should fail only on fatal error
 107          * otherwise it should provide enough functionalities
 108          * for shadowfb to run
 109          */
 110         r = radeon_modeset_init(rdev);
 111         if (r)
 112                 dev_err(&dev->pdev->dev, "Fatal error during modeset init\n");
 113
 114         /* Call ACPI methods: require modeset init
 115          * but failure is not fatal
 116          */
 117         if (!r) {
 118                 acpi_status = radeon_acpi_init(rdev);
 119                 if (acpi_status)
 120                 dev_dbg(&dev->pdev->dev,
 121                                 "Error during ACPI methods call\n");
 122         }
 123
 124 out:
 125         if (r)
 126                 radeon_driver_unload_kms(dev);
 127         return r;
 128 }
 129
 130 /**
 131  * radeon_set_filp_rights - Set filp right.
 132  *
 133  * @dev: drm dev pointer
 134  * @owner: drm file
 135  * @applier: drm file
 136  * @value: value
 137  *
 138  * Sets the filp rights for the device (all asics).
 139  */
 140 static void radeon_set_filp_rights(struct drm_device *dev,
 141                                    struct drm_file **owner,
 142                                    struct drm_file *applier,
 143                                    uint32_t *value)
 144 {
 145         mutex_lock(&dev->struct_mutex);
 146         if (*value == 1) {
 147                 /* wants rights */
 148                 if (!*owner)
 149                         *owner = applier;
 150         } else if (*value == 0) {
 151                 /* revokes rights */
 152                 if (*owner == applier)
 153                         *owner = NULL;
 154         }
 155         *value = *owner == applier ? 1 : 0;
 156         mutex_unlock(&dev->struct_mutex);
 157 }
 158
 159 /*
 160  * Userspace get information ioctl
 161  */
 162 /**
 163  * radeon_info_ioctl - answer a device specific request.
 164  *
 165  * @rdev: radeon device pointer
 166  * @data: request object
 167  * @filp: drm filp
 168  *
 169  * This function is used to pass device specific parameters to the userspace
 170  * drivers.  Examples include: pci device id, pipeline parms, tiling params,
 171  * etc. (all asics).
 172  * Returns 0 on success, -EINVAL on failure.
 173  */
 174 int radeon_info_ioctl(struct drm_device *dev, void *data, struct drm_file *filp)
 175 {
 176         struct radeon_device *rdev = dev->dev_private;
 177         struct drm_radeon_info *info = data;
 178         struct radeon_mode_info *minfo = &rdev->mode_info;
 179         uint32_t value, *value_ptr;
 180         uint64_t value64, *value_ptr64;
 181         struct drm_crtc *crtc;
 182         int i, found;
 183
 184         /* TIMESTAMP is a 64-bit value, needs special handling. */
 185         if (info->request == RADEON_INFO_TIMESTAMP) {
 186                 if (rdev->family >= CHIP_R600) {
 187                         value_ptr64 = (uint64_t*)((unsigned long)info->value);
 188                         value64 = radeon_get_gpu_clock_counter(rdev);
 189
 190                         if (DRM_COPY_TO_USER(value_ptr64, &value64, sizeof(value64))) {
 191                                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 192                                 return -EFAULT;
 193                         }
 194                         return 0;
 195                 } else {
 196                         DRM_DEBUG_KMS("timestamp is r6xx+ only!\n");
 197                         return -EINVAL;
 198                 }
 199         }
 200
 201         value_ptr = (uint32_t *)((unsigned long)info->value);
 202         if (DRM_COPY_FROM_USER(&value, value_ptr, sizeof(value))) {
 203                 DRM_ERROR("copy_from_user %s:%u\n", __func__, __LINE__);
 204                 return -EFAULT;
 205         }
 206
 207         switch (info->request) {
 208         case RADEON_INFO_DEVICE_ID:
 209                 value = dev->pci_device;
 210                 break;
 211         case RADEON_INFO_NUM_GB_PIPES:
 212                 value = rdev->num_gb_pipes;
 213                 break;
 214         case RADEON_INFO_NUM_Z_PIPES:
 215                 value = rdev->num_z_pipes;
 216                 break;
 217         case RADEON_INFO_ACCEL_WORKING:
 218                 /* xf86-video-ati 6.13.0 relies on this being false for evergreen */
 219                 if ((rdev->family >= CHIP_CEDAR) && (rdev->family <= CHIP_HEMLOCK))
 220                         value = false;
 221                 else
 222                         value = rdev->accel_working;
 223                 break;
 224         case RADEON_INFO_CRTC_FROM_ID:
 225                 for (i = 0, found = 0; i < rdev->num_crtc; i++) {
 226                         crtc = (struct drm_crtc *)minfo->crtcs[i];
 227                         if (crtc && crtc->base.id == value) {
 228                                 struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc);
 229                                 value = radeon_crtc->crtc_id;
 230                                 found = 1;
 231                                 break;
 232                         }
 233                 }
 234                 if (!found) {
 235                         DRM_DEBUG_KMS("unknown crtc id %d\n", value);
 236                         return -EINVAL;
 237                 }
 238                 break;
 239         case RADEON_INFO_ACCEL_WORKING2:
 240                 value = rdev->accel_working;
 241                 break;
 242         case RADEON_INFO_TILING_CONFIG:
 243                 if (rdev->family >= CHIP_TAHITI)
 244                         value = rdev->config.si.tile_config;
 245                 else if (rdev->family >= CHIP_CAYMAN)
 246                         value = rdev->config.cayman.tile_config;
 247                 else if (rdev->family >= CHIP_CEDAR)
 248                         value = rdev->config.evergreen.tile_config;
 249                 else if (rdev->family >= CHIP_RV770)
 250                         value = rdev->config.rv770.tile_config;
 251                 else if (rdev->family >= CHIP_R600)
 252                         value = rdev->config.r600.tile_config;
 253                 else {
 254                         DRM_DEBUG_KMS("tiling config is r6xx+ only!\n");
 255                         return -EINVAL;
 256                 }
 257                 break;
 258         case RADEON_INFO_WANT_HYPERZ:
 259                 /* The "value" here is both an input and output parameter.
 260                  * If the input value is 1, filp requests hyper-z access.
 261                  * If the input value is 0, filp revokes its hyper-z access.
 262                  *
 263                  * When returning, the value is 1 if filp owns hyper-z access,
 264                  * 0 otherwise. */
 265                 if (value >= 2) {
 266                         DRM_DEBUG_KMS("WANT_HYPERZ: invalid value %d\n", value);
 267                         return -EINVAL;
 268                 }
 269                 radeon_set_filp_rights(dev, &rdev->hyperz_filp, filp, &value);
 270                 break;
 271         case RADEON_INFO_WANT_CMASK:
 272                 /* The same logic as Hyper-Z. */
 273                 if (value >= 2) {
 274                         DRM_DEBUG_KMS("WANT_CMASK: invalid value %d\n", value);
 275                         return -EINVAL;
 276                 }
 277                 radeon_set_filp_rights(dev, &rdev->cmask_filp, filp, &value);
 278                 break;
 279         case RADEON_INFO_CLOCK_CRYSTAL_FREQ:
 280                 /* return clock value in KHz */
 281                 if (rdev->asic->get_xclk)
 282                         value = radeon_get_xclk(rdev) * 10;
 283                 else
 284                         value = rdev->clock.spll.reference_freq * 10;
 285                 break;
 286         case RADEON_INFO_NUM_BACKENDS:
 287                 if (rdev->family >= CHIP_TAHITI)
 288                         value = rdev->config.si.max_backends_per_se *
 289                                 rdev->config.si.max_shader_engines;
 290                 else if (rdev->family >= CHIP_CAYMAN)
 291                         value = rdev->config.cayman.max_backends_per_se *
 292                                 rdev->config.cayman.max_shader_engines;
 293                 else if (rdev->family >= CHIP_CEDAR)
 294                         value = rdev->config.evergreen.max_backends;
 295                 else if (rdev->family >= CHIP_RV770)
 296                         value = rdev->config.rv770.max_backends;
 297                 else if (rdev->family >= CHIP_R600)
 298                         value = rdev->config.r600.max_backends;
 299                 else {
 300                         return -EINVAL;
 301                 }
 302                 break;
 303         case RADEON_INFO_NUM_TILE_PIPES:
 304                 if (rdev->family >= CHIP_TAHITI)
 305                         value = rdev->config.si.max_tile_pipes;
 306                 else if (rdev->family >= CHIP_CAYMAN)
 307                         value = rdev->config.cayman.max_tile_pipes;
 308                 else if (rdev->family >= CHIP_CEDAR)
 309                         value = rdev->config.evergreen.max_tile_pipes;
 310                 else if (rdev->family >= CHIP_RV770)
 311                         value = rdev->config.rv770.max_tile_pipes;
 312                 else if (rdev->family >= CHIP_R600)
 313                         value = rdev->config.r600.max_tile_pipes;
 314                 else {
 315                         return -EINVAL;
 316                 }
 317                 break;
 318         case RADEON_INFO_FUSION_GART_WORKING:
 319                 value = 1;
 320                 break;
 321         case RADEON_INFO_BACKEND_MAP:
 322                 if (rdev->family >= CHIP_TAHITI)
 323                         value = rdev->config.si.backend_map;
 324                 else if (rdev->family >= CHIP_CAYMAN)
 325                         value = rdev->config.cayman.backend_map;
 326                 else if (rdev->family >= CHIP_CEDAR)
 327                         value = rdev->config.evergreen.backend_map;
 328                 else if (rdev->family >= CHIP_RV770)
 329                         value = rdev->config.rv770.backend_map;
 330                 else if (rdev->family >= CHIP_R600)
 331                         value = rdev->config.r600.backend_map;
 332                 else {
 333                         return -EINVAL;
 334                 }
 335                 break;
 336         case RADEON_INFO_VA_START:
 337                 /* this is where we report if vm is supported or not */
 338                 if (rdev->family < CHIP_CAYMAN)
 339                         return -EINVAL;
 340                 value = RADEON_VA_RESERVED_SIZE;
 341                 break;
 342         case RADEON_INFO_IB_VM_MAX_SIZE:
 343                 /* this is where we report if vm is supported or not */
 344                 if (rdev->family < CHIP_CAYMAN)
 345                         return -EINVAL;
 346                 value = RADEON_IB_VM_MAX_SIZE;
 347                 break;
 348         case RADEON_INFO_MAX_PIPES:
 349                 if (rdev->family >= CHIP_TAHITI)
 350                         value = rdev->config.si.max_cu_per_sh;
 351                 else if (rdev->family >= CHIP_CAYMAN)
 352                         value = rdev->config.cayman.max_pipes_per_simd;
 353                 else if (rdev->family >= CHIP_CEDAR)
 354                         value = rdev->config.evergreen.max_pipes;
 355                 else if (rdev->family >= CHIP_RV770)
 356                         value = rdev->config.rv770.max_pipes;
 357                 else if (rdev->family >= CHIP_R600)
 358                         value = rdev->config.r600.max_pipes;
 359                 else {
 360                         return -EINVAL;
 361                 }
 362                 break;
 363         case RADEON_INFO_MAX_SE:
 364                 if (rdev->family >= CHIP_TAHITI)
 365                         value = rdev->config.si.max_shader_engines;
 366                 else if (rdev->family >= CHIP_CAYMAN)
 367                         value = rdev->config.cayman.max_shader_engines;
 368                 else if (rdev->family >= CHIP_CEDAR)
 369                         value = rdev->config.evergreen.num_ses;
 370                 else
 371                         value = 1;
 372                 break;
 373         case RADEON_INFO_MAX_SH_PER_SE:
 374                 if (rdev->family >= CHIP_TAHITI)
 375                         value = rdev->config.si.max_sh_per_se;
 376                 else
 377                         return -EINVAL;
 378                 break;
 379         case RADEON_INFO_FASTFB_WORKING:
 380                 value = rdev->fastfb_working;
 381                 break;
 382         default:
 383                 DRM_DEBUG_KMS("Invalid request %d\n", info->request);
 384                 return -EINVAL;
 385         }
 386         if (DRM_COPY_TO_USER(value_ptr, &value, sizeof(uint32_t))) {
 387                 DRM_ERROR("copy_to_user %s:%u\n", __func__, __LINE__);
 388                 return -EFAULT;
 389         }
 390         return 0;
 391 }
 392
 393
 394 /*
 395  * Outdated mess for old drm with Xorg being in charge (void function now).
 396  */
 397 /**
 398  * radeon_driver_firstopen_kms - drm callback for first open
 399  *
 400  * @dev: drm dev pointer
 401  *
 402  * Nothing to be done for KMS (all asics).
 403  * Returns 0 on success.
 404  */
 405 int radeon_driver_firstopen_kms(struct drm_device *dev)
 406 {
 407         return 0;
 408 }
 409
 410 /**
 411  * radeon_driver_firstopen_kms - drm callback for last close
 412  *
 413  * @dev: drm dev pointer
 414  *
 415  * Switch vga switcheroo state after last close (all asics).
 416  */
 417 void radeon_driver_lastclose_kms(struct drm_device *dev)
 418 {
 419         vga_switcheroo_process_delayed_switch();
 420 }
 421
 422 /**
 423  * radeon_driver_open_kms - drm callback for open
 424  *
 425  * @dev: drm dev pointer
 426  * @file_priv: drm file
 427  *
 428  * On device open, init vm on cayman+ (all asics).
 429  * Returns 0 on success, error on failure.
 430  */
 431 int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv)
 432 {
 433         struct radeon_device *rdev = dev->dev_private;
 434
 435         file_priv->driver_priv = NULL;
 436
 437         /* new gpu have virtual address space support */
 438         if (rdev->family >= CHIP_CAYMAN) {
 439                 struct radeon_fpriv *fpriv;
 440                 struct radeon_bo_va *bo_va;
 441                 int r;
 442
 443                 fpriv = kzalloc(sizeof(*fpriv), GFP_KERNEL);
 444                 if (unlikely(!fpriv)) {
 445                         return -ENOMEM;
 446                 }
 447
 448                 radeon_vm_init(rdev, &fpriv->vm);
 449
 450                 /* map the ib pool buffer read only into
 451                  * virtual address space */
 452                 bo_va = radeon_vm_bo_add(rdev, &fpriv->vm,
 453                                          rdev->ring_tmp_bo.bo);
 454                 r = radeon_vm_bo_set_addr(rdev, bo_va, RADEON_VA_IB_OFFSET,
 455                                           RADEON_VM_PAGE_READABLE |
 456                                           RADEON_VM_PAGE_SNOOPED);
 457                 if (r) {
 458                         radeon_vm_fini(rdev, &fpriv->vm);
 459                         kfree(fpriv);
 460                         return r;
 461                 }
 462
 463                 file_priv->driver_priv = fpriv;
 464         }
 465         return 0;
 466 }
 467
 468 /**
 469  * radeon_driver_postclose_kms - drm callback for post close
 470  *
 471  * @dev: drm dev pointer
 472  * @file_priv: drm file
 473  *
 474  * On device post close, tear down vm on cayman+ (all asics).
 475  */
 476 void radeon_driver_postclose_kms(struct drm_device *dev,
 477                                  struct drm_file *file_priv)
 478 {
 479         struct radeon_device *rdev = dev->dev_private;
 480
 481         /* new gpu have virtual address space support */
 482         if (rdev->family >= CHIP_CAYMAN && file_priv->driver_priv) {
 483                 struct radeon_fpriv *fpriv = file_priv->driver_priv;
 484                 struct radeon_bo_va *bo_va;
 485                 int r;
 486
 487                 r = radeon_bo_reserve(rdev->ring_tmp_bo.bo, false);
 488                 if (!r) {
 489                         bo_va = radeon_vm_bo_find(&fpriv->vm,
 490                                                   rdev->ring_tmp_bo.bo);
 491                         if (bo_va)
 492                                 radeon_vm_bo_rmv(rdev, bo_va);
 493                         radeon_bo_unreserve(rdev->ring_tmp_bo.bo);
 494                 }
 495
 496                 radeon_vm_fini(rdev, &fpriv->vm);
 497                 kfree(fpriv);
 498                 file_priv->driver_priv = NULL;
 499         }
 500 }
 501
 502 /**
 503  * radeon_driver_preclose_kms - drm callback for pre close
 504  *
 505  * @dev: drm dev pointer
 506  * @file_priv: drm file
 507  *
 508  * On device pre close, tear down hyperz and cmask filps on r1xx-r5xx
 509  * (all asics).
 510  */
 511 void radeon_driver_preclose_kms(struct drm_device *dev,
 512                                 struct drm_file *file_priv)
 513 {
 514         struct radeon_device *rdev = dev->dev_private;
 515         if (rdev->hyperz_filp == file_priv)
 516                 rdev->hyperz_filp = NULL;
 517         if (rdev->cmask_filp == file_priv)
 518                 rdev->cmask_filp = NULL;
 519 }
 520
 521 /*
 522  * VBlank related functions.
 523  */
 524 /**
 525  * radeon_get_vblank_counter_kms - get frame count
 526  *
 527  * @dev: drm dev pointer
 528  * @crtc: crtc to get the frame count from
 529  *
 530  * Gets the frame count on the requested crtc (all asics).
 531  * Returns frame count on success, -EINVAL on failure.
 532  */
 533 u32 radeon_get_vblank_counter_kms(struct drm_device *dev, int crtc)
 534 {
 535         struct radeon_device *rdev = dev->dev_private;
 536
 537         if (crtc < 0 || crtc >= rdev->num_crtc) {
 538                 DRM_ERROR("Invalid crtc %d\n", crtc);
 539                 return -EINVAL;
 540         }
 541
 542         return radeon_get_vblank_counter(rdev, crtc);
 543 }
 544
 545 /**
 546  * radeon_enable_vblank_kms - enable vblank interrupt
 547  *
 548  * @dev: drm dev pointer
 549  * @crtc: crtc to enable vblank interrupt for
 550  *
 551  * Enable the interrupt on the requested crtc (all asics).
 552  * Returns 0 on success, -EINVAL on failure.
 553  */
 554 int radeon_enable_vblank_kms(struct drm_device *dev, int crtc)
 555 {
 556         struct radeon_device *rdev = dev->dev_private;
 557         unsigned long irqflags;
 558         int r;
 559
 560         if (crtc < 0 || crtc >= rdev->num_crtc) {
 561                 DRM_ERROR("Invalid crtc %d\n", crtc);
 562                 return -EINVAL;
 563         }
 564
 565         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 566         rdev->irq.crtc_vblank_int[crtc] = true;
 567         r = radeon_irq_set(rdev);
 568         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 569         return r;
 570 }
 571
 572 /**
 573  * radeon_disable_vblank_kms - disable vblank interrupt
 574  *
 575  * @dev: drm dev pointer
 576  * @crtc: crtc to disable vblank interrupt for
 577  *
 578  * Disable the interrupt on the requested crtc (all asics).
 579  */
 580 void radeon_disable_vblank_kms(struct drm_device *dev, int crtc)
 581 {
 582         struct radeon_device *rdev = dev->dev_private;
 583         unsigned long irqflags;
 584
 585         if (crtc < 0 || crtc >= rdev->num_crtc) {
 586                 DRM_ERROR("Invalid crtc %d\n", crtc);
 587                 return;
 588         }
 589
 590         spin_lock_irqsave(&rdev->irq.lock, irqflags);
 591         rdev->irq.crtc_vblank_int[crtc] = false;
 592         radeon_irq_set(rdev);
 593         spin_unlock_irqrestore(&rdev->irq.lock, irqflags);
 594 }
 595
 596 /**
 597  * radeon_get_vblank_timestamp_kms - get vblank timestamp
 598  *
 599  * @dev: drm dev pointer
 600  * @crtc: crtc to get the timestamp for
 601  * @max_error: max error
 602  * @vblank_time: time value
 603  * @flags: flags passed to the driver
 604  *
 605  * Gets the timestamp on the requested crtc based on the
 606  * scanout position.  (all asics).
 607  * Returns postive status flags on success, negative error on failure.
 608  */
 609 int radeon_get_vblank_timestamp_kms(struct drm_device *dev, int crtc,
 610                                     int *max_error,
 611                                     struct timeval *vblank_time,
 612                                     unsigned flags)
 613 {
 614         struct drm_crtc *drmcrtc;
 615         struct radeon_device *rdev = dev->dev_private;
 616
 617         if (crtc < 0 || crtc >= dev->num_crtcs) {
 618                 DRM_ERROR("Invalid crtc %d\n", crtc);
 619                 return -EINVAL;
 620         }
 621
 622         /* Get associated drm_crtc: */
 623         drmcrtc = &rdev->mode_info.crtcs[crtc]->base;
 624
 625         /* Helper routine in DRM core does all the work: */
 626         return drm_calc_vbltimestamp_from_scanoutpos(dev, crtc, max_error,
 627                                                      vblank_time, flags,
 628                                                      drmcrtc);
 629 }
 630
 631 /*
 632  * IOCTL.
 633  */
 634 int radeon_dma_ioctl_kms(struct drm_device *dev, void *data,
 635                          struct drm_file *file_priv)
 636 {
 637         /* Not valid in KMS. */
 638         return -EINVAL;
 639 }
 640
 641 #define KMS_INVALID_IOCTL(name)                                         \
 642 int name(struct drm_device *dev, void *data, struct drm_file *file_priv)\
 643 {                                                                       \
 644         DRM_ERROR("invalid ioctl with kms %s\n", __func__);             \
 645         return -EINVAL;                                                 \
 646 }
 647
 648 /*
 649  * All these ioctls are invalid in kms world.
 650  */
 651 KMS_INVALID_IOCTL(radeon_cp_init_kms)
 652 KMS_INVALID_IOCTL(radeon_cp_start_kms)
 653 KMS_INVALID_IOCTL(radeon_cp_stop_kms)
 654 KMS_INVALID_IOCTL(radeon_cp_reset_kms)
 655 KMS_INVALID_IOCTL(radeon_cp_idle_kms)
 656 KMS_INVALID_IOCTL(radeon_cp_resume_kms)
 657 KMS_INVALID_IOCTL(radeon_engine_reset_kms)
 658 KMS_INVALID_IOCTL(radeon_fullscreen_kms)
 659 KMS_INVALID_IOCTL(radeon_cp_swap_kms)
 660 KMS_INVALID_IOCTL(radeon_cp_clear_kms)
 661 KMS_INVALID_IOCTL(radeon_cp_vertex_kms)
 662 KMS_INVALID_IOCTL(radeon_cp_indices_kms)
 663 KMS_INVALID_IOCTL(radeon_cp_texture_kms)
 664 KMS_INVALID_IOCTL(radeon_cp_stipple_kms)
 665 KMS_INVALID_IOCTL(radeon_cp_indirect_kms)
 666 KMS_INVALID_IOCTL(radeon_cp_vertex2_kms)
 667 KMS_INVALID_IOCTL(radeon_cp_cmdbuf_kms)
 668 KMS_INVALID_IOCTL(radeon_cp_getparam_kms)
 669 KMS_INVALID_IOCTL(radeon_cp_flip_kms)
 670 KMS_INVALID_IOCTL(radeon_mem_alloc_kms)
 671 KMS_INVALID_IOCTL(radeon_mem_free_kms)
 672 KMS_INVALID_IOCTL(radeon_mem_init_heap_kms)
 673 KMS_INVALID_IOCTL(radeon_irq_emit_kms)
 674 KMS_INVALID_IOCTL(radeon_irq_wait_kms)
 675 KMS_INVALID_IOCTL(radeon_cp_setparam_kms)
 676 KMS_INVALID_IOCTL(radeon_surface_alloc_kms)
 677 KMS_INVALID_IOCTL(radeon_surface_free_kms)
 678
 679
 680 struct drm_ioctl_desc radeon_ioctls_kms[] = {
 681         DRM_IOCTL_DEF_DRV(RADEON_CP_INIT, radeon_cp_init_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 682         DRM_IOCTL_DEF_DRV(RADEON_CP_START, radeon_cp_start_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 683         DRM_IOCTL_DEF_DRV(RADEON_CP_STOP, radeon_cp_stop_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 684         DRM_IOCTL_DEF_DRV(RADEON_CP_RESET, radeon_cp_reset_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 685         DRM_IOCTL_DEF_DRV(RADEON_CP_IDLE, radeon_cp_idle_kms, DRM_AUTH),
 686         DRM_IOCTL_DEF_DRV(RADEON_CP_RESUME, radeon_cp_resume_kms, DRM_AUTH),
 687         DRM_IOCTL_DEF_DRV(RADEON_RESET, radeon_engine_reset_kms, DRM_AUTH),
 688         DRM_IOCTL_DEF_DRV(RADEON_FULLSCREEN, radeon_fullscreen_kms, DRM_AUTH),
 689         DRM_IOCTL_DEF_DRV(RADEON_SWAP, radeon_cp_swap_kms, DRM_AUTH),
 690         DRM_IOCTL_DEF_DRV(RADEON_CLEAR, radeon_cp_clear_kms, DRM_AUTH),
 691         DRM_IOCTL_DEF_DRV(RADEON_VERTEX, radeon_cp_vertex_kms, DRM_AUTH),
 692         DRM_IOCTL_DEF_DRV(RADEON_INDICES, radeon_cp_indices_kms, DRM_AUTH),
 693         DRM_IOCTL_DEF_DRV(RADEON_TEXTURE, radeon_cp_texture_kms, DRM_AUTH),
 694         DRM_IOCTL_DEF_DRV(RADEON_STIPPLE, radeon_cp_stipple_kms, DRM_AUTH),
 695         DRM_IOCTL_DEF_DRV(RADEON_INDIRECT, radeon_cp_indirect_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 696         DRM_IOCTL_DEF_DRV(RADEON_VERTEX2, radeon_cp_vertex2_kms, DRM_AUTH),
 697         DRM_IOCTL_DEF_DRV(RADEON_CMDBUF, radeon_cp_cmdbuf_kms, DRM_AUTH),
 698         DRM_IOCTL_DEF_DRV(RADEON_GETPARAM, radeon_cp_getparam_kms, DRM_AUTH),
 699         DRM_IOCTL_DEF_DRV(RADEON_FLIP, radeon_cp_flip_kms, DRM_AUTH),
 700         DRM_IOCTL_DEF_DRV(RADEON_ALLOC, radeon_mem_alloc_kms, DRM_AUTH),
 701         DRM_IOCTL_DEF_DRV(RADEON_FREE, radeon_mem_free_kms, DRM_AUTH),
 702         DRM_IOCTL_DEF_DRV(RADEON_INIT_HEAP, radeon_mem_init_heap_kms, DRM_AUTH|DRM_MASTER|DRM_ROOT_ONLY),
 703         DRM_IOCTL_DEF_DRV(RADEON_IRQ_EMIT, radeon_irq_emit_kms, DRM_AUTH),
 704         DRM_IOCTL_DEF_DRV(RADEON_IRQ_WAIT, radeon_irq_wait_kms, DRM_AUTH),
 705         DRM_IOCTL_DEF_DRV(RADEON_SETPARAM, radeon_cp_setparam_kms, DRM_AUTH),
 706         DRM_IOCTL_DEF_DRV(RADEON_SURF_ALLOC, radeon_surface_alloc_kms, DRM_AUTH),
 707         DRM_IOCTL_DEF_DRV(RADEON_SURF_FREE, radeon_surface_free_kms, DRM_AUTH),
 708         /* KMS */
 709         DRM_IOCTL_DEF_DRV(RADEON_GEM_INFO, radeon_gem_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 710         DRM_IOCTL_DEF_DRV(RADEON_GEM_CREATE, radeon_gem_create_ioctl, DRM_AUTH|DRM_UNLOCKED),
 711         DRM_IOCTL_DEF_DRV(RADEON_GEM_MMAP, radeon_gem_mmap_ioctl, DRM_AUTH|DRM_UNLOCKED),
 712         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_DOMAIN, radeon_gem_set_domain_ioctl, DRM_AUTH|DRM_UNLOCKED),
 713         DRM_IOCTL_DEF_DRV(RADEON_GEM_PREAD, radeon_gem_pread_ioctl, DRM_AUTH|DRM_UNLOCKED),
 714         DRM_IOCTL_DEF_DRV(RADEON_GEM_PWRITE, radeon_gem_pwrite_ioctl, DRM_AUTH|DRM_UNLOCKED),
 715         DRM_IOCTL_DEF_DRV(RADEON_GEM_WAIT_IDLE, radeon_gem_wait_idle_ioctl, DRM_AUTH|DRM_UNLOCKED),
 716         DRM_IOCTL_DEF_DRV(RADEON_CS, radeon_cs_ioctl, DRM_AUTH|DRM_UNLOCKED),
 717         DRM_IOCTL_DEF_DRV(RADEON_INFO, radeon_info_ioctl, DRM_AUTH|DRM_UNLOCKED),
 718         DRM_IOCTL_DEF_DRV(RADEON_GEM_SET_TILING, radeon_gem_set_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 719         DRM_IOCTL_DEF_DRV(RADEON_GEM_GET_TILING, radeon_gem_get_tiling_ioctl, DRM_AUTH|DRM_UNLOCKED),
 720         DRM_IOCTL_DEF_DRV(RADEON_GEM_BUSY, radeon_gem_busy_ioctl, DRM_AUTH|DRM_UNLOCKED),
 721         DRM_IOCTL_DEF_DRV(RADEON_GEM_VA, radeon_gem_va_ioctl, DRM_AUTH|DRM_UNLOCKED),
 722 };
 723 int radeon_max_kms_ioctl = DRM_ARRAY_SIZE(radeon_ioctls_kms);