drivers/gpu/drm/radeon/radeon_pm.c

   1 /*
   2  * Permission is hereby granted, free of charge, to any person obtaining a
   3  * copy of this software and associated documentation files (the "Software"),
   4  * to deal in the Software without restriction, including without limitation
   5  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   6  * and/or sell copies of the Software, and to permit persons to whom the
   7  * Software is furnished to do so, subject to the following conditions:
   8  *
   9  * The above copyright notice and this permission notice shall be included in
  10  * all copies or substantial portions of the Software.
  11  *
  12  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  13  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  14  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  15  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  16  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  17  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  18  * OTHER DEALINGS IN THE SOFTWARE.
  19  *
  20  * Authors: Rafał Miłecki <zajec5@gmail.com>
  21  *          Alex Deucher <alexdeucher@gmail.com>
  22  */
  23 #include <drm/drmP.h>
  24 #include "radeon.h"
  25 #include "avivod.h"
  26 #include "atom.h"
  27 #include <linux/power_supply.h>
  28 #include <linux/hwmon.h>
  29 #include <linux/hwmon-sysfs.h>
  30
  31 #define RADEON_IDLE_LOOP_MS 100
  32 #define RADEON_RECLOCK_DELAY_MS 200
  33 #define RADEON_WAIT_VBLANK_TIMEOUT 200
  34
  35 static const char *radeon_pm_state_type_name[5] = {
  36         "",
  37         "Powersave",
  38         "Battery",
  39         "Balanced",
  40         "Performance",
  41 };
  42
  43 static void radeon_dynpm_idle_work_handler(struct work_struct *work);
  44 static int radeon_debugfs_pm_init(struct radeon_device *rdev);
  45 static bool radeon_pm_in_vbl(struct radeon_device *rdev);
  46 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish);
  47 static void radeon_pm_update_profile(struct radeon_device *rdev);
  48 static void radeon_pm_set_clocks(struct radeon_device *rdev);
  49
  50 int radeon_pm_get_type_index(struct radeon_device *rdev,
  51                              enum radeon_pm_state_type ps_type,
  52                              int instance)
  53 {
  54         int i;
  55         int found_instance = -1;
  56
  57         for (i = 0; i < rdev->pm.num_power_states; i++) {
  58                 if (rdev->pm.power_state[i].type == ps_type) {
  59                         found_instance++;
  60                         if (found_instance == instance)
  61                                 return i;
  62                 }
  63         }
  64         /* return default if no match */
  65         return rdev->pm.default_power_state_index;
  66 }
  67
  68 void radeon_pm_acpi_event_handler(struct radeon_device *rdev)
  69 {
  70         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
  71                 if (rdev->pm.profile == PM_PROFILE_AUTO) {
  72                         mutex_lock(&rdev->pm.mutex);
  73                         radeon_pm_update_profile(rdev);
  74                         radeon_pm_set_clocks(rdev);
  75                         mutex_unlock(&rdev->pm.mutex);
  76                 }
  77         }
  78 }
  79
  80 static void radeon_pm_update_profile(struct radeon_device *rdev)
  81 {
  82         switch (rdev->pm.profile) {
  83         case PM_PROFILE_DEFAULT:
  84                 rdev->pm.profile_index = PM_PROFILE_DEFAULT_IDX;
  85                 break;
  86         case PM_PROFILE_AUTO:
  87                 if (power_supply_is_system_supplied() > 0) {
  88                         if (rdev->pm.active_crtc_count > 1)
  89                                 rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
  90                         else
  91                                 rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
  92                 } else {
  93                         if (rdev->pm.active_crtc_count > 1)
  94                                 rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
  95                         else
  96                                 rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
  97                 }
  98                 break;
  99         case PM_PROFILE_LOW:
 100                 if (rdev->pm.active_crtc_count > 1)
 101                         rdev->pm.profile_index = PM_PROFILE_LOW_MH_IDX;
 102                 else
 103                         rdev->pm.profile_index = PM_PROFILE_LOW_SH_IDX;
 104                 break;
 105         case PM_PROFILE_MID:
 106                 if (rdev->pm.active_crtc_count > 1)
 107                         rdev->pm.profile_index = PM_PROFILE_MID_MH_IDX;
 108                 else
 109                         rdev->pm.profile_index = PM_PROFILE_MID_SH_IDX;
 110                 break;
 111         case PM_PROFILE_HIGH:
 112                 if (rdev->pm.active_crtc_count > 1)
 113                         rdev->pm.profile_index = PM_PROFILE_HIGH_MH_IDX;
 114                 else
 115                         rdev->pm.profile_index = PM_PROFILE_HIGH_SH_IDX;
 116                 break;
 117         }
 118
 119         if (rdev->pm.active_crtc_count == 0) {
 120                 rdev->pm.requested_power_state_index =
 121                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_ps_idx;
 122                 rdev->pm.requested_clock_mode_index =
 123                         rdev->pm.profiles[rdev->pm.profile_index].dpms_off_cm_idx;
 124         } else {
 125                 rdev->pm.requested_power_state_index =
 126                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_ps_idx;
 127                 rdev->pm.requested_clock_mode_index =
 128                         rdev->pm.profiles[rdev->pm.profile_index].dpms_on_cm_idx;
 129         }
 130 }
 131
 132 static void radeon_unmap_vram_bos(struct radeon_device *rdev)
 133 {
 134         struct radeon_bo *bo, *n;
 135
 136         if (list_empty(&rdev->gem.objects))
 137                 return;
 138
 139         list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
 140                 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
 141                         ttm_bo_unmap_virtual(&bo->tbo);
 142         }
 143 }
 144
 145 static void radeon_sync_with_vblank(struct radeon_device *rdev)
 146 {
 147         if (rdev->pm.active_crtcs) {
 148                 rdev->pm.vblank_sync = false;
 149                 wait_event_timeout(
 150                         rdev->irq.vblank_queue, rdev->pm.vblank_sync,
 151                         msecs_to_jiffies(RADEON_WAIT_VBLANK_TIMEOUT));
 152         }
 153 }
 154
 155 static void radeon_set_power_state(struct radeon_device *rdev)
 156 {
 157         u32 sclk, mclk;
 158         bool misc_after = false;
 159
 160         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 161             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 162                 return;
 163
 164         if (radeon_gui_idle(rdev)) {
 165                 sclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 166                         clock_info[rdev->pm.requested_clock_mode_index].sclk;
 167                 if (sclk > rdev->pm.default_sclk)
 168                         sclk = rdev->pm.default_sclk;
 169
 170                 /* starting with BTC, there is one state that is used for both
 171                  * MH and SH.  Difference is that we always use the high clock index for
 172                  * mclk and vddci.
 173                  */
 174                 if ((rdev->pm.pm_method == PM_METHOD_PROFILE) &&
 175                     (rdev->family >= CHIP_BARTS) &&
 176                     rdev->pm.active_crtc_count &&
 177                     ((rdev->pm.profile_index == PM_PROFILE_MID_MH_IDX) ||
 178                      (rdev->pm.profile_index == PM_PROFILE_LOW_MH_IDX)))
 179                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 180                                 clock_info[rdev->pm.profiles[PM_PROFILE_HIGH_MH_IDX].dpms_on_cm_idx].mclk;
 181                 else
 182                         mclk = rdev->pm.power_state[rdev->pm.requested_power_state_index].
 183                                 clock_info[rdev->pm.requested_clock_mode_index].mclk;
 184
 185                 if (mclk > rdev->pm.default_mclk)
 186                         mclk = rdev->pm.default_mclk;
 187
 188                 /* upvolt before raising clocks, downvolt after lowering clocks */
 189                 if (sclk < rdev->pm.current_sclk)
 190                         misc_after = true;
 191
 192                 radeon_sync_with_vblank(rdev);
 193
 194                 if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 195                         if (!radeon_pm_in_vbl(rdev))
 196                                 return;
 197                 }
 198
 199                 radeon_pm_prepare(rdev);
 200
 201                 if (!misc_after)
 202                         /* voltage, pcie lanes, etc.*/
 203                         radeon_pm_misc(rdev);
 204
 205                 /* set engine clock */
 206                 if (sclk != rdev->pm.current_sclk) {
 207                         radeon_pm_debug_check_in_vbl(rdev, false);
 208                         radeon_set_engine_clock(rdev, sclk);
 209                         radeon_pm_debug_check_in_vbl(rdev, true);
 210                         rdev->pm.current_sclk = sclk;
 211                         DRM_DEBUG_DRIVER("Setting: e: %d\n", sclk);
 212                 }
 213
 214                 /* set memory clock */
 215                 if (rdev->asic->pm.set_memory_clock && (mclk != rdev->pm.current_mclk)) {
 216                         radeon_pm_debug_check_in_vbl(rdev, false);
 217                         radeon_set_memory_clock(rdev, mclk);
 218                         radeon_pm_debug_check_in_vbl(rdev, true);
 219                         rdev->pm.current_mclk = mclk;
 220                         DRM_DEBUG_DRIVER("Setting: m: %d\n", mclk);
 221                 }
 222
 223                 if (misc_after)
 224                         /* voltage, pcie lanes, etc.*/
 225                         radeon_pm_misc(rdev);
 226
 227                 radeon_pm_finish(rdev);
 228
 229                 rdev->pm.current_power_state_index = rdev->pm.requested_power_state_index;
 230                 rdev->pm.current_clock_mode_index = rdev->pm.requested_clock_mode_index;
 231         } else
 232                 DRM_DEBUG_DRIVER("pm: GUI not idle!!!\n");
 233 }
 234
 235 static void radeon_pm_set_clocks(struct radeon_device *rdev)
 236 {
 237         int i, r;
 238
 239         /* no need to take locks, etc. if nothing's going to change */
 240         if ((rdev->pm.requested_clock_mode_index == rdev->pm.current_clock_mode_index) &&
 241             (rdev->pm.requested_power_state_index == rdev->pm.current_power_state_index))
 242                 return;
 243
 244         mutex_lock(&rdev->ddev->struct_mutex);
 245         down_write(&rdev->pm.mclk_lock);
 246         mutex_lock(&rdev->ring_lock);
 247
 248         /* wait for the rings to drain */
 249         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 250                 struct radeon_ring *ring = &rdev->ring[i];
 251                 if (!ring->ready) {
 252                         continue;
 253                 }
 254                 r = radeon_fence_wait_empty_locked(rdev, i);
 255                 if (r) {
 256                         /* needs a GPU reset dont reset here */
 257                         mutex_unlock(&rdev->ring_lock);
 258                         up_write(&rdev->pm.mclk_lock);
 259                         mutex_unlock(&rdev->ddev->struct_mutex);
 260                         return;
 261                 }
 262         }
 263
 264         radeon_unmap_vram_bos(rdev);
 265
 266         if (rdev->irq.installed) {
 267                 for (i = 0; i < rdev->num_crtc; i++) {
 268                         if (rdev->pm.active_crtcs & (1 << i)) {
 269                                 rdev->pm.req_vblank |= (1 << i);
 270                                 drm_vblank_get(rdev->ddev, i);
 271                         }
 272                 }
 273         }
 274
 275         radeon_set_power_state(rdev);
 276
 277         if (rdev->irq.installed) {
 278                 for (i = 0; i < rdev->num_crtc; i++) {
 279                         if (rdev->pm.req_vblank & (1 << i)) {
 280                                 rdev->pm.req_vblank &= ~(1 << i);
 281                                 drm_vblank_put(rdev->ddev, i);
 282                         }
 283                 }
 284         }
 285
 286         /* update display watermarks based on new power state */
 287         radeon_update_bandwidth_info(rdev);
 288         if (rdev->pm.active_crtc_count)
 289                 radeon_bandwidth_update(rdev);
 290
 291         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 292
 293         mutex_unlock(&rdev->ring_lock);
 294         up_write(&rdev->pm.mclk_lock);
 295         mutex_unlock(&rdev->ddev->struct_mutex);
 296 }
 297
 298 static void radeon_pm_print_states(struct radeon_device *rdev)
 299 {
 300         int i, j;
 301         struct radeon_power_state *power_state;
 302         struct radeon_pm_clock_info *clock_info;
 303
 304         DRM_DEBUG_DRIVER("%d Power State(s)\n", rdev->pm.num_power_states);
 305         for (i = 0; i < rdev->pm.num_power_states; i++) {
 306                 power_state = &rdev->pm.power_state[i];
 307                 DRM_DEBUG_DRIVER("State %d: %s\n", i,
 308                         radeon_pm_state_type_name[power_state->type]);
 309                 if (i == rdev->pm.default_power_state_index)
 310                         DRM_DEBUG_DRIVER("\tDefault");
 311                 if ((rdev->flags & RADEON_IS_PCIE) && !(rdev->flags & RADEON_IS_IGP))
 312                         DRM_DEBUG_DRIVER("\t%d PCIE Lanes\n", power_state->pcie_lanes);
 313                 if (power_state->flags & RADEON_PM_STATE_SINGLE_DISPLAY_ONLY)
 314                         DRM_DEBUG_DRIVER("\tSingle display only\n");
 315                 DRM_DEBUG_DRIVER("\t%d Clock Mode(s)\n", power_state->num_clock_modes);
 316                 for (j = 0; j < power_state->num_clock_modes; j++) {
 317                         clock_info = &(power_state->clock_info[j]);
 318                         if (rdev->flags & RADEON_IS_IGP)
 319                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\n",
 320                                                  j,
 321                                                  clock_info->sclk * 10);
 322                         else
 323                                 DRM_DEBUG_DRIVER("\t\t%d e: %d\tm: %d\tv: %d\n",
 324                                                  j,
 325                                                  clock_info->sclk * 10,
 326                                                  clock_info->mclk * 10,
 327                                                  clock_info->voltage.voltage);
 328                 }
 329         }
 330 }
 331
 332 static ssize_t radeon_get_pm_profile(struct device *dev,
 333                                      struct device_attribute *attr,
 334                                      char *buf)
 335 {
 336         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 337         struct radeon_device *rdev = ddev->dev_private;
 338         int cp = rdev->pm.profile;
 339
 340         return snprintf(buf, PAGE_SIZE, "%s\n",
 341                         (cp == PM_PROFILE_AUTO) ? "auto" :
 342                         (cp == PM_PROFILE_LOW) ? "low" :
 343                         (cp == PM_PROFILE_MID) ? "mid" :
 344                         (cp == PM_PROFILE_HIGH) ? "high" : "default");
 345 }
 346
 347 static ssize_t radeon_set_pm_profile(struct device *dev,
 348                                      struct device_attribute *attr,
 349                                      const char *buf,
 350                                      size_t count)
 351 {
 352         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 353         struct radeon_device *rdev = ddev->dev_private;
 354
 355         mutex_lock(&rdev->pm.mutex);
 356         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
 357                 if (strncmp("default", buf, strlen("default")) == 0)
 358                         rdev->pm.profile = PM_PROFILE_DEFAULT;
 359                 else if (strncmp("auto", buf, strlen("auto")) == 0)
 360                         rdev->pm.profile = PM_PROFILE_AUTO;
 361                 else if (strncmp("low", buf, strlen("low")) == 0)
 362                         rdev->pm.profile = PM_PROFILE_LOW;
 363                 else if (strncmp("mid", buf, strlen("mid")) == 0)
 364                         rdev->pm.profile = PM_PROFILE_MID;
 365                 else if (strncmp("high", buf, strlen("high")) == 0)
 366                         rdev->pm.profile = PM_PROFILE_HIGH;
 367                 else {
 368                         count = -EINVAL;
 369                         goto fail;
 370                 }
 371                 radeon_pm_update_profile(rdev);
 372                 radeon_pm_set_clocks(rdev);
 373         } else
 374                 count = -EINVAL;
 375
 376 fail:
 377         mutex_unlock(&rdev->pm.mutex);
 378
 379         return count;
 380 }
 381
 382 static ssize_t radeon_get_pm_method(struct device *dev,
 383                                     struct device_attribute *attr,
 384                                     char *buf)
 385 {
 386         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 387         struct radeon_device *rdev = ddev->dev_private;
 388         int pm = rdev->pm.pm_method;
 389
 390         return snprintf(buf, PAGE_SIZE, "%s\n",
 391                         (pm == PM_METHOD_DYNPM) ? "dynpm" :
 392                         (pm == PM_METHOD_PROFILE) ? "profile" : "dpm");
 393 }
 394
 395 static ssize_t radeon_set_pm_method(struct device *dev,
 396                                     struct device_attribute *attr,
 397                                     const char *buf,
 398                                     size_t count)
 399 {
 400         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 401         struct radeon_device *rdev = ddev->dev_private;
 402
 403         /* we don't support the legacy modes with dpm */
 404         if (rdev->pm.pm_method == PM_METHOD_DPM) {
 405                 count = -EINVAL;
 406                 goto fail;
 407         }
 408
 409         if (strncmp("dynpm", buf, strlen("dynpm")) == 0) {
 410                 mutex_lock(&rdev->pm.mutex);
 411                 rdev->pm.pm_method = PM_METHOD_DYNPM;
 412                 rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
 413                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
 414                 mutex_unlock(&rdev->pm.mutex);
 415         } else if (strncmp("profile", buf, strlen("profile")) == 0) {
 416                 mutex_lock(&rdev->pm.mutex);
 417                 /* disable dynpm */
 418                 rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 419                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 420                 rdev->pm.pm_method = PM_METHOD_PROFILE;
 421                 mutex_unlock(&rdev->pm.mutex);
 422                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 423         } else {
 424                 count = -EINVAL;
 425                 goto fail;
 426         }
 427         radeon_pm_compute_clocks(rdev);
 428 fail:
 429         return count;
 430 }
 431
 432 static ssize_t radeon_get_dpm_state(struct device *dev,
 433                                     struct device_attribute *attr,
 434                                     char *buf)
 435 {
 436         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 437         struct radeon_device *rdev = ddev->dev_private;
 438         enum radeon_pm_state_type pm = rdev->pm.dpm.user_state;
 439
 440         return snprintf(buf, PAGE_SIZE, "%s\n",
 441                         (pm == POWER_STATE_TYPE_BATTERY) ? "battery" :
 442                         (pm == POWER_STATE_TYPE_BALANCED) ? "balanced" : "performance");
 443 }
 444
 445 static ssize_t radeon_set_dpm_state(struct device *dev,
 446                                     struct device_attribute *attr,
 447                                     const char *buf,
 448                                     size_t count)
 449 {
 450         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 451         struct radeon_device *rdev = ddev->dev_private;
 452
 453         mutex_lock(&rdev->pm.mutex);
 454         if (strncmp("battery", buf, strlen("battery")) == 0)
 455                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BATTERY;
 456         else if (strncmp("balanced", buf, strlen("balanced")) == 0)
 457                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
 458         else if (strncmp("performance", buf, strlen("performance")) == 0)
 459                 rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
 460         else {
 461                 mutex_unlock(&rdev->pm.mutex);
 462                 count = -EINVAL;
 463                 goto fail;
 464         }
 465         mutex_unlock(&rdev->pm.mutex);
 466         radeon_pm_compute_clocks(rdev);
 467 fail:
 468         return count;
 469 }
 470
 471 static DEVICE_ATTR(power_profile, S_IRUGO | S_IWUSR, radeon_get_pm_profile, radeon_set_pm_profile);
 472 static DEVICE_ATTR(power_method, S_IRUGO | S_IWUSR, radeon_get_pm_method, radeon_set_pm_method);
 473 static DEVICE_ATTR(power_dpm_state, S_IRUGO | S_IWUSR, radeon_get_dpm_state, radeon_set_dpm_state);
 474
 475 static ssize_t radeon_hwmon_show_temp(struct device *dev,
 476                                       struct device_attribute *attr,
 477                                       char *buf)
 478 {
 479         struct drm_device *ddev = pci_get_drvdata(to_pci_dev(dev));
 480         struct radeon_device *rdev = ddev->dev_private;
 481         int temp;
 482
 483         if (rdev->asic->pm.get_temperature)
 484                 temp = radeon_get_temperature(rdev);
 485         else
 486                 temp = 0;
 487
 488         return snprintf(buf, PAGE_SIZE, "%d\n", temp);
 489 }
 490
 491 static ssize_t radeon_hwmon_show_name(struct device *dev,
 492                                       struct device_attribute *attr,
 493                                       char *buf)
 494 {
 495         return sprintf(buf, "radeon\n");
 496 }
 497
 498 static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, radeon_hwmon_show_temp, NULL, 0);
 499 static SENSOR_DEVICE_ATTR(name, S_IRUGO, radeon_hwmon_show_name, NULL, 0);
 500
 501 static struct attribute *hwmon_attributes[] = {
 502         &sensor_dev_attr_temp1_input.dev_attr.attr,
 503         &sensor_dev_attr_name.dev_attr.attr,
 504         NULL
 505 };
 506
 507 static const struct attribute_group hwmon_attrgroup = {
 508         .attrs = hwmon_attributes,
 509 };
 510
 511 static int radeon_hwmon_init(struct radeon_device *rdev)
 512 {
 513         int err = 0;
 514
 515         rdev->pm.int_hwmon_dev = NULL;
 516
 517         switch (rdev->pm.int_thermal_type) {
 518         case THERMAL_TYPE_RV6XX:
 519         case THERMAL_TYPE_RV770:
 520         case THERMAL_TYPE_EVERGREEN:
 521         case THERMAL_TYPE_NI:
 522         case THERMAL_TYPE_SUMO:
 523         case THERMAL_TYPE_SI:
 524                 if (rdev->asic->pm.get_temperature == NULL)
 525                         return err;
 526                 rdev->pm.int_hwmon_dev = hwmon_device_register(rdev->dev);
 527                 if (IS_ERR(rdev->pm.int_hwmon_dev)) {
 528                         err = PTR_ERR(rdev->pm.int_hwmon_dev);
 529                         dev_err(rdev->dev,
 530                                 "Unable to register hwmon device: %d\n", err);
 531                         break;
 532                 }
 533                 dev_set_drvdata(rdev->pm.int_hwmon_dev, rdev->ddev);
 534                 err = sysfs_create_group(&rdev->pm.int_hwmon_dev->kobj,
 535                                          &hwmon_attrgroup);
 536                 if (err) {
 537                         dev_err(rdev->dev,
 538                                 "Unable to create hwmon sysfs file: %d\n", err);
 539                         hwmon_device_unregister(rdev->dev);
 540                 }
 541                 break;
 542         default:
 543                 break;
 544         }
 545
 546         return err;
 547 }
 548
 549 static void radeon_hwmon_fini(struct radeon_device *rdev)
 550 {
 551         if (rdev->pm.int_hwmon_dev) {
 552                 sysfs_remove_group(&rdev->pm.int_hwmon_dev->kobj, &hwmon_attrgroup);
 553                 hwmon_device_unregister(rdev->pm.int_hwmon_dev);
 554         }
 555 }
 556
 557 static void radeon_dpm_thermal_work_handler(struct work_struct *work)
 558 {
 559         struct radeon_device *rdev =
 560                 container_of(work, struct radeon_device,
 561                              pm.dpm.thermal.work);
 562         /* switch to the thermal state */
 563         enum radeon_pm_state_type dpm_state = POWER_STATE_TYPE_INTERNAL_THERMAL;
 564
 565         if (!rdev->pm.dpm_enabled)
 566                 return;
 567
 568         if (rdev->asic->pm.get_temperature) {
 569                 int temp = radeon_get_temperature(rdev);
 570
 571                 if (temp < rdev->pm.dpm.thermal.min_temp)
 572                         /* switch back the user state */
 573                         dpm_state = rdev->pm.dpm.user_state;
 574         } else {
 575                 if (rdev->pm.dpm.thermal.high_to_low)
 576                         /* switch back the user state */
 577                         dpm_state = rdev->pm.dpm.user_state;
 578         }
 579         radeon_dpm_enable_power_state(rdev, dpm_state);
 580 }
 581
 582 static struct radeon_ps *radeon_dpm_pick_power_state(struct radeon_device *rdev,
 583                                                      enum radeon_pm_state_type dpm_state)
 584 {
 585         int i;
 586         struct radeon_ps *ps;
 587         u32 ui_class;
 588
 589 restart_search:
 590         /* balanced states don't exist at the moment */
 591         if (dpm_state == POWER_STATE_TYPE_BALANCED)
 592                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 593
 594         /* Pick the best power state based on current conditions */
 595         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 596                 ps = &rdev->pm.dpm.ps[i];
 597                 ui_class = ps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK;
 598                 switch (dpm_state) {
 599                 /* user states */
 600                 case POWER_STATE_TYPE_BATTERY:
 601                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) {
 602                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 603                                         if (rdev->pm.dpm.new_active_crtc_count < 2)
 604                                                 return ps;
 605                                 } else
 606                                         return ps;
 607                         }
 608                         break;
 609                 case POWER_STATE_TYPE_BALANCED:
 610                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_BALANCED) {
 611                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 612                                         if (rdev->pm.dpm.new_active_crtc_count < 2)
 613                                                 return ps;
 614                                 } else
 615                                         return ps;
 616                         }
 617                         break;
 618                 case POWER_STATE_TYPE_PERFORMANCE:
 619                         if (ui_class == ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
 620                                 if (ps->caps & ATOM_PPLIB_SINGLE_DISPLAY_ONLY) {
 621                                         if (rdev->pm.dpm.new_active_crtc_count < 2)
 622                                                 return ps;
 623                                 } else
 624                                         return ps;
 625                         }
 626                         break;
 627                 /* internal states */
 628                 case POWER_STATE_TYPE_INTERNAL_UVD:
 629                         return rdev->pm.dpm.uvd_ps;
 630                 case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 631                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE)
 632                                 return ps;
 633                         break;
 634                 case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 635                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE)
 636                                 return ps;
 637                         break;
 638                 case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 639                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_HD2STATE)
 640                                 return ps;
 641                         break;
 642                 case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 643                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC)
 644                                 return ps;
 645                         break;
 646                 case POWER_STATE_TYPE_INTERNAL_BOOT:
 647                         return rdev->pm.dpm.boot_ps;
 648                 case POWER_STATE_TYPE_INTERNAL_THERMAL:
 649                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
 650                                 return ps;
 651                         break;
 652                 case POWER_STATE_TYPE_INTERNAL_ACPI:
 653                         if (ps->class & ATOM_PPLIB_CLASSIFICATION_ACPI)
 654                                 return ps;
 655                         break;
 656                 case POWER_STATE_TYPE_INTERNAL_ULV:
 657                         if (ps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV)
 658                                 return ps;
 659                         break;
 660                 default:
 661                         break;
 662                 }
 663         }
 664         /* use a fallback state if we didn't match */
 665         switch (dpm_state) {
 666         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 667         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 668         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 669         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 670                 return rdev->pm.dpm.uvd_ps;
 671         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 672                 dpm_state = POWER_STATE_TYPE_INTERNAL_ACPI;
 673                 goto restart_search;
 674         case POWER_STATE_TYPE_INTERNAL_ACPI:
 675                 dpm_state = POWER_STATE_TYPE_BATTERY;
 676                 goto restart_search;
 677         case POWER_STATE_TYPE_BATTERY:
 678                 dpm_state = POWER_STATE_TYPE_PERFORMANCE;
 679                 goto restart_search;
 680         default:
 681                 break;
 682         }
 683
 684         return NULL;
 685 }
 686
 687 static void radeon_dpm_change_power_state_locked(struct radeon_device *rdev)
 688 {
 689         int i;
 690         struct radeon_ps *ps;
 691         enum radeon_pm_state_type dpm_state;
 692         int ret;
 693
 694         /* if dpm init failed */
 695         if (!rdev->pm.dpm_enabled)
 696                 return;
 697
 698         if (rdev->pm.dpm.user_state != rdev->pm.dpm.state) {
 699                 /* add other state override checks here */
 700                 if ((!rdev->pm.dpm.thermal_active) &&
 701                     (!rdev->pm.dpm.uvd_active))
 702                         rdev->pm.dpm.state = rdev->pm.dpm.user_state;
 703         }
 704         dpm_state = rdev->pm.dpm.state;
 705
 706         ps = radeon_dpm_pick_power_state(rdev, dpm_state);
 707         if (ps)
 708                 rdev->pm.dpm.requested_ps = ps;
 709         else
 710                 return;
 711
 712         /* no need to reprogram if nothing changed unless we are on BTC+ */
 713         if (rdev->pm.dpm.current_ps == rdev->pm.dpm.requested_ps) {
 714                 if ((rdev->family < CHIP_BARTS) || (rdev->flags & RADEON_IS_IGP)) {
 715                         /* for pre-BTC and APUs if the num crtcs changed but state is the same,
 716                          * all we need to do is update the display configuration.
 717                          */
 718                         if (rdev->pm.dpm.new_active_crtcs != rdev->pm.dpm.current_active_crtcs) {
 719                                 /* update display watermarks based on new power state */
 720                                 radeon_bandwidth_update(rdev);
 721                                 /* update displays */
 722                                 radeon_dpm_display_configuration_changed(rdev);
 723                                 rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 724                                 rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 725                         }
 726                         return;
 727                 } else {
 728                         /* for BTC+ if the num crtcs hasn't changed and state is the same,
 729                          * nothing to do, if the num crtcs is > 1 and state is the same,
 730                          * update display configuration.
 731                          */
 732                         if (rdev->pm.dpm.new_active_crtcs ==
 733                             rdev->pm.dpm.current_active_crtcs) {
 734                                 return;
 735                         } else {
 736                                 if ((rdev->pm.dpm.current_active_crtc_count > 1) &&
 737                                     (rdev->pm.dpm.new_active_crtc_count > 1)) {
 738                                         /* update display watermarks based on new power state */
 739                                         radeon_bandwidth_update(rdev);
 740                                         /* update displays */
 741                                         radeon_dpm_display_configuration_changed(rdev);
 742                                         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 743                                         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 744                                         return;
 745                                 }
 746                         }
 747                 }
 748         }
 749
 750         printk("switching from power state:\n");
 751         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.current_ps);
 752         printk("switching to power state:\n");
 753         radeon_dpm_print_power_state(rdev, rdev->pm.dpm.requested_ps);
 754
 755         mutex_lock(&rdev->ddev->struct_mutex);
 756         down_write(&rdev->pm.mclk_lock);
 757         mutex_lock(&rdev->ring_lock);
 758
 759         ret = radeon_dpm_pre_set_power_state(rdev);
 760         if (ret)
 761                 goto done;
 762
 763         /* update display watermarks based on new power state */
 764         radeon_bandwidth_update(rdev);
 765         /* update displays */
 766         radeon_dpm_display_configuration_changed(rdev);
 767
 768         rdev->pm.dpm.current_active_crtcs = rdev->pm.dpm.new_active_crtcs;
 769         rdev->pm.dpm.current_active_crtc_count = rdev->pm.dpm.new_active_crtc_count;
 770
 771         /* wait for the rings to drain */
 772         for (i = 0; i < RADEON_NUM_RINGS; i++) {
 773                 struct radeon_ring *ring = &rdev->ring[i];
 774                 if (ring->ready)
 775                         radeon_fence_wait_empty_locked(rdev, i);
 776         }
 777
 778         /* program the new power state */
 779         radeon_dpm_set_power_state(rdev);
 780
 781         /* update current power state */
 782         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps;
 783
 784         radeon_dpm_post_set_power_state(rdev);
 785
 786 done:
 787         mutex_unlock(&rdev->ring_lock);
 788         up_write(&rdev->pm.mclk_lock);
 789         mutex_unlock(&rdev->ddev->struct_mutex);
 790 }
 791
 792 void radeon_dpm_enable_power_state(struct radeon_device *rdev,
 793                                    enum radeon_pm_state_type dpm_state)
 794 {
 795         if (!rdev->pm.dpm_enabled)
 796                 return;
 797
 798         mutex_lock(&rdev->pm.mutex);
 799         switch (dpm_state) {
 800         case POWER_STATE_TYPE_INTERNAL_THERMAL:
 801                 rdev->pm.dpm.thermal_active = true;
 802                 break;
 803         case POWER_STATE_TYPE_INTERNAL_UVD:
 804         case POWER_STATE_TYPE_INTERNAL_UVD_SD:
 805         case POWER_STATE_TYPE_INTERNAL_UVD_HD:
 806         case POWER_STATE_TYPE_INTERNAL_UVD_HD2:
 807         case POWER_STATE_TYPE_INTERNAL_UVD_MVC:
 808                 rdev->pm.dpm.uvd_active = true;
 809                 break;
 810         default:
 811                 rdev->pm.dpm.thermal_active = false;
 812                 rdev->pm.dpm.uvd_active = false;
 813                 break;
 814         }
 815         rdev->pm.dpm.state = dpm_state;
 816         mutex_unlock(&rdev->pm.mutex);
 817         radeon_pm_compute_clocks(rdev);
 818 }
 819
 820 static void radeon_pm_suspend_old(struct radeon_device *rdev)
 821 {
 822         mutex_lock(&rdev->pm.mutex);
 823         if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
 824                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE)
 825                         rdev->pm.dynpm_state = DYNPM_STATE_SUSPENDED;
 826         }
 827         mutex_unlock(&rdev->pm.mutex);
 828
 829         cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
 830 }
 831
 832 static void radeon_pm_suspend_dpm(struct radeon_device *rdev)
 833 {
 834         mutex_lock(&rdev->pm.mutex);
 835         /* disable dpm */
 836         radeon_dpm_disable(rdev);
 837         /* reset the power state */
 838         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 839         rdev->pm.dpm_enabled = false;
 840         mutex_unlock(&rdev->pm.mutex);
 841 }
 842
 843 void radeon_pm_suspend(struct radeon_device *rdev)
 844 {
 845         if (rdev->pm.pm_method == PM_METHOD_DPM)
 846                 radeon_pm_suspend_dpm(rdev);
 847         else
 848                 radeon_pm_suspend_old(rdev);
 849 }
 850
 851 static void radeon_pm_resume_old(struct radeon_device *rdev)
 852 {
 853         /* set up the default clocks if the MC ucode is loaded */
 854         if ((rdev->family >= CHIP_BARTS) &&
 855             (rdev->family <= CHIP_CAYMAN) &&
 856             rdev->mc_fw) {
 857                 if (rdev->pm.default_vddc)
 858                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 859                                                 SET_VOLTAGE_TYPE_ASIC_VDDC);
 860                 if (rdev->pm.default_vddci)
 861                         radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 862                                                 SET_VOLTAGE_TYPE_ASIC_VDDCI);
 863                 if (rdev->pm.default_sclk)
 864                         radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 865                 if (rdev->pm.default_mclk)
 866                         radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 867         }
 868         /* asic init will reset the default power state */
 869         mutex_lock(&rdev->pm.mutex);
 870         rdev->pm.current_power_state_index = rdev->pm.default_power_state_index;
 871         rdev->pm.current_clock_mode_index = 0;
 872         rdev->pm.current_sclk = rdev->pm.default_sclk;
 873         rdev->pm.current_mclk = rdev->pm.default_mclk;
 874         rdev->pm.current_vddc = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.voltage;
 875         rdev->pm.current_vddci = rdev->pm.power_state[rdev->pm.default_power_state_index].clock_info[0].voltage.vddci;
 876         if (rdev->pm.pm_method == PM_METHOD_DYNPM
 877             && rdev->pm.dynpm_state == DYNPM_STATE_SUSPENDED) {
 878                 rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
 879                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
 880                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
 881         }
 882         mutex_unlock(&rdev->pm.mutex);
 883         radeon_pm_compute_clocks(rdev);
 884 }
 885
 886 static void radeon_pm_resume_dpm(struct radeon_device *rdev)
 887 {
 888         int ret;
 889
 890         /* asic init will reset to the boot state */
 891         mutex_lock(&rdev->pm.mutex);
 892         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
 893         radeon_dpm_setup_asic(rdev);
 894         ret = radeon_dpm_enable(rdev);
 895         mutex_unlock(&rdev->pm.mutex);
 896         if (ret) {
 897                 DRM_ERROR("radeon: dpm resume failed\n");
 898                 if ((rdev->family >= CHIP_BARTS) &&
 899                     (rdev->family <= CHIP_CAYMAN) &&
 900                     rdev->mc_fw) {
 901                         if (rdev->pm.default_vddc)
 902                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 903                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 904                         if (rdev->pm.default_vddci)
 905                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 906                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 907                         if (rdev->pm.default_sclk)
 908                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 909                         if (rdev->pm.default_mclk)
 910                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 911                 }
 912         } else {
 913                 rdev->pm.dpm_enabled = true;
 914                 radeon_pm_compute_clocks(rdev);
 915         }
 916 }
 917
 918 void radeon_pm_resume(struct radeon_device *rdev)
 919 {
 920         if (rdev->pm.pm_method == PM_METHOD_DPM)
 921                 radeon_pm_resume_dpm(rdev);
 922         else
 923                 radeon_pm_resume_old(rdev);
 924 }
 925
 926 static int radeon_pm_init_old(struct radeon_device *rdev)
 927 {
 928         int ret;
 929
 930         rdev->pm.profile = PM_PROFILE_DEFAULT;
 931         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
 932         rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
 933         rdev->pm.dynpm_can_upclock = true;
 934         rdev->pm.dynpm_can_downclock = true;
 935         rdev->pm.default_sclk = rdev->clock.default_sclk;
 936         rdev->pm.default_mclk = rdev->clock.default_mclk;
 937         rdev->pm.current_sclk = rdev->clock.default_sclk;
 938         rdev->pm.current_mclk = rdev->clock.default_mclk;
 939         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
 940
 941         if (rdev->bios) {
 942                 if (rdev->is_atom_bios)
 943                         radeon_atombios_get_power_modes(rdev);
 944                 else
 945                         radeon_combios_get_power_modes(rdev);
 946                 radeon_pm_print_states(rdev);
 947                 radeon_pm_init_profile(rdev);
 948                 /* set up the default clocks if the MC ucode is loaded */
 949                 if ((rdev->family >= CHIP_BARTS) &&
 950                     (rdev->family <= CHIP_CAYMAN) &&
 951                     rdev->mc_fw) {
 952                         if (rdev->pm.default_vddc)
 953                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
 954                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
 955                         if (rdev->pm.default_vddci)
 956                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
 957                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
 958                         if (rdev->pm.default_sclk)
 959                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
 960                         if (rdev->pm.default_mclk)
 961                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
 962                 }
 963         }
 964
 965         /* set up the internal thermal sensor if applicable */
 966         ret = radeon_hwmon_init(rdev);
 967         if (ret)
 968                 return ret;
 969
 970         INIT_DELAYED_WORK(&rdev->pm.dynpm_idle_work, radeon_dynpm_idle_work_handler);
 971
 972         if (rdev->pm.num_power_states > 1) {
 973                 /* where's the best place to put these? */
 974                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
 975                 if (ret)
 976                         DRM_ERROR("failed to create device file for power profile\n");
 977                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
 978                 if (ret)
 979                         DRM_ERROR("failed to create device file for power method\n");
 980
 981                 if (radeon_debugfs_pm_init(rdev)) {
 982                         DRM_ERROR("Failed to register debugfs file for PM!\n");
 983                 }
 984
 985                 DRM_INFO("radeon: power management initialized\n");
 986         }
 987
 988         return 0;
 989 }
 990
 991 static void radeon_dpm_print_power_states(struct radeon_device *rdev)
 992 {
 993         int i;
 994
 995         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
 996                 printk("== power state %d ==\n", i);
 997                 radeon_dpm_print_power_state(rdev, &rdev->pm.dpm.ps[i]);
 998         }
 999 }
1000
1001 static int radeon_pm_init_dpm(struct radeon_device *rdev)
1002 {
1003         int ret;
1004
1005         /* default to performance state */
1006         rdev->pm.dpm.state = POWER_STATE_TYPE_PERFORMANCE;
1007         rdev->pm.dpm.user_state = POWER_STATE_TYPE_PERFORMANCE;
1008         rdev->pm.default_sclk = rdev->clock.default_sclk;
1009         rdev->pm.default_mclk = rdev->clock.default_mclk;
1010         rdev->pm.current_sclk = rdev->clock.default_sclk;
1011         rdev->pm.current_mclk = rdev->clock.default_mclk;
1012         rdev->pm.int_thermal_type = THERMAL_TYPE_NONE;
1013
1014         if (rdev->bios && rdev->is_atom_bios)
1015                 radeon_atombios_get_power_modes(rdev);
1016         else
1017                 return -EINVAL;
1018
1019         /* set up the internal thermal sensor if applicable */
1020         ret = radeon_hwmon_init(rdev);
1021         if (ret)
1022                 return ret;
1023
1024         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1025         mutex_lock(&rdev->pm.mutex);
1026         radeon_dpm_init(rdev);
1027         rdev->pm.dpm.current_ps = rdev->pm.dpm.requested_ps = rdev->pm.dpm.boot_ps;
1028         radeon_dpm_print_power_states(rdev);
1029         radeon_dpm_setup_asic(rdev);
1030         ret = radeon_dpm_enable(rdev);
1031         mutex_unlock(&rdev->pm.mutex);
1032         if (ret) {
1033                 rdev->pm.dpm_enabled = false;
1034                 if ((rdev->family >= CHIP_BARTS) &&
1035                     (rdev->family <= CHIP_CAYMAN) &&
1036                     rdev->mc_fw) {
1037                         if (rdev->pm.default_vddc)
1038                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddc,
1039                                                         SET_VOLTAGE_TYPE_ASIC_VDDC);
1040                         if (rdev->pm.default_vddci)
1041                                 radeon_atom_set_voltage(rdev, rdev->pm.default_vddci,
1042                                                         SET_VOLTAGE_TYPE_ASIC_VDDCI);
1043                         if (rdev->pm.default_sclk)
1044                                 radeon_set_engine_clock(rdev, rdev->pm.default_sclk);
1045                         if (rdev->pm.default_mclk)
1046                                 radeon_set_memory_clock(rdev, rdev->pm.default_mclk);
1047                 }
1048                 DRM_ERROR("radeon: dpm initialization failed\n");
1049                 return ret;
1050         }
1051         rdev->pm.dpm_enabled = true;
1052         radeon_pm_compute_clocks(rdev);
1053
1054         if (rdev->pm.num_power_states > 1) {
1055                 ret = device_create_file(rdev->dev, &dev_attr_power_dpm_state);
1056                 if (ret)
1057                         DRM_ERROR("failed to create device file for dpm state\n");
1058                 /* XXX: these are noops for dpm but are here for backwards compat */
1059                 ret = device_create_file(rdev->dev, &dev_attr_power_profile);
1060                 if (ret)
1061                         DRM_ERROR("failed to create device file for power profile\n");
1062                 ret = device_create_file(rdev->dev, &dev_attr_power_method);
1063                 if (ret)
1064                         DRM_ERROR("failed to create device file for power method\n");
1065
1066                 if (radeon_debugfs_pm_init(rdev)) {
1067                         DRM_ERROR("Failed to register debugfs file for dpm!\n");
1068                 }
1069
1070                 DRM_INFO("radeon: dpm initialized\n");
1071         }
1072
1073         return 0;
1074 }
1075
1076 int radeon_pm_init(struct radeon_device *rdev)
1077 {
1078         /* enable dpm on rv6xx+ */
1079         switch (rdev->family) {
1080         case CHIP_RV610:
1081         case CHIP_RV630:
1082         case CHIP_RV620:
1083         case CHIP_RV635:
1084         case CHIP_RV670:
1085         case CHIP_RS780:
1086         case CHIP_RS880:
1087         case CHIP_RV770:
1088         case CHIP_RV730:
1089         case CHIP_RV710:
1090         case CHIP_RV740:
1091         case CHIP_CEDAR:
1092         case CHIP_REDWOOD:
1093         case CHIP_JUNIPER:
1094         case CHIP_CYPRESS:
1095         case CHIP_HEMLOCK:
1096         case CHIP_PALM:
1097         case CHIP_SUMO:
1098         case CHIP_SUMO2:
1099         case CHIP_BARTS:
1100         case CHIP_TURKS:
1101         case CHIP_CAICOS:
1102         case CHIP_CAYMAN:
1103         case CHIP_ARUBA:
1104         case CHIP_TAHITI:
1105         case CHIP_PITCAIRN:
1106         case CHIP_VERDE:
1107         case CHIP_OLAND:
1108         case CHIP_HAINAN:
1109                 if (radeon_dpm == 1)
1110                         rdev->pm.pm_method = PM_METHOD_DPM;
1111                 else
1112                         rdev->pm.pm_method = PM_METHOD_PROFILE;
1113                 break;
1114         default:
1115                 /* default to profile method */
1116                 rdev->pm.pm_method = PM_METHOD_PROFILE;
1117                 break;
1118         }
1119
1120         if (rdev->pm.pm_method == PM_METHOD_DPM)
1121                 return radeon_pm_init_dpm(rdev);
1122         else
1123                 return radeon_pm_init_old(rdev);
1124 }
1125
1126 static void radeon_pm_fini_old(struct radeon_device *rdev)
1127 {
1128         if (rdev->pm.num_power_states > 1) {
1129                 mutex_lock(&rdev->pm.mutex);
1130                 if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1131                         rdev->pm.profile = PM_PROFILE_DEFAULT;
1132                         radeon_pm_update_profile(rdev);
1133                         radeon_pm_set_clocks(rdev);
1134                 } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1135                         /* reset default clocks */
1136                         rdev->pm.dynpm_state = DYNPM_STATE_DISABLED;
1137                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1138                         radeon_pm_set_clocks(rdev);
1139                 }
1140                 mutex_unlock(&rdev->pm.mutex);
1141
1142                 cancel_delayed_work_sync(&rdev->pm.dynpm_idle_work);
1143
1144                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1145                 device_remove_file(rdev->dev, &dev_attr_power_method);
1146         }
1147
1148         if (rdev->pm.power_state)
1149                 kfree(rdev->pm.power_state);
1150
1151         radeon_hwmon_fini(rdev);
1152 }
1153
1154 static void radeon_pm_fini_dpm(struct radeon_device *rdev)
1155 {
1156         if (rdev->pm.num_power_states > 1) {
1157                 mutex_lock(&rdev->pm.mutex);
1158                 radeon_dpm_disable(rdev);
1159                 mutex_unlock(&rdev->pm.mutex);
1160
1161                 device_remove_file(rdev->dev, &dev_attr_power_dpm_state);
1162                 /* XXX backwards compat */
1163                 device_remove_file(rdev->dev, &dev_attr_power_profile);
1164                 device_remove_file(rdev->dev, &dev_attr_power_method);
1165         }
1166         radeon_dpm_fini(rdev);
1167
1168         if (rdev->pm.power_state)
1169                 kfree(rdev->pm.power_state);
1170
1171         radeon_hwmon_fini(rdev);
1172 }
1173
1174 void radeon_pm_fini(struct radeon_device *rdev)
1175 {
1176         if (rdev->pm.pm_method == PM_METHOD_DPM)
1177                 radeon_pm_fini_dpm(rdev);
1178         else
1179                 radeon_pm_fini_old(rdev);
1180 }
1181
1182 static void radeon_pm_compute_clocks_old(struct radeon_device *rdev)
1183 {
1184         struct drm_device *ddev = rdev->ddev;
1185         struct drm_crtc *crtc;
1186         struct radeon_crtc *radeon_crtc;
1187
1188         if (rdev->pm.num_power_states < 2)
1189                 return;
1190
1191         INIT_WORK(&rdev->pm.dpm.thermal.work, radeon_dpm_thermal_work_handler);
1192         mutex_lock(&rdev->pm.mutex);
1193
1194         rdev->pm.active_crtcs = 0;
1195         rdev->pm.active_crtc_count = 0;
1196         list_for_each_entry(crtc,
1197                 &ddev->mode_config.crtc_list, head) {
1198                 radeon_crtc = to_radeon_crtc(crtc);
1199                 if (radeon_crtc->enabled) {
1200                         rdev->pm.active_crtcs |= (1 << radeon_crtc->crtc_id);
1201                         rdev->pm.active_crtc_count++;
1202                 }
1203         }
1204
1205         if (rdev->pm.pm_method == PM_METHOD_PROFILE) {
1206                 radeon_pm_update_profile(rdev);
1207                 radeon_pm_set_clocks(rdev);
1208         } else if (rdev->pm.pm_method == PM_METHOD_DYNPM) {
1209                 if (rdev->pm.dynpm_state != DYNPM_STATE_DISABLED) {
1210                         if (rdev->pm.active_crtc_count > 1) {
1211                                 if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1212                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1213
1214                                         rdev->pm.dynpm_state = DYNPM_STATE_PAUSED;
1215                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_DEFAULT;
1216                                         radeon_pm_get_dynpm_state(rdev);
1217                                         radeon_pm_set_clocks(rdev);
1218
1219                                         DRM_DEBUG_DRIVER("radeon: dynamic power management deactivated\n");
1220                                 }
1221                         } else if (rdev->pm.active_crtc_count == 1) {
1222                                 /* TODO: Increase clocks if needed for current mode */
1223
1224                                 if (rdev->pm.dynpm_state == DYNPM_STATE_MINIMUM) {
1225                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1226                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_UPCLOCK;
1227                                         radeon_pm_get_dynpm_state(rdev);
1228                                         radeon_pm_set_clocks(rdev);
1229
1230                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1231                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1232                                 } else if (rdev->pm.dynpm_state == DYNPM_STATE_PAUSED) {
1233                                         rdev->pm.dynpm_state = DYNPM_STATE_ACTIVE;
1234                                         schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1235                                                               msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1236                                         DRM_DEBUG_DRIVER("radeon: dynamic power management activated\n");
1237                                 }
1238                         } else { /* count == 0 */
1239                                 if (rdev->pm.dynpm_state != DYNPM_STATE_MINIMUM) {
1240                                         cancel_delayed_work(&rdev->pm.dynpm_idle_work);
1241
1242                                         rdev->pm.dynpm_state = DYNPM_STATE_MINIMUM;
1243                                         rdev->pm.dynpm_planned_action = DYNPM_ACTION_MINIMUM;
1244                                         radeon_pm_get_dynpm_state(rdev);
1245                                         radeon_pm_set_clocks(rdev);
1246                                 }
1247                         }
1248                 }
1249         }
1250
1251         mutex_unlock(&rdev->pm.mutex);
1252 }
1253
1254 static void radeon_pm_compute_clocks_dpm(struct radeon_device *rdev)
1255 {
1256         struct drm_device *ddev = rdev->ddev;
1257         struct drm_crtc *crtc;
1258         struct radeon_crtc *radeon_crtc;
1259
1260         mutex_lock(&rdev->pm.mutex);
1261
1262         /* update active crtc counts */
1263         rdev->pm.dpm.new_active_crtcs = 0;
1264         rdev->pm.dpm.new_active_crtc_count = 0;
1265         list_for_each_entry(crtc,
1266                 &ddev->mode_config.crtc_list, head) {
1267                 radeon_crtc = to_radeon_crtc(crtc);
1268                 if (crtc->enabled) {
1269                         rdev->pm.dpm.new_active_crtcs |= (1 << radeon_crtc->crtc_id);
1270                         rdev->pm.dpm.new_active_crtc_count++;
1271                 }
1272         }
1273
1274         /* update battery/ac status */
1275         if (power_supply_is_system_supplied() > 0)
1276                 rdev->pm.dpm.ac_power = true;
1277         else
1278                 rdev->pm.dpm.ac_power = false;
1279
1280         radeon_dpm_change_power_state_locked(rdev);
1281
1282         mutex_unlock(&rdev->pm.mutex);
1283
1284 }
1285
1286 void radeon_pm_compute_clocks(struct radeon_device *rdev)
1287 {
1288         if (rdev->pm.pm_method == PM_METHOD_DPM)
1289                 radeon_pm_compute_clocks_dpm(rdev);
1290         else
1291                 radeon_pm_compute_clocks_old(rdev);
1292 }
1293
1294 static bool radeon_pm_in_vbl(struct radeon_device *rdev)
1295 {
1296         int  crtc, vpos, hpos, vbl_status;
1297         bool in_vbl = true;
1298
1299         /* Iterate over all active crtc's. All crtc's must be in vblank,
1300          * otherwise return in_vbl == false.
1301          */
1302         for (crtc = 0; (crtc < rdev->num_crtc) && in_vbl; crtc++) {
1303                 if (rdev->pm.active_crtcs & (1 << crtc)) {
1304                         vbl_status = radeon_get_crtc_scanoutpos(rdev->ddev, crtc, &vpos, &hpos);
1305                         if ((vbl_status & DRM_SCANOUTPOS_VALID) &&
1306                             !(vbl_status & DRM_SCANOUTPOS_INVBL))
1307                                 in_vbl = false;
1308                 }
1309         }
1310
1311         return in_vbl;
1312 }
1313
1314 static bool radeon_pm_debug_check_in_vbl(struct radeon_device *rdev, bool finish)
1315 {
1316         u32 stat_crtc = 0;
1317         bool in_vbl = radeon_pm_in_vbl(rdev);
1318
1319         if (in_vbl == false)
1320                 DRM_DEBUG_DRIVER("not in vbl for pm change %08x at %s\n", stat_crtc,
1321                          finish ? "exit" : "entry");
1322         return in_vbl;
1323 }
1324
1325 static void radeon_dynpm_idle_work_handler(struct work_struct *work)
1326 {
1327         struct radeon_device *rdev;
1328         int resched;
1329         rdev = container_of(work, struct radeon_device,
1330                                 pm.dynpm_idle_work.work);
1331
1332         resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev);
1333         mutex_lock(&rdev->pm.mutex);
1334         if (rdev->pm.dynpm_state == DYNPM_STATE_ACTIVE) {
1335                 int not_processed = 0;
1336                 int i;
1337
1338                 for (i = 0; i < RADEON_NUM_RINGS; ++i) {
1339                         struct radeon_ring *ring = &rdev->ring[i];
1340
1341                         if (ring->ready) {
1342                                 not_processed += radeon_fence_count_emitted(rdev, i);
1343                                 if (not_processed >= 3)
1344                                         break;
1345                         }
1346                 }
1347
1348                 if (not_processed >= 3) { /* should upclock */
1349                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_DOWNCLOCK) {
1350                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1351                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1352                                    rdev->pm.dynpm_can_upclock) {
1353                                 rdev->pm.dynpm_planned_action =
1354                                         DYNPM_ACTION_UPCLOCK;
1355                                 rdev->pm.dynpm_action_timeout = jiffies +
1356                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1357                         }
1358                 } else if (not_processed == 0) { /* should downclock */
1359                         if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_UPCLOCK) {
1360                                 rdev->pm.dynpm_planned_action = DYNPM_ACTION_NONE;
1361                         } else if (rdev->pm.dynpm_planned_action == DYNPM_ACTION_NONE &&
1362                                    rdev->pm.dynpm_can_downclock) {
1363                                 rdev->pm.dynpm_planned_action =
1364                                         DYNPM_ACTION_DOWNCLOCK;
1365                                 rdev->pm.dynpm_action_timeout = jiffies +
1366                                 msecs_to_jiffies(RADEON_RECLOCK_DELAY_MS);
1367                         }
1368                 }
1369
1370                 /* Note, radeon_pm_set_clocks is called with static_switch set
1371                  * to false since we want to wait for vbl to avoid flicker.
1372                  */
1373                 if (rdev->pm.dynpm_planned_action != DYNPM_ACTION_NONE &&
1374                     jiffies > rdev->pm.dynpm_action_timeout) {
1375                         radeon_pm_get_dynpm_state(rdev);
1376                         radeon_pm_set_clocks(rdev);
1377                 }
1378
1379                 schedule_delayed_work(&rdev->pm.dynpm_idle_work,
1380                                       msecs_to_jiffies(RADEON_IDLE_LOOP_MS));
1381         }
1382         mutex_unlock(&rdev->pm.mutex);
1383         ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched);
1384 }
1385
1386 /*
1387  * Debugfs info
1388  */
1389 #if defined(CONFIG_DEBUG_FS)
1390
1391 static int radeon_debugfs_pm_info(struct seq_file *m, void *data)
1392 {
1393         struct drm_info_node *node = (struct drm_info_node *) m->private;
1394         struct drm_device *dev = node->minor->dev;
1395         struct radeon_device *rdev = dev->dev_private;
1396
1397         if (rdev->pm.dpm_enabled) {
1398                 mutex_lock(&rdev->pm.mutex);
1399                 if (rdev->asic->dpm.debugfs_print_current_performance_level)
1400                         radeon_dpm_debugfs_print_current_performance_level(rdev, m);
1401                 else
1402                         seq_printf(m, "Debugfs support not implemented for this asic\n");
1403                 mutex_unlock(&rdev->pm.mutex);
1404         } else {
1405                 seq_printf(m, "default engine clock: %u0 kHz\n", rdev->pm.default_sclk);
1406                 /* radeon_get_engine_clock is not reliable on APUs so just print the current clock */
1407                 if ((rdev->family >= CHIP_PALM) && (rdev->flags & RADEON_IS_IGP))
1408                         seq_printf(m, "current engine clock: %u0 kHz\n", rdev->pm.current_sclk);
1409                 else
1410                         seq_printf(m, "current engine clock: %u0 kHz\n", radeon_get_engine_clock(rdev));
1411                 seq_printf(m, "default memory clock: %u0 kHz\n", rdev->pm.default_mclk);
1412                 if (rdev->asic->pm.get_memory_clock)
1413                         seq_printf(m, "current memory clock: %u0 kHz\n", radeon_get_memory_clock(rdev));
1414                 if (rdev->pm.current_vddc)
1415                         seq_printf(m, "voltage: %u mV\n", rdev->pm.current_vddc);
1416                 if (rdev->asic->pm.get_pcie_lanes)
1417                         seq_printf(m, "PCIE lanes: %d\n", radeon_get_pcie_lanes(rdev));
1418         }
1419
1420         return 0;
1421 }
1422
1423 static struct drm_info_list radeon_pm_info_list[] = {
1424         {"radeon_pm_info", radeon_debugfs_pm_info, 0, NULL},
1425 };
1426 #endif
1427
1428 static int radeon_debugfs_pm_init(struct radeon_device *rdev)
1429 {
1430 #if defined(CONFIG_DEBUG_FS)
1431         return radeon_debugfs_add_files(rdev, radeon_pm_info_list, ARRAY_SIZE(radeon_pm_info_list));
1432 #else
1433         return 0;
1434 #endif
1435 }