2 * Copyright 2009 Advanced Micro Devices, Inc.
3 * Copyright 2009 Red Hat Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be included in
13 * all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
19 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
20 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
21 * OTHER DEALINGS IN THE SOFTWARE.
23 * Authors: Dave Airlie
30 #define R7XX_MAX_SH_GPRS 256
31 #define R7XX_MAX_TEMP_GPRS 16
32 #define R7XX_MAX_SH_THREADS 256
33 #define R7XX_MAX_SH_STACK_ENTRIES 4096
34 #define R7XX_MAX_BACKENDS 8
35 #define R7XX_MAX_BACKENDS_MASK 0xff
36 #define R7XX_MAX_SIMDS 16
37 #define R7XX_MAX_SIMDS_MASK 0xffff
38 #define R7XX_MAX_PIPES 8
39 #define R7XX_MAX_PIPES_MASK 0xff
42 #define CB_COLOR0_BASE 0x28040
43 #define CB_COLOR1_BASE 0x28044
44 #define CB_COLOR2_BASE 0x28048
45 #define CB_COLOR3_BASE 0x2804C
46 #define CB_COLOR4_BASE 0x28050
47 #define CB_COLOR5_BASE 0x28054
48 #define CB_COLOR6_BASE 0x28058
49 #define CB_COLOR7_BASE 0x2805C
50 #define CB_COLOR7_FRAG 0x280FC
52 #define CC_GC_SHADER_PIPE_CONFIG 0x8950
53 #define CC_RB_BACKEND_DISABLE 0x98F4
54 #define BACKEND_DISABLE(x) ((x) << 16)
55 #define CC_SYS_RB_BACKEND_DISABLE 0x3F88
57 #define CGTS_SYS_TCC_DISABLE 0x3F90
58 #define CGTS_TCC_DISABLE 0x9148
59 #define CGTS_USER_SYS_TCC_DISABLE 0x3F94
60 #define CGTS_USER_TCC_DISABLE 0x914C
62 #define CONFIG_MEMSIZE 0x5428
64 #define CP_ME_CNTL 0x86D8
65 #define CP_ME_HALT (1<<28)
66 #define CP_PFP_HALT (1<<26)
67 #define CP_ME_RAM_DATA 0xC160
68 #define CP_ME_RAM_RADDR 0xC158
69 #define CP_ME_RAM_WADDR 0xC15C
70 #define CP_MEQ_THRESHOLDS 0x8764
71 #define STQ_SPLIT(x) ((x) << 0)
72 #define CP_PERFMON_CNTL 0x87FC
73 #define CP_PFP_UCODE_ADDR 0xC150
74 #define CP_PFP_UCODE_DATA 0xC154
75 #define CP_QUEUE_THRESHOLDS 0x8760
76 #define ROQ_IB1_START(x) ((x) << 0)
77 #define ROQ_IB2_START(x) ((x) << 8)
78 #define CP_RB_CNTL 0xC104
79 #define RB_BUFSZ(x) ((x) << 0)
80 #define RB_BLKSZ(x) ((x) << 8)
81 #define RB_NO_UPDATE (1 << 27)
82 #define RB_RPTR_WR_ENA (1 << 31)
83 #define BUF_SWAP_32BIT (2 << 16)
84 #define CP_RB_RPTR 0x8700
85 #define CP_RB_RPTR_ADDR 0xC10C
86 #define CP_RB_RPTR_ADDR_HI 0xC110
87 #define CP_RB_RPTR_WR 0xC108
88 #define CP_RB_WPTR 0xC114
89 #define CP_RB_WPTR_ADDR 0xC118
90 #define CP_RB_WPTR_ADDR_HI 0xC11C
91 #define CP_RB_WPTR_DELAY 0x8704
92 #define CP_SEM_WAIT_TIMER 0x85BC
94 #define DB_DEBUG3 0x98B0
95 #define DB_CLK_OFF_DELAY(x) ((x) << 11)
96 #define DB_DEBUG4 0x9B8C
97 #define DISABLE_TILE_COVERED_FOR_PS_ITER (1 << 6)
99 #define DCP_TILING_CONFIG 0x6CA0
100 #define PIPE_TILING(x) ((x) << 1)
101 #define BANK_TILING(x) ((x) << 4)
102 #define GROUP_SIZE(x) ((x) << 6)
103 #define ROW_TILING(x) ((x) << 8)
104 #define BANK_SWAPS(x) ((x) << 11)
105 #define SAMPLE_SPLIT(x) ((x) << 14)
106 #define BACKEND_MAP(x) ((x) << 16)
108 #define GB_TILING_CONFIG 0x98F0
109 #define PIPE_TILING__SHIFT 1
110 #define PIPE_TILING__MASK 0x0000000e
112 #define DMA_TILING_CONFIG 0x3ec8
113 #define DMA_TILING_CONFIG2 0xd0b8
115 #define GC_USER_SHADER_PIPE_CONFIG 0x8954
116 #define INACTIVE_QD_PIPES(x) ((x) << 8)
117 #define INACTIVE_QD_PIPES_MASK 0x0000FF00
118 #define INACTIVE_QD_PIPES_SHIFT 8
119 #define INACTIVE_SIMDS(x) ((x) << 16)
120 #define INACTIVE_SIMDS_MASK 0x00FF0000
122 #define GRBM_CNTL 0x8000
123 #define GRBM_READ_TIMEOUT(x) ((x) << 0)
124 #define GRBM_SOFT_RESET 0x8020
125 #define SOFT_RESET_CP (1<<0)
126 #define GRBM_STATUS 0x8010
127 #define CMDFIFO_AVAIL_MASK 0x0000000F
128 #define GUI_ACTIVE (1<<31)
129 #define GRBM_STATUS2 0x8014
131 #define CG_CLKPIN_CNTL 0x660
132 # define MUX_TCLK_TO_XCLK (1 << 8)
133 # define XTALIN_DIVIDE (1 << 9)
135 #define CG_MULT_THERMAL_STATUS 0x740
136 #define ASIC_T(x) ((x) << 16)
137 #define ASIC_T_MASK 0x3FF0000
138 #define ASIC_T_SHIFT 16
140 #define HDP_HOST_PATH_CNTL 0x2C00
141 #define HDP_NONSURFACE_BASE 0x2C04
142 #define HDP_NONSURFACE_INFO 0x2C08
143 #define HDP_NONSURFACE_SIZE 0x2C0C
144 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0
145 #define HDP_TILING_CONFIG 0x2F3C
146 #define HDP_DEBUG1 0x2F34
148 #define MC_SHARED_CHMAP 0x2004
149 #define NOOFCHAN_SHIFT 12
150 #define NOOFCHAN_MASK 0x00003000
151 #define MC_SHARED_CHREMAP 0x2008
153 #define MC_ARB_RAMCFG 0x2760
154 #define NOOFBANK_SHIFT 0
155 #define NOOFBANK_MASK 0x00000003
156 #define NOOFRANK_SHIFT 2
157 #define NOOFRANK_MASK 0x00000004
158 #define NOOFROWS_SHIFT 3
159 #define NOOFROWS_MASK 0x00000038
160 #define NOOFCOLS_SHIFT 6
161 #define NOOFCOLS_MASK 0x000000C0
162 #define CHANSIZE_SHIFT 8
163 #define CHANSIZE_MASK 0x00000100
164 #define BURSTLENGTH_SHIFT 9
165 #define BURSTLENGTH_MASK 0x00000200
166 #define CHANSIZE_OVERRIDE (1 << 11)
167 #define MC_VM_AGP_TOP 0x2028
168 #define MC_VM_AGP_BOT 0x202C
169 #define MC_VM_AGP_BASE 0x2030
170 #define MC_VM_FB_LOCATION 0x2024
171 #define MC_VM_MB_L1_TLB0_CNTL 0x2234
172 #define MC_VM_MB_L1_TLB1_CNTL 0x2238
173 #define MC_VM_MB_L1_TLB2_CNTL 0x223C
174 #define MC_VM_MB_L1_TLB3_CNTL 0x2240
175 #define ENABLE_L1_TLB (1 << 0)
176 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1)
177 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3)
178 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3)
179 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3)
180 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3)
181 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5)
182 #define EFFECTIVE_L1_TLB_SIZE(x) ((x)<<15)
183 #define EFFECTIVE_L1_QUEUE_SIZE(x) ((x)<<18)
184 #define MC_VM_MD_L1_TLB0_CNTL 0x2654
185 #define MC_VM_MD_L1_TLB1_CNTL 0x2658
186 #define MC_VM_MD_L1_TLB2_CNTL 0x265C
187 #define MC_VM_MD_L1_TLB3_CNTL 0x2698
188 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C
189 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038
190 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034
192 #define PA_CL_ENHANCE 0x8A14
193 #define CLIP_VTX_REORDER_ENA (1 << 0)
194 #define NUM_CLIP_SEQ(x) ((x) << 1)
195 #define PA_SC_AA_CONFIG 0x28C04
196 #define PA_SC_CLIPRECT_RULE 0x2820C
197 #define PA_SC_EDGERULE 0x28230
198 #define PA_SC_FIFO_SIZE 0x8BCC
199 #define SC_PRIM_FIFO_SIZE(x) ((x) << 0)
200 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 12)
201 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24
202 #define FORCE_EOV_MAX_CLK_CNT(x) ((x)<<0)
203 #define FORCE_EOV_MAX_REZ_CNT(x) ((x)<<16)
204 #define PA_SC_LINE_STIPPLE 0x28A0C
205 #define PA_SC_LINE_STIPPLE_STATE 0x8B10
206 #define PA_SC_MODE_CNTL 0x28A4C
207 #define PA_SC_MULTI_CHIP_CNTL 0x8B20
208 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 20)
210 #define SCRATCH_REG0 0x8500
211 #define SCRATCH_REG1 0x8504
212 #define SCRATCH_REG2 0x8508
213 #define SCRATCH_REG3 0x850C
214 #define SCRATCH_REG4 0x8510
215 #define SCRATCH_REG5 0x8514
216 #define SCRATCH_REG6 0x8518
217 #define SCRATCH_REG7 0x851C
218 #define SCRATCH_UMSK 0x8540
219 #define SCRATCH_ADDR 0x8544
221 #define SMX_SAR_CTL0 0xA008
222 #define SMX_DC_CTL0 0xA020
223 #define USE_HASH_FUNCTION (1 << 0)
224 #define CACHE_DEPTH(x) ((x) << 1)
225 #define FLUSH_ALL_ON_EVENT (1 << 10)
226 #define STALL_ON_EVENT (1 << 11)
227 #define SMX_EVENT_CTL 0xA02C
228 #define ES_FLUSH_CTL(x) ((x) << 0)
229 #define GS_FLUSH_CTL(x) ((x) << 3)
230 #define ACK_FLUSH_CTL(x) ((x) << 6)
231 #define SYNC_FLUSH_CTL (1 << 8)
233 #define SPI_CONFIG_CNTL 0x9100
234 #define GPR_WRITE_PRIORITY(x) ((x) << 0)
235 #define DISABLE_INTERP_1 (1 << 5)
236 #define SPI_CONFIG_CNTL_1 0x913C
237 #define VTX_DONE_DELAY(x) ((x) << 0)
238 #define INTERP_ONE_PRIM_PER_ROW (1 << 4)
239 #define SPI_INPUT_Z 0x286D8
240 #define SPI_PS_IN_CONTROL_0 0x286CC
241 #define NUM_INTERP(x) ((x)<<0)
242 #define POSITION_ENA (1<<8)
243 #define POSITION_CENTROID (1<<9)
244 #define POSITION_ADDR(x) ((x)<<10)
245 #define PARAM_GEN(x) ((x)<<15)
246 #define PARAM_GEN_ADDR(x) ((x)<<19)
247 #define BARYC_SAMPLE_CNTL(x) ((x)<<26)
248 #define PERSP_GRADIENT_ENA (1<<28)
249 #define LINEAR_GRADIENT_ENA (1<<29)
250 #define POSITION_SAMPLE (1<<30)
251 #define BARYC_AT_SAMPLE_ENA (1<<31)
253 #define SQ_CONFIG 0x8C00
254 #define VC_ENABLE (1 << 0)
255 #define EXPORT_SRC_C (1 << 1)
256 #define DX9_CONSTS (1 << 2)
257 #define ALU_INST_PREFER_VECTOR (1 << 3)
258 #define DX10_CLAMP (1 << 4)
259 #define CLAUSE_SEQ_PRIO(x) ((x) << 8)
260 #define PS_PRIO(x) ((x) << 24)
261 #define VS_PRIO(x) ((x) << 26)
262 #define GS_PRIO(x) ((x) << 28)
263 #define SQ_DYN_GPR_SIZE_SIMD_AB_0 0x8DB0
264 #define SIMDA_RING0(x) ((x)<<0)
265 #define SIMDA_RING1(x) ((x)<<8)
266 #define SIMDB_RING0(x) ((x)<<16)
267 #define SIMDB_RING1(x) ((x)<<24)
268 #define SQ_DYN_GPR_SIZE_SIMD_AB_1 0x8DB4
269 #define SQ_DYN_GPR_SIZE_SIMD_AB_2 0x8DB8
270 #define SQ_DYN_GPR_SIZE_SIMD_AB_3 0x8DBC
271 #define SQ_DYN_GPR_SIZE_SIMD_AB_4 0x8DC0
272 #define SQ_DYN_GPR_SIZE_SIMD_AB_5 0x8DC4
273 #define SQ_DYN_GPR_SIZE_SIMD_AB_6 0x8DC8
274 #define SQ_DYN_GPR_SIZE_SIMD_AB_7 0x8DCC
275 #define ES_PRIO(x) ((x) << 30)
276 #define SQ_GPR_RESOURCE_MGMT_1 0x8C04
277 #define NUM_PS_GPRS(x) ((x) << 0)
278 #define NUM_VS_GPRS(x) ((x) << 16)
279 #define DYN_GPR_ENABLE (1 << 27)
280 #define NUM_CLAUSE_TEMP_GPRS(x) ((x) << 28)
281 #define SQ_GPR_RESOURCE_MGMT_2 0x8C08
282 #define NUM_GS_GPRS(x) ((x) << 0)
283 #define NUM_ES_GPRS(x) ((x) << 16)
284 #define SQ_MS_FIFO_SIZES 0x8CF0
285 #define CACHE_FIFO_SIZE(x) ((x) << 0)
286 #define FETCH_FIFO_HIWATER(x) ((x) << 8)
287 #define DONE_FIFO_HIWATER(x) ((x) << 16)
288 #define ALU_UPDATE_FIFO_HIWATER(x) ((x) << 24)
289 #define SQ_STACK_RESOURCE_MGMT_1 0x8C10
290 #define NUM_PS_STACK_ENTRIES(x) ((x) << 0)
291 #define NUM_VS_STACK_ENTRIES(x) ((x) << 16)
292 #define SQ_STACK_RESOURCE_MGMT_2 0x8C14
293 #define NUM_GS_STACK_ENTRIES(x) ((x) << 0)
294 #define NUM_ES_STACK_ENTRIES(x) ((x) << 16)
295 #define SQ_THREAD_RESOURCE_MGMT 0x8C0C
296 #define NUM_PS_THREADS(x) ((x) << 0)
297 #define NUM_VS_THREADS(x) ((x) << 8)
298 #define NUM_GS_THREADS(x) ((x) << 16)
299 #define NUM_ES_THREADS(x) ((x) << 24)
301 #define SX_DEBUG_1 0x9058
302 #define ENABLE_NEW_SMX_ADDRESS (1 << 16)
303 #define SX_EXPORT_BUFFER_SIZES 0x900C
304 #define COLOR_BUFFER_SIZE(x) ((x) << 0)
305 #define POSITION_BUFFER_SIZE(x) ((x) << 8)
306 #define SMX_BUFFER_SIZE(x) ((x) << 16)
307 #define SX_MISC 0x28350
309 #define TA_CNTL_AUX 0x9508
310 #define DISABLE_CUBE_WRAP (1 << 0)
311 #define DISABLE_CUBE_ANISO (1 << 1)
312 #define SYNC_GRADIENT (1 << 24)
313 #define SYNC_WALKER (1 << 25)
314 #define SYNC_ALIGNER (1 << 26)
315 #define BILINEAR_PRECISION_6_BIT (0 << 31)
316 #define BILINEAR_PRECISION_8_BIT (1 << 31)
318 #define TCP_CNTL 0x9610
319 #define TCP_CHAN_STEER 0x9614
321 #define VC_ENHANCE 0x9714
323 #define VGT_CACHE_INVALIDATION 0x88C4
324 #define CACHE_INVALIDATION(x) ((x)<<0)
328 #define AUTO_INVLD_EN(x) ((x) << 6)
332 #define ES_AND_GS_AUTO 3
333 #define VGT_ES_PER_GS 0x88CC
334 #define VGT_GS_PER_ES 0x88C8
335 #define VGT_GS_PER_VS 0x88E8
336 #define VGT_GS_VERTEX_REUSE 0x88D4
337 #define VGT_NUM_INSTANCES 0x8974
338 #define VGT_OUT_DEALLOC_CNTL 0x28C5C
339 #define DEALLOC_DIST_MASK 0x0000007F
340 #define VGT_STRMOUT_EN 0x28AB0
341 #define VGT_VERTEX_REUSE_BLOCK_CNTL 0x28C58
342 #define VTX_REUSE_DEPTH_MASK 0x000000FF
344 #define VM_CONTEXT0_CNTL 0x1410
345 #define ENABLE_CONTEXT (1 << 0)
346 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1)
347 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4)
348 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153C
349 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C
350 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155C
351 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518
352 #define VM_L2_CNTL 0x1400
353 #define ENABLE_L2_CACHE (1 << 0)
354 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1)
355 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9)
356 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 14)
357 #define VM_L2_CNTL2 0x1404
358 #define INVALIDATE_ALL_L1_TLBS (1 << 0)
359 #define INVALIDATE_L2_CACHE (1 << 1)
360 #define VM_L2_CNTL3 0x1408
361 #define BANK_SELECT(x) ((x) << 0)
362 #define CACHE_UPDATE_MODE(x) ((x) << 6)
363 #define VM_L2_STATUS 0x140C
364 #define L2_BUSY (1 << 0)
366 #define WAIT_UNTIL 0x8040
369 #define DMA_RB_RPTR 0xd008
370 #define DMA_RB_WPTR 0xd00c
372 /* async DMA packets */
373 #define DMA_PACKET(cmd, t, s, n) ((((cmd) & 0xF) << 28) | \
374 (((t) & 0x1) << 23) | \
375 (((s) & 0x1) << 22) | \
376 (((n) & 0xFFFF) << 0))
377 /* async DMA Packet types */
378 #define DMA_PACKET_WRITE 0x2
379 #define DMA_PACKET_COPY 0x3
380 #define DMA_PACKET_INDIRECT_BUFFER 0x4
381 #define DMA_PACKET_SEMAPHORE 0x5
382 #define DMA_PACKET_FENCE 0x6
383 #define DMA_PACKET_TRAP 0x7
384 #define DMA_PACKET_CONSTANT_FILL 0xd
385 #define DMA_PACKET_NOP 0xf
388 #define SRBM_STATUS 0x0E50
391 #define HDMI_CONTROL 0x7400
392 # define HDMI_KEEPOUT_MODE (1 << 0)
393 # define HDMI_PACKET_GEN_VERSION (1 << 4) /* 0 = r6xx compat */
394 # define HDMI_ERROR_ACK (1 << 8)
395 # define HDMI_ERROR_MASK (1 << 9)
396 #define HDMI_STATUS 0x7404
397 # define HDMI_ACTIVE_AVMUTE (1 << 0)
398 # define HDMI_AUDIO_PACKET_ERROR (1 << 16)
399 # define HDMI_VBI_PACKET_ERROR (1 << 20)
400 #define HDMI_AUDIO_PACKET_CONTROL 0x7408
401 # define HDMI_AUDIO_DELAY_EN(x) (((x) & 3) << 4)
402 # define HDMI_AUDIO_PACKETS_PER_LINE(x) (((x) & 0x1f) << 16)
403 #define HDMI_ACR_PACKET_CONTROL 0x740c
404 # define HDMI_ACR_SEND (1 << 0)
405 # define HDMI_ACR_CONT (1 << 1)
406 # define HDMI_ACR_SELECT(x) (((x) & 3) << 4)
407 # define HDMI_ACR_HW 0
408 # define HDMI_ACR_32 1
409 # define HDMI_ACR_44 2
410 # define HDMI_ACR_48 3
411 # define HDMI_ACR_SOURCE (1 << 8) /* 0 - hw; 1 - cts value */
412 # define HDMI_ACR_AUTO_SEND (1 << 12)
413 #define HDMI_VBI_PACKET_CONTROL 0x7410
414 # define HDMI_NULL_SEND (1 << 0)
415 # define HDMI_GC_SEND (1 << 4)
416 # define HDMI_GC_CONT (1 << 5) /* 0 - once; 1 - every frame */
417 #define HDMI_INFOFRAME_CONTROL0 0x7414
418 # define HDMI_AVI_INFO_SEND (1 << 0)
419 # define HDMI_AVI_INFO_CONT (1 << 1)
420 # define HDMI_AUDIO_INFO_SEND (1 << 4)
421 # define HDMI_AUDIO_INFO_CONT (1 << 5)
422 # define HDMI_MPEG_INFO_SEND (1 << 8)
423 # define HDMI_MPEG_INFO_CONT (1 << 9)
424 #define HDMI_INFOFRAME_CONTROL1 0x7418
425 # define HDMI_AVI_INFO_LINE(x) (((x) & 0x3f) << 0)
426 # define HDMI_AUDIO_INFO_LINE(x) (((x) & 0x3f) << 8)
427 # define HDMI_MPEG_INFO_LINE(x) (((x) & 0x3f) << 16)
428 #define HDMI_GENERIC_PACKET_CONTROL 0x741c
429 # define HDMI_GENERIC0_SEND (1 << 0)
430 # define HDMI_GENERIC0_CONT (1 << 1)
431 # define HDMI_GENERIC1_SEND (1 << 4)
432 # define HDMI_GENERIC1_CONT (1 << 5)
433 # define HDMI_GENERIC0_LINE(x) (((x) & 0x3f) << 16)
434 # define HDMI_GENERIC1_LINE(x) (((x) & 0x3f) << 24)
435 #define HDMI_GC 0x7428
436 # define HDMI_GC_AVMUTE (1 << 0)
437 #define AFMT_AUDIO_PACKET_CONTROL2 0x742c
438 # define AFMT_AUDIO_LAYOUT_OVRD (1 << 0)
439 # define AFMT_AUDIO_LAYOUT_SELECT (1 << 1)
440 # define AFMT_60958_CS_SOURCE (1 << 4)
441 # define AFMT_AUDIO_CHANNEL_ENABLE(x) (((x) & 0xff) << 8)
442 # define AFMT_DP_AUDIO_STREAM_ID(x) (((x) & 0xff) << 16)
443 #define AFMT_AVI_INFO0 0x7454
444 # define AFMT_AVI_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
445 # define AFMT_AVI_INFO_S(x) (((x) & 3) << 8)
446 # define AFMT_AVI_INFO_B(x) (((x) & 3) << 10)
447 # define AFMT_AVI_INFO_A(x) (((x) & 1) << 12)
448 # define AFMT_AVI_INFO_Y(x) (((x) & 3) << 13)
449 # define AFMT_AVI_INFO_Y_RGB 0
450 # define AFMT_AVI_INFO_Y_YCBCR422 1
451 # define AFMT_AVI_INFO_Y_YCBCR444 2
452 # define AFMT_AVI_INFO_Y_A_B_S(x) (((x) & 0xff) << 8)
453 # define AFMT_AVI_INFO_R(x) (((x) & 0xf) << 16)
454 # define AFMT_AVI_INFO_M(x) (((x) & 0x3) << 20)
455 # define AFMT_AVI_INFO_C(x) (((x) & 0x3) << 22)
456 # define AFMT_AVI_INFO_C_M_R(x) (((x) & 0xff) << 16)
457 # define AFMT_AVI_INFO_SC(x) (((x) & 0x3) << 24)
458 # define AFMT_AVI_INFO_Q(x) (((x) & 0x3) << 26)
459 # define AFMT_AVI_INFO_EC(x) (((x) & 0x3) << 28)
460 # define AFMT_AVI_INFO_ITC(x) (((x) & 0x1) << 31)
461 # define AFMT_AVI_INFO_ITC_EC_Q_SC(x) (((x) & 0xff) << 24)
462 #define AFMT_AVI_INFO1 0x7458
463 # define AFMT_AVI_INFO_VIC(x) (((x) & 0x7f) << 0) /* don't use avi infoframe v1 */
464 # define AFMT_AVI_INFO_PR(x) (((x) & 0xf) << 8) /* don't use avi infoframe v1 */
465 # define AFMT_AVI_INFO_TOP(x) (((x) & 0xffff) << 16)
466 #define AFMT_AVI_INFO2 0x745c
467 # define AFMT_AVI_INFO_BOTTOM(x) (((x) & 0xffff) << 0)
468 # define AFMT_AVI_INFO_LEFT(x) (((x) & 0xffff) << 16)
469 #define AFMT_AVI_INFO3 0x7460
470 # define AFMT_AVI_INFO_RIGHT(x) (((x) & 0xffff) << 0)
471 # define AFMT_AVI_INFO_VERSION(x) (((x) & 3) << 24)
472 #define AFMT_MPEG_INFO0 0x7464
473 # define AFMT_MPEG_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
474 # define AFMT_MPEG_INFO_MB0(x) (((x) & 0xff) << 8)
475 # define AFMT_MPEG_INFO_MB1(x) (((x) & 0xff) << 16)
476 # define AFMT_MPEG_INFO_MB2(x) (((x) & 0xff) << 24)
477 #define AFMT_MPEG_INFO1 0x7468
478 # define AFMT_MPEG_INFO_MB3(x) (((x) & 0xff) << 0)
479 # define AFMT_MPEG_INFO_MF(x) (((x) & 3) << 8)
480 # define AFMT_MPEG_INFO_FR(x) (((x) & 1) << 12)
481 #define AFMT_GENERIC0_HDR 0x746c
482 #define AFMT_GENERIC0_0 0x7470
483 #define AFMT_GENERIC0_1 0x7474
484 #define AFMT_GENERIC0_2 0x7478
485 #define AFMT_GENERIC0_3 0x747c
486 #define AFMT_GENERIC0_4 0x7480
487 #define AFMT_GENERIC0_5 0x7484
488 #define AFMT_GENERIC0_6 0x7488
489 #define AFMT_GENERIC1_HDR 0x748c
490 #define AFMT_GENERIC1_0 0x7490
491 #define AFMT_GENERIC1_1 0x7494
492 #define AFMT_GENERIC1_2 0x7498
493 #define AFMT_GENERIC1_3 0x749c
494 #define AFMT_GENERIC1_4 0x74a0
495 #define AFMT_GENERIC1_5 0x74a4
496 #define AFMT_GENERIC1_6 0x74a8
497 #define HDMI_ACR_32_0 0x74ac
498 # define HDMI_ACR_CTS_32(x) (((x) & 0xfffff) << 12)
499 #define HDMI_ACR_32_1 0x74b0
500 # define HDMI_ACR_N_32(x) (((x) & 0xfffff) << 0)
501 #define HDMI_ACR_44_0 0x74b4
502 # define HDMI_ACR_CTS_44(x) (((x) & 0xfffff) << 12)
503 #define HDMI_ACR_44_1 0x74b8
504 # define HDMI_ACR_N_44(x) (((x) & 0xfffff) << 0)
505 #define HDMI_ACR_48_0 0x74bc
506 # define HDMI_ACR_CTS_48(x) (((x) & 0xfffff) << 12)
507 #define HDMI_ACR_48_1 0x74c0
508 # define HDMI_ACR_N_48(x) (((x) & 0xfffff) << 0)
509 #define HDMI_ACR_STATUS_0 0x74c4
510 #define HDMI_ACR_STATUS_1 0x74c8
511 #define AFMT_AUDIO_INFO0 0x74cc
512 # define AFMT_AUDIO_INFO_CHECKSUM(x) (((x) & 0xff) << 0)
513 # define AFMT_AUDIO_INFO_CC(x) (((x) & 7) << 8)
514 # define AFMT_AUDIO_INFO_CHECKSUM_OFFSET(x) (((x) & 0xff) << 16)
515 #define AFMT_AUDIO_INFO1 0x74d0
516 # define AFMT_AUDIO_INFO_CA(x) (((x) & 0xff) << 0)
517 # define AFMT_AUDIO_INFO_LSV(x) (((x) & 0xf) << 11)
518 # define AFMT_AUDIO_INFO_DM_INH(x) (((x) & 1) << 15)
519 # define AFMT_AUDIO_INFO_DM_INH_LSV(x) (((x) & 0xff) << 8)
520 #define AFMT_60958_0 0x74d4
521 # define AFMT_60958_CS_A(x) (((x) & 1) << 0)
522 # define AFMT_60958_CS_B(x) (((x) & 1) << 1)
523 # define AFMT_60958_CS_C(x) (((x) & 1) << 2)
524 # define AFMT_60958_CS_D(x) (((x) & 3) << 3)
525 # define AFMT_60958_CS_MODE(x) (((x) & 3) << 6)
526 # define AFMT_60958_CS_CATEGORY_CODE(x) (((x) & 0xff) << 8)
527 # define AFMT_60958_CS_SOURCE_NUMBER(x) (((x) & 0xf) << 16)
528 # define AFMT_60958_CS_CHANNEL_NUMBER_L(x) (((x) & 0xf) << 20)
529 # define AFMT_60958_CS_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 24)
530 # define AFMT_60958_CS_CLOCK_ACCURACY(x) (((x) & 3) << 28)
531 #define AFMT_60958_1 0x74d8
532 # define AFMT_60958_CS_WORD_LENGTH(x) (((x) & 0xf) << 0)
533 # define AFMT_60958_CS_ORIGINAL_SAMPLING_FREQUENCY(x) (((x) & 0xf) << 4)
534 # define AFMT_60958_CS_VALID_L(x) (((x) & 1) << 16)
535 # define AFMT_60958_CS_VALID_R(x) (((x) & 1) << 18)
536 # define AFMT_60958_CS_CHANNEL_NUMBER_R(x) (((x) & 0xf) << 20)
537 #define AFMT_AUDIO_CRC_CONTROL 0x74dc
538 # define AFMT_AUDIO_CRC_EN (1 << 0)
539 #define AFMT_RAMP_CONTROL0 0x74e0
540 # define AFMT_RAMP_MAX_COUNT(x) (((x) & 0xffffff) << 0)
541 # define AFMT_RAMP_DATA_SIGN (1 << 31)
542 #define AFMT_RAMP_CONTROL1 0x74e4
543 # define AFMT_RAMP_MIN_COUNT(x) (((x) & 0xffffff) << 0)
544 # define AFMT_AUDIO_TEST_CH_DISABLE(x) (((x) & 0xff) << 24)
545 #define AFMT_RAMP_CONTROL2 0x74e8
546 # define AFMT_RAMP_INC_COUNT(x) (((x) & 0xffffff) << 0)
547 #define AFMT_RAMP_CONTROL3 0x74ec
548 # define AFMT_RAMP_DEC_COUNT(x) (((x) & 0xffffff) << 0)
549 #define AFMT_60958_2 0x74f0
550 # define AFMT_60958_CS_CHANNEL_NUMBER_2(x) (((x) & 0xf) << 0)
551 # define AFMT_60958_CS_CHANNEL_NUMBER_3(x) (((x) & 0xf) << 4)
552 # define AFMT_60958_CS_CHANNEL_NUMBER_4(x) (((x) & 0xf) << 8)
553 # define AFMT_60958_CS_CHANNEL_NUMBER_5(x) (((x) & 0xf) << 12)
554 # define AFMT_60958_CS_CHANNEL_NUMBER_6(x) (((x) & 0xf) << 16)
555 # define AFMT_60958_CS_CHANNEL_NUMBER_7(x) (((x) & 0xf) << 20)
556 #define AFMT_STATUS 0x7600
557 # define AFMT_AUDIO_ENABLE (1 << 4)
558 # define AFMT_AZ_FORMAT_WTRIG (1 << 28)
559 # define AFMT_AZ_FORMAT_WTRIG_INT (1 << 29)
560 # define AFMT_AZ_AUDIO_ENABLE_CHG (1 << 30)
561 #define AFMT_AUDIO_PACKET_CONTROL 0x7604
562 # define AFMT_AUDIO_SAMPLE_SEND (1 << 0)
563 # define AFMT_AUDIO_TEST_EN (1 << 12)
564 # define AFMT_AUDIO_CHANNEL_SWAP (1 << 24)
565 # define AFMT_60958_CS_UPDATE (1 << 26)
566 # define AFMT_AZ_AUDIO_ENABLE_CHG_MASK (1 << 27)
567 # define AFMT_AZ_FORMAT_WTRIG_MASK (1 << 28)
568 # define AFMT_AZ_FORMAT_WTRIG_ACK (1 << 29)
569 # define AFMT_AZ_AUDIO_ENABLE_CHG_ACK (1 << 30)
570 #define AFMT_VBI_PACKET_CONTROL 0x7608
571 # define AFMT_GENERIC0_UPDATE (1 << 2)
572 #define AFMT_INFOFRAME_CONTROL0 0x760c
573 # define AFMT_AUDIO_INFO_SOURCE (1 << 6) /* 0 - sound block; 1 - hmdi regs */
574 # define AFMT_AUDIO_INFO_UPDATE (1 << 7)
575 # define AFMT_MPEG_INFO_UPDATE (1 << 10)
576 #define AFMT_GENERIC0_7 0x7610
577 /* second instance starts at 0x7800 */
578 #define HDMI_OFFSET0 (0x7400 - 0x7400)
579 #define HDMI_OFFSET1 (0x7800 - 0x7400)
581 /* DCE3.2 ELD audio interface */
582 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR0 0x71c8 /* LPCM */
583 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR1 0x71cc /* AC3 */
584 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR2 0x71d0 /* MPEG1 */
585 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR3 0x71d4 /* MP3 */
586 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR4 0x71d8 /* MPEG2 */
587 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR5 0x71dc /* AAC */
588 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR6 0x71e0 /* DTS */
589 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR7 0x71e4 /* ATRAC */
590 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR8 0x71e8 /* one bit audio - leave at 0 (default) */
591 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR9 0x71ec /* Dolby Digital */
592 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR10 0x71f0 /* DTS-HD */
593 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR11 0x71f4 /* MAT-MLP */
594 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR12 0x71f8 /* DTS */
595 #define AZ_F0_CODEC_PIN0_CONTROL_AUDIO_DESCRIPTOR13 0x71fc /* WMA Pro */
596 # define MAX_CHANNELS(x) (((x) & 0x7) << 0)
597 /* max channels minus one. 7 = 8 channels */
598 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8)
599 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16)
600 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */
601 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO
611 #define AZ_HOT_PLUG_CONTROL 0x7300
612 # define AZ_FORCE_CODEC_WAKE (1 << 0)
613 # define PIN0_JACK_DETECTION_ENABLE (1 << 4)
614 # define PIN1_JACK_DETECTION_ENABLE (1 << 5)
615 # define PIN2_JACK_DETECTION_ENABLE (1 << 6)
616 # define PIN3_JACK_DETECTION_ENABLE (1 << 7)
617 # define PIN0_UNSOLICITED_RESPONSE_ENABLE (1 << 8)
618 # define PIN1_UNSOLICITED_RESPONSE_ENABLE (1 << 9)
619 # define PIN2_UNSOLICITED_RESPONSE_ENABLE (1 << 10)
620 # define PIN3_UNSOLICITED_RESPONSE_ENABLE (1 << 11)
621 # define CODEC_HOT_PLUG_ENABLE (1 << 12)
622 # define PIN0_AUDIO_ENABLED (1 << 24)
623 # define PIN1_AUDIO_ENABLED (1 << 25)
624 # define PIN2_AUDIO_ENABLED (1 << 26)
625 # define PIN3_AUDIO_ENABLED (1 << 27)
626 # define AUDIO_ENABLED (1 << 31)
629 #define D1GRPH_PRIMARY_SURFACE_ADDRESS 0x6110
630 #define D1GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6914
631 #define D2GRPH_PRIMARY_SURFACE_ADDRESS_HIGH 0x6114
632 #define D1GRPH_SECONDARY_SURFACE_ADDRESS 0x6118
633 #define D1GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x691c
634 #define D2GRPH_SECONDARY_SURFACE_ADDRESS_HIGH 0x611c
636 /* PCIE link stuff */
637 #define PCIE_LC_TRAINING_CNTL 0xa1 /* PCIE_P */
638 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */
639 # define LC_LINK_WIDTH_SHIFT 0
640 # define LC_LINK_WIDTH_MASK 0x7
641 # define LC_LINK_WIDTH_X0 0
642 # define LC_LINK_WIDTH_X1 1
643 # define LC_LINK_WIDTH_X2 2
644 # define LC_LINK_WIDTH_X4 3
645 # define LC_LINK_WIDTH_X8 4
646 # define LC_LINK_WIDTH_X16 6
647 # define LC_LINK_WIDTH_RD_SHIFT 4
648 # define LC_LINK_WIDTH_RD_MASK 0x70
649 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7)
650 # define LC_RECONFIG_NOW (1 << 8)
651 # define LC_RENEGOTIATION_SUPPORT (1 << 9)
652 # define LC_RENEGOTIATE_EN (1 << 10)
653 # define LC_SHORT_RECONFIG_EN (1 << 11)
654 # define LC_UPCONFIGURE_SUPPORT (1 << 12)
655 # define LC_UPCONFIGURE_DIS (1 << 13)
656 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */
657 # define LC_GEN2_EN_STRAP (1 << 0)
658 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 1)
659 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 5)
660 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 6)
661 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 8)
662 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 3
663 # define LC_CURRENT_DATA_RATE (1 << 11)
664 # define LC_VOLTAGE_TIMER_SEL_MASK (0xf << 14)
665 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 21)
666 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 23)
667 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 24)
668 #define MM_CFGREGS_CNTL 0x544c
669 # define MM_WR_TO_CFG_EN (1 << 3)
670 #define LINK_CNTL2 0x88 /* F0 */
671 # define TARGET_LINK_SPEED_MASK (0xf << 0)
672 # define SELECTABLE_DEEMPHASIS (1 << 6)
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