2 * Copyright 2012 Advanced Micro Devices, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
28 #include "cypress_dpm.h"
30 #include <linux/seq_file.h>
32 #define SUMO_MAX_DEEPSLEEP_DIVIDER_ID 5
33 #define SUMO_MINIMUM_ENGINE_CLOCK 800
34 #define BOOST_DPM_LEVEL 7
36 static const u32 sumo_utc[SUMO_PM_NUMBER_OF_TC] =
55 static const u32 sumo_dtc[SUMO_PM_NUMBER_OF_TC] =
74 struct sumo_ps *sumo_get_ps(struct radeon_ps *rps)
76 struct sumo_ps *ps = rps->ps_priv;
81 struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev)
83 struct sumo_power_info *pi = rdev->pm.dpm.priv;
88 static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable)
91 WREG32_P(SCLK_PWRMGT_CNTL, DYN_GFX_CLK_OFF_EN, ~DYN_GFX_CLK_OFF_EN);
93 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~DYN_GFX_CLK_OFF_EN);
94 WREG32_P(SCLK_PWRMGT_CNTL, GFX_CLK_FORCE_ON, ~GFX_CLK_FORCE_ON);
95 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~GFX_CLK_FORCE_ON);
96 RREG32(GB_ADDR_CONFIG);
100 #define CGCG_CGTT_LOCAL0_MASK 0xE5BFFFFF
101 #define CGCG_CGTT_LOCAL1_MASK 0xEFFF07FF
103 static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable)
108 local0 = RREG32(CG_CGTT_LOCAL_0);
109 local1 = RREG32(CG_CGTT_LOCAL_1);
112 WREG32(CG_CGTT_LOCAL_0, (0 & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
113 WREG32(CG_CGTT_LOCAL_1, (0 & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
115 WREG32(CG_CGTT_LOCAL_0, (0xFFFFFFFF & CGCG_CGTT_LOCAL0_MASK) | (local0 & ~CGCG_CGTT_LOCAL0_MASK) );
116 WREG32(CG_CGTT_LOCAL_1, (0xFFFFCFFF & CGCG_CGTT_LOCAL1_MASK) | (local1 & ~CGCG_CGTT_LOCAL1_MASK) );
120 static void sumo_program_git(struct radeon_device *rdev)
123 u32 xclk = radeon_get_xclk(rdev);
125 r600_calculate_u_and_p(SUMO_GICST_DFLT,
128 WREG32_P(CG_GIT, CG_GICST(p), ~CG_GICST_MASK);
131 static void sumo_program_grsd(struct radeon_device *rdev)
134 u32 xclk = radeon_get_xclk(rdev);
135 u32 grs = 256 * 25 / 100;
137 r600_calculate_u_and_p(1, xclk, 14, &p, &u);
139 WREG32(CG_GCOOR, PHC(grs) | SDC(p) | SU(u));
142 void sumo_gfx_clockgating_initialize(struct radeon_device *rdev)
144 sumo_program_git(rdev);
145 sumo_program_grsd(rdev);
148 static void sumo_gfx_powergating_initialize(struct radeon_device *rdev)
150 u32 rcu_pwr_gating_cntl;
154 u32 xclk = radeon_get_xclk(rdev);
156 if (rdev->family == CHIP_PALM) {
161 p_p = 50 + 1000/200 + 6 * 32;
170 WREG32(CG_SCRATCH2, 0x01B60A17);
172 r600_calculate_u_and_p(SUMO_GFXPOWERGATINGT_DFLT,
175 WREG32_P(CG_PWR_GATING_CNTL, PGP(p) | PGU(u),
176 ~(PGP_MASK | PGU_MASK));
178 r600_calculate_u_and_p(SUMO_VOLTAGEDROPT_DFLT,
181 WREG32_P(CG_CG_VOLTAGE_CNTL, PGP(p) | PGU(u),
182 ~(PGP_MASK | PGU_MASK));
184 if (rdev->family == CHIP_PALM) {
185 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x10103210);
186 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0x10101010);
188 WREG32_RCU(RCU_PWR_GATING_SEQ0, 0x76543210);
189 WREG32_RCU(RCU_PWR_GATING_SEQ1, 0xFEDCBA98);
192 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
193 rcu_pwr_gating_cntl &=
194 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
195 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(1) | PWR_GATING_EN;
196 if (rdev->family == CHIP_PALM) {
197 rcu_pwr_gating_cntl &= ~PCP_MASK;
198 rcu_pwr_gating_cntl |= PCP(0x77);
200 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
202 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
203 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
204 rcu_pwr_gating_cntl |= MPPU(p_p) | MPPD(50);
205 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
207 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
208 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
209 rcu_pwr_gating_cntl |= DPPU(d_p) | DPPD(50);
210 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
212 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_4);
213 rcu_pwr_gating_cntl &= ~(RT_MASK | IT_MASK);
214 rcu_pwr_gating_cntl |= RT(r_t) | IT(i_t);
215 WREG32_RCU(RCU_PWR_GATING_CNTL_4, rcu_pwr_gating_cntl);
217 if (rdev->family == CHIP_PALM)
218 WREG32_RCU(RCU_PWR_GATING_CNTL_5, 0xA02);
220 sumo_smu_pg_init(rdev);
222 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
223 rcu_pwr_gating_cntl &=
224 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
225 rcu_pwr_gating_cntl |= PCV(p_c) | PGS(4) | PWR_GATING_EN;
226 if (rdev->family == CHIP_PALM) {
227 rcu_pwr_gating_cntl &= ~PCP_MASK;
228 rcu_pwr_gating_cntl |= PCP(0x77);
230 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
232 if (rdev->family == CHIP_PALM) {
233 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
234 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
235 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
236 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
238 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
239 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
240 rcu_pwr_gating_cntl |= DPPU(16) | DPPD(50);
241 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
244 sumo_smu_pg_init(rdev);
246 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL);
247 rcu_pwr_gating_cntl &=
248 ~(RSVD_MASK | PCV_MASK | PGS_MASK);
249 rcu_pwr_gating_cntl |= PGS(5) | PWR_GATING_EN;
251 if (rdev->family == CHIP_PALM) {
252 rcu_pwr_gating_cntl |= PCV(4);
253 rcu_pwr_gating_cntl &= ~PCP_MASK;
254 rcu_pwr_gating_cntl |= PCP(0x77);
256 rcu_pwr_gating_cntl |= PCV(11);
257 WREG32_RCU(RCU_PWR_GATING_CNTL, rcu_pwr_gating_cntl);
259 if (rdev->family == CHIP_PALM) {
260 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_2);
261 rcu_pwr_gating_cntl &= ~(MPPU_MASK | MPPD_MASK);
262 rcu_pwr_gating_cntl |= MPPU(113) | MPPD(50);
263 WREG32_RCU(RCU_PWR_GATING_CNTL_2, rcu_pwr_gating_cntl);
265 rcu_pwr_gating_cntl = RREG32_RCU(RCU_PWR_GATING_CNTL_3);
266 rcu_pwr_gating_cntl &= ~(DPPU_MASK | DPPD_MASK);
267 rcu_pwr_gating_cntl |= DPPU(22) | DPPD(50);
268 WREG32_RCU(RCU_PWR_GATING_CNTL_3, rcu_pwr_gating_cntl);
271 sumo_smu_pg_init(rdev);
274 static void sumo_gfx_powergating_enable(struct radeon_device *rdev, bool enable)
277 WREG32_P(CG_PWR_GATING_CNTL, DYN_PWR_DOWN_EN, ~DYN_PWR_DOWN_EN);
279 WREG32_P(CG_PWR_GATING_CNTL, 0, ~DYN_PWR_DOWN_EN);
280 RREG32(GB_ADDR_CONFIG);
284 static int sumo_enable_clock_power_gating(struct radeon_device *rdev)
286 struct sumo_power_info *pi = sumo_get_pi(rdev);
288 if (pi->enable_gfx_clock_gating)
289 sumo_gfx_clockgating_initialize(rdev);
290 if (pi->enable_gfx_power_gating)
291 sumo_gfx_powergating_initialize(rdev);
292 if (pi->enable_mg_clock_gating)
293 sumo_mg_clockgating_enable(rdev, true);
294 if (pi->enable_gfx_clock_gating)
295 sumo_gfx_clockgating_enable(rdev, true);
296 if (pi->enable_gfx_power_gating)
297 sumo_gfx_powergating_enable(rdev, true);
302 static void sumo_disable_clock_power_gating(struct radeon_device *rdev)
304 struct sumo_power_info *pi = sumo_get_pi(rdev);
306 if (pi->enable_gfx_clock_gating)
307 sumo_gfx_clockgating_enable(rdev, false);
308 if (pi->enable_gfx_power_gating)
309 sumo_gfx_powergating_enable(rdev, false);
310 if (pi->enable_mg_clock_gating)
311 sumo_mg_clockgating_enable(rdev, false);
314 static void sumo_calculate_bsp(struct radeon_device *rdev,
317 struct sumo_power_info *pi = sumo_get_pi(rdev);
318 u32 xclk = radeon_get_xclk(rdev);
320 pi->pasi = 65535 * 100 / high_clk;
321 pi->asi = 65535 * 100 / high_clk;
323 r600_calculate_u_and_p(pi->asi,
324 xclk, 16, &pi->bsp, &pi->bsu);
326 r600_calculate_u_and_p(pi->pasi,
327 xclk, 16, &pi->pbsp, &pi->pbsu);
329 pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
330 pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
333 static void sumo_init_bsp(struct radeon_device *rdev)
335 struct sumo_power_info *pi = sumo_get_pi(rdev);
337 WREG32(CG_BSP_0, pi->psp);
341 static void sumo_program_bsp(struct radeon_device *rdev,
342 struct radeon_ps *rps)
344 struct sumo_power_info *pi = sumo_get_pi(rdev);
345 struct sumo_ps *ps = sumo_get_ps(rps);
347 u32 highest_engine_clock = ps->levels[ps->num_levels - 1].sclk;
349 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
350 highest_engine_clock = pi->boost_pl.sclk;
352 sumo_calculate_bsp(rdev, highest_engine_clock);
354 for (i = 0; i < ps->num_levels - 1; i++)
355 WREG32(CG_BSP_0 + (i * 4), pi->dsp);
357 WREG32(CG_BSP_0 + (i * 4), pi->psp);
359 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
360 WREG32(CG_BSP_0 + (BOOST_DPM_LEVEL * 4), pi->psp);
363 static void sumo_write_at(struct radeon_device *rdev,
364 u32 index, u32 value)
367 WREG32(CG_AT_0, value);
369 WREG32(CG_AT_1, value);
371 WREG32(CG_AT_2, value);
373 WREG32(CG_AT_3, value);
375 WREG32(CG_AT_4, value);
377 WREG32(CG_AT_5, value);
379 WREG32(CG_AT_6, value);
381 WREG32(CG_AT_7, value);
384 static void sumo_program_at(struct radeon_device *rdev,
385 struct radeon_ps *rps)
387 struct sumo_power_info *pi = sumo_get_pi(rdev);
388 struct sumo_ps *ps = sumo_get_ps(rps);
393 u32 r[SUMO_MAX_HARDWARE_POWERLEVELS];
394 u32 l[SUMO_MAX_HARDWARE_POWERLEVELS];
408 for (i = 0; i < ps->num_levels; i++) {
409 asi = (i == ps->num_levels - 1) ? pi->pasi : pi->asi;
411 m_a = asi * ps->levels[i].sclk / 100;
413 a_t = CG_R(m_a * r[i] / 100) | CG_L(m_a * l[i] / 100);
415 sumo_write_at(rdev, i, a_t);
418 if (ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
421 m_a = asi * pi->boost_pl.sclk / 100;
423 a_t = CG_R(m_a * r[ps->num_levels - 1] / 100) |
424 CG_L(m_a * l[ps->num_levels - 1] / 100);
426 sumo_write_at(rdev, BOOST_DPM_LEVEL, a_t);
430 static void sumo_program_tp(struct radeon_device *rdev)
433 enum r600_td td = R600_TD_DFLT;
435 for (i = 0; i < SUMO_PM_NUMBER_OF_TC; i++) {
436 WREG32_P(CG_FFCT_0 + (i * 4), UTC_0(sumo_utc[i]), ~UTC_0_MASK);
437 WREG32_P(CG_FFCT_0 + (i * 4), DTC_0(sumo_dtc[i]), ~DTC_0_MASK);
440 if (td == R600_TD_AUTO)
441 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
443 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
445 if (td == R600_TD_UP)
446 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
448 if (td == R600_TD_DOWN)
449 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
452 void sumo_program_vc(struct radeon_device *rdev, u32 vrc)
457 void sumo_clear_vc(struct radeon_device *rdev)
462 void sumo_program_sstp(struct radeon_device *rdev)
465 u32 xclk = radeon_get_xclk(rdev);
467 r600_calculate_u_and_p(SUMO_SST_DFLT,
470 WREG32(CG_SSP, SSTU(u) | SST(p));
473 static void sumo_set_divider_value(struct radeon_device *rdev,
474 u32 index, u32 divider)
476 u32 reg_index = index / 4;
477 u32 field_index = index % 4;
479 if (field_index == 0)
480 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
481 SCLK_FSTATE_0_DIV(divider), ~SCLK_FSTATE_0_DIV_MASK);
482 else if (field_index == 1)
483 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
484 SCLK_FSTATE_1_DIV(divider), ~SCLK_FSTATE_1_DIV_MASK);
485 else if (field_index == 2)
486 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
487 SCLK_FSTATE_2_DIV(divider), ~SCLK_FSTATE_2_DIV_MASK);
488 else if (field_index == 3)
489 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
490 SCLK_FSTATE_3_DIV(divider), ~SCLK_FSTATE_3_DIV_MASK);
493 static void sumo_set_ds_dividers(struct radeon_device *rdev,
494 u32 index, u32 divider)
496 struct sumo_power_info *pi = sumo_get_pi(rdev);
498 if (pi->enable_sclk_ds) {
499 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_6);
501 dpm_ctrl &= ~(0x7 << (index * 3));
502 dpm_ctrl |= (divider << (index * 3));
503 WREG32(CG_SCLK_DPM_CTRL_6, dpm_ctrl);
507 static void sumo_set_ss_dividers(struct radeon_device *rdev,
508 u32 index, u32 divider)
510 struct sumo_power_info *pi = sumo_get_pi(rdev);
512 if (pi->enable_sclk_ds) {
513 u32 dpm_ctrl = RREG32(CG_SCLK_DPM_CTRL_11);
515 dpm_ctrl &= ~(0x7 << (index * 3));
516 dpm_ctrl |= (divider << (index * 3));
517 WREG32(CG_SCLK_DPM_CTRL_11, dpm_ctrl);
521 static void sumo_set_vid(struct radeon_device *rdev, u32 index, u32 vid)
523 u32 voltage_cntl = RREG32(CG_DPM_VOLTAGE_CNTL);
525 voltage_cntl &= ~(DPM_STATE0_LEVEL_MASK << (index * 2));
526 voltage_cntl |= (vid << (DPM_STATE0_LEVEL_SHIFT + index * 2));
527 WREG32(CG_DPM_VOLTAGE_CNTL, voltage_cntl);
530 static void sumo_set_allos_gnb_slow(struct radeon_device *rdev, u32 index, u32 gnb_slow)
532 struct sumo_power_info *pi = sumo_get_pi(rdev);
534 u32 cg_sclk_dpm_ctrl_3;
536 if (pi->driver_nbps_policy_disable)
539 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
540 cg_sclk_dpm_ctrl_3 &= ~(GNB_SLOW_FSTATE_0_MASK << index);
541 cg_sclk_dpm_ctrl_3 |= (temp << (GNB_SLOW_FSTATE_0_SHIFT + index));
543 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
546 static void sumo_program_power_level(struct radeon_device *rdev,
547 struct sumo_pl *pl, u32 index)
549 struct sumo_power_info *pi = sumo_get_pi(rdev);
551 struct atom_clock_dividers dividers;
552 u32 ds_en = RREG32(DEEP_SLEEP_CNTL) & ENABLE_DS;
554 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
555 pl->sclk, false, ÷rs);
559 sumo_set_divider_value(rdev, index, dividers.post_div);
561 sumo_set_vid(rdev, index, pl->vddc_index);
563 if (pl->ss_divider_index == 0 || pl->ds_divider_index == 0) {
565 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
567 sumo_set_ss_dividers(rdev, index, pl->ss_divider_index);
568 sumo_set_ds_dividers(rdev, index, pl->ds_divider_index);
571 WREG32_P(DEEP_SLEEP_CNTL, ENABLE_DS, ~ENABLE_DS);
574 sumo_set_allos_gnb_slow(rdev, index, pl->allow_gnb_slow);
576 if (pi->enable_boost)
577 sumo_set_tdp_limit(rdev, index, pl->sclk_dpm_tdp_limit);
580 static void sumo_power_level_enable(struct radeon_device *rdev, u32 index, bool enable)
582 u32 reg_index = index / 4;
583 u32 field_index = index % 4;
585 if (field_index == 0)
586 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
587 enable ? SCLK_FSTATE_0_VLD : 0, ~SCLK_FSTATE_0_VLD);
588 else if (field_index == 1)
589 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
590 enable ? SCLK_FSTATE_1_VLD : 0, ~SCLK_FSTATE_1_VLD);
591 else if (field_index == 2)
592 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
593 enable ? SCLK_FSTATE_2_VLD : 0, ~SCLK_FSTATE_2_VLD);
594 else if (field_index == 3)
595 WREG32_P(CG_SCLK_DPM_CTRL + (reg_index * 4),
596 enable ? SCLK_FSTATE_3_VLD : 0, ~SCLK_FSTATE_3_VLD);
599 static bool sumo_dpm_enabled(struct radeon_device *rdev)
601 if (RREG32(CG_SCLK_DPM_CTRL_3) & DPM_SCLK_ENABLE)
607 static void sumo_start_dpm(struct radeon_device *rdev)
609 WREG32_P(CG_SCLK_DPM_CTRL_3, DPM_SCLK_ENABLE, ~DPM_SCLK_ENABLE);
612 static void sumo_stop_dpm(struct radeon_device *rdev)
614 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~DPM_SCLK_ENABLE);
617 static void sumo_set_forced_mode(struct radeon_device *rdev, bool enable)
620 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE_EN, ~FORCE_SCLK_STATE_EN);
622 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_SCLK_STATE_EN);
625 static void sumo_set_forced_mode_enabled(struct radeon_device *rdev)
629 sumo_set_forced_mode(rdev, true);
630 for (i = 0; i < rdev->usec_timeout; i++) {
631 if (RREG32(CG_SCLK_STATUS) & SCLK_OVERCLK_DETECT)
637 static void sumo_wait_for_level_0(struct radeon_device *rdev)
641 for (i = 0; i < rdev->usec_timeout; i++) {
642 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_SCLK_INDEX_MASK) == 0)
646 for (i = 0; i < rdev->usec_timeout; i++) {
647 if ((RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) == 0)
653 static void sumo_set_forced_mode_disabled(struct radeon_device *rdev)
655 sumo_set_forced_mode(rdev, false);
658 static void sumo_enable_power_level_0(struct radeon_device *rdev)
660 sumo_power_level_enable(rdev, 0, true);
663 static void sumo_patch_boost_state(struct radeon_device *rdev,
664 struct radeon_ps *rps)
666 struct sumo_power_info *pi = sumo_get_pi(rdev);
667 struct sumo_ps *new_ps = sumo_get_ps(rps);
669 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE) {
670 pi->boost_pl = new_ps->levels[new_ps->num_levels - 1];
671 pi->boost_pl.sclk = pi->sys_info.boost_sclk;
672 pi->boost_pl.vddc_index = pi->sys_info.boost_vid_2bit;
673 pi->boost_pl.sclk_dpm_tdp_limit = pi->sys_info.sclk_dpm_tdp_limit_boost;
677 static void sumo_pre_notify_alt_vddnb_change(struct radeon_device *rdev,
678 struct radeon_ps *new_rps,
679 struct radeon_ps *old_rps)
681 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
682 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
687 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
689 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE) ? 1 : 0;
691 if (nbps1_old == 1 && nbps1_new == 0)
692 sumo_smu_notify_alt_vddnb_change(rdev, 0, 0);
695 static void sumo_post_notify_alt_vddnb_change(struct radeon_device *rdev,
696 struct radeon_ps *new_rps,
697 struct radeon_ps *old_rps)
699 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
700 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
705 nbps1_old = (old_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
707 nbps1_new = (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)? 1 : 0;
709 if (nbps1_old == 0 && nbps1_new == 1)
710 sumo_smu_notify_alt_vddnb_change(rdev, 1, 1);
713 static void sumo_enable_boost(struct radeon_device *rdev,
714 struct radeon_ps *rps,
717 struct sumo_ps *new_ps = sumo_get_ps(rps);
720 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
721 sumo_boost_state_enable(rdev, true);
723 sumo_boost_state_enable(rdev, false);
726 static void sumo_set_forced_level(struct radeon_device *rdev, u32 index)
728 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_SCLK_STATE(index), ~FORCE_SCLK_STATE_MASK);
731 static void sumo_set_forced_level_0(struct radeon_device *rdev)
733 sumo_set_forced_level(rdev, 0);
736 static void sumo_program_wl(struct radeon_device *rdev,
737 struct radeon_ps *rps)
739 struct sumo_ps *new_ps = sumo_get_ps(rps);
740 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
742 dpm_ctrl4 &= 0xFFFFFF00;
743 dpm_ctrl4 |= (1 << (new_ps->num_levels - 1));
745 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
746 dpm_ctrl4 |= (1 << BOOST_DPM_LEVEL);
748 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
751 static void sumo_program_power_levels_0_to_n(struct radeon_device *rdev,
752 struct radeon_ps *new_rps,
753 struct radeon_ps *old_rps)
755 struct sumo_power_info *pi = sumo_get_pi(rdev);
756 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
757 struct sumo_ps *old_ps = sumo_get_ps(old_rps);
759 u32 n_current_state_levels = (old_ps == NULL) ? 1 : old_ps->num_levels;
761 for (i = 0; i < new_ps->num_levels; i++) {
762 sumo_program_power_level(rdev, &new_ps->levels[i], i);
763 sumo_power_level_enable(rdev, i, true);
766 for (i = new_ps->num_levels; i < n_current_state_levels; i++)
767 sumo_power_level_enable(rdev, i, false);
769 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_BOOST_STATE)
770 sumo_program_power_level(rdev, &pi->boost_pl, BOOST_DPM_LEVEL);
773 static void sumo_enable_acpi_pm(struct radeon_device *rdev)
775 WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
778 static void sumo_program_power_level_enter_state(struct radeon_device *rdev)
780 WREG32_P(CG_SCLK_DPM_CTRL_5, SCLK_FSTATE_BOOTUP(0), ~SCLK_FSTATE_BOOTUP_MASK);
783 static void sumo_program_acpi_power_level(struct radeon_device *rdev)
785 struct sumo_power_info *pi = sumo_get_pi(rdev);
786 struct atom_clock_dividers dividers;
789 ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
795 WREG32_P(CG_ACPI_CNTL, SCLK_ACPI_DIV(dividers.post_div), ~SCLK_ACPI_DIV_MASK);
796 WREG32_P(CG_ACPI_VOLTAGE_CNTL, 0, ~ACPI_VOLTAGE_EN);
799 static void sumo_program_bootup_state(struct radeon_device *rdev)
801 struct sumo_power_info *pi = sumo_get_pi(rdev);
802 u32 dpm_ctrl4 = RREG32(CG_SCLK_DPM_CTRL_4);
805 sumo_program_power_level(rdev, &pi->boot_pl, 0);
807 dpm_ctrl4 &= 0xFFFFFF00;
808 WREG32(CG_SCLK_DPM_CTRL_4, dpm_ctrl4);
810 for (i = 1; i < 8; i++)
811 sumo_power_level_enable(rdev, i, false);
814 static void sumo_setup_uvd_clocks(struct radeon_device *rdev,
815 struct radeon_ps *new_rps,
816 struct radeon_ps *old_rps)
818 struct sumo_power_info *pi = sumo_get_pi(rdev);
820 if (pi->enable_gfx_power_gating) {
821 sumo_gfx_powergating_enable(rdev, false);
824 radeon_set_uvd_clocks(rdev, new_rps->vclk, new_rps->dclk);
826 if (pi->enable_gfx_power_gating) {
827 sumo_gfx_powergating_enable(rdev, true);
831 static void sumo_set_uvd_clock_before_set_eng_clock(struct radeon_device *rdev,
832 struct radeon_ps *new_rps,
833 struct radeon_ps *old_rps)
835 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
836 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
838 if ((new_rps->vclk == old_rps->vclk) &&
839 (new_rps->dclk == old_rps->dclk))
842 if (new_ps->levels[new_ps->num_levels - 1].sclk >=
843 current_ps->levels[current_ps->num_levels - 1].sclk)
846 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
849 static void sumo_set_uvd_clock_after_set_eng_clock(struct radeon_device *rdev,
850 struct radeon_ps *new_rps,
851 struct radeon_ps *old_rps)
853 struct sumo_ps *new_ps = sumo_get_ps(new_rps);
854 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
856 if ((new_rps->vclk == old_rps->vclk) &&
857 (new_rps->dclk == old_rps->dclk))
860 if (new_ps->levels[new_ps->num_levels - 1].sclk <
861 current_ps->levels[current_ps->num_levels - 1].sclk)
864 sumo_setup_uvd_clocks(rdev, new_rps, old_rps);
867 void sumo_take_smu_control(struct radeon_device *rdev, bool enable)
869 /* This bit selects who handles display phy powergating.
870 * Clear the bit to let atom handle it.
871 * Set it to let the driver handle it.
872 * For now we just let atom handle it.
875 u32 v = RREG32(DOUT_SCRATCH3);
882 WREG32(DOUT_SCRATCH3, v);
886 static void sumo_enable_sclk_ds(struct radeon_device *rdev, bool enable)
889 u32 deep_sleep_cntl = RREG32(DEEP_SLEEP_CNTL);
890 u32 deep_sleep_cntl2 = RREG32(DEEP_SLEEP_CNTL2);
893 deep_sleep_cntl &= ~R_DIS;
894 deep_sleep_cntl &= ~HS_MASK;
895 deep_sleep_cntl |= HS(t > 4095 ? 4095 : t);
897 deep_sleep_cntl2 |= LB_UFP_EN;
898 deep_sleep_cntl2 &= INOUT_C_MASK;
899 deep_sleep_cntl2 |= INOUT_C(0xf);
901 WREG32(DEEP_SLEEP_CNTL2, deep_sleep_cntl2);
902 WREG32(DEEP_SLEEP_CNTL, deep_sleep_cntl);
904 WREG32_P(DEEP_SLEEP_CNTL, 0, ~ENABLE_DS);
907 static void sumo_program_bootup_at(struct radeon_device *rdev)
909 WREG32_P(CG_AT_0, CG_R(0xffff), ~CG_R_MASK);
910 WREG32_P(CG_AT_0, CG_L(0), ~CG_L_MASK);
913 static void sumo_reset_am(struct radeon_device *rdev)
915 WREG32_P(SCLK_PWRMGT_CNTL, FIR_RESET, ~FIR_RESET);
918 static void sumo_start_am(struct radeon_device *rdev)
920 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_RESET);
923 static void sumo_program_ttp(struct radeon_device *rdev)
925 u32 xclk = radeon_get_xclk(rdev);
927 u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5);
929 r600_calculate_u_and_p(1000,
932 cg_sclk_dpm_ctrl_5 &= ~(TT_TP_MASK | TT_TU_MASK);
933 cg_sclk_dpm_ctrl_5 |= TT_TP(p) | TT_TU(u);
935 WREG32(CG_SCLK_DPM_CTRL_5, cg_sclk_dpm_ctrl_5);
938 static void sumo_program_ttt(struct radeon_device *rdev)
940 u32 cg_sclk_dpm_ctrl_3 = RREG32(CG_SCLK_DPM_CTRL_3);
941 struct sumo_power_info *pi = sumo_get_pi(rdev);
943 cg_sclk_dpm_ctrl_3 &= ~(GNB_TT_MASK | GNB_THERMTHRO_MASK);
944 cg_sclk_dpm_ctrl_3 |= GNB_TT(pi->thermal_auto_throttling + 49);
946 WREG32(CG_SCLK_DPM_CTRL_3, cg_sclk_dpm_ctrl_3);
950 static void sumo_enable_voltage_scaling(struct radeon_device *rdev, bool enable)
953 WREG32_P(CG_DPM_VOLTAGE_CNTL, DPM_VOLTAGE_EN, ~DPM_VOLTAGE_EN);
954 WREG32_P(CG_CG_VOLTAGE_CNTL, 0, ~CG_VOLTAGE_EN);
956 WREG32_P(CG_CG_VOLTAGE_CNTL, CG_VOLTAGE_EN, ~CG_VOLTAGE_EN);
957 WREG32_P(CG_DPM_VOLTAGE_CNTL, 0, ~DPM_VOLTAGE_EN);
961 static void sumo_override_cnb_thermal_events(struct radeon_device *rdev)
963 WREG32_P(CG_SCLK_DPM_CTRL_3, CNB_THERMTHRO_MASK_SCLK,
964 ~CNB_THERMTHRO_MASK_SCLK);
967 static void sumo_program_dc_hto(struct radeon_device *rdev)
969 u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4);
971 u32 xclk = radeon_get_xclk(rdev);
973 r600_calculate_u_and_p(100000,
976 cg_sclk_dpm_ctrl_4 &= ~(DC_HDC_MASK | DC_HU_MASK);
977 cg_sclk_dpm_ctrl_4 |= DC_HDC(p) | DC_HU(u);
979 WREG32(CG_SCLK_DPM_CTRL_4, cg_sclk_dpm_ctrl_4);
982 static void sumo_force_nbp_state(struct radeon_device *rdev,
983 struct radeon_ps *rps)
985 struct sumo_power_info *pi = sumo_get_pi(rdev);
986 struct sumo_ps *new_ps = sumo_get_ps(rps);
988 if (!pi->driver_nbps_policy_disable) {
989 if (new_ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
990 WREG32_P(CG_SCLK_DPM_CTRL_3, FORCE_NB_PSTATE_1, ~FORCE_NB_PSTATE_1);
992 WREG32_P(CG_SCLK_DPM_CTRL_3, 0, ~FORCE_NB_PSTATE_1);
996 u32 sumo_get_sleep_divider_from_id(u32 id)
1001 u32 sumo_get_sleep_divider_id_from_clock(struct radeon_device *rdev,
1005 struct sumo_power_info *pi = sumo_get_pi(rdev);
1008 u32 min = (min_sclk_in_sr > SUMO_MINIMUM_ENGINE_CLOCK) ?
1009 min_sclk_in_sr : SUMO_MINIMUM_ENGINE_CLOCK;
1014 if (!pi->enable_sclk_ds)
1017 for (i = SUMO_MAX_DEEPSLEEP_DIVIDER_ID; ; i--) {
1018 temp = sclk / sumo_get_sleep_divider_from_id(i);
1020 if (temp >= min || i == 0)
1026 static u32 sumo_get_valid_engine_clock(struct radeon_device *rdev,
1029 struct sumo_power_info *pi = sumo_get_pi(rdev);
1032 for (i = 0; i < pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries; i++) {
1033 if (pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency >= lower_limit)
1034 return pi->sys_info.sclk_voltage_mapping_table.entries[i].sclk_frequency;
1037 return pi->sys_info.sclk_voltage_mapping_table.entries[pi->sys_info.sclk_voltage_mapping_table.num_max_dpm_entries - 1].sclk_frequency;
1040 static void sumo_patch_thermal_state(struct radeon_device *rdev,
1042 struct sumo_ps *current_ps)
1044 struct sumo_power_info *pi = sumo_get_pi(rdev);
1045 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1048 u32 current_index = 0;
1051 current_vddc = current_ps->levels[current_index].vddc_index;
1052 current_sclk = current_ps->levels[current_index].sclk;
1054 current_vddc = pi->boot_pl.vddc_index;
1055 current_sclk = pi->boot_pl.sclk;
1058 ps->levels[0].vddc_index = current_vddc;
1060 if (ps->levels[0].sclk > current_sclk)
1061 ps->levels[0].sclk = current_sclk;
1063 ps->levels[0].ss_divider_index =
1064 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, sclk_in_sr);
1066 ps->levels[0].ds_divider_index =
1067 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[0].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1069 if (ps->levels[0].ds_divider_index > ps->levels[0].ss_divider_index + 1)
1070 ps->levels[0].ds_divider_index = ps->levels[0].ss_divider_index + 1;
1072 if (ps->levels[0].ss_divider_index == ps->levels[0].ds_divider_index) {
1073 if (ps->levels[0].ss_divider_index > 1)
1074 ps->levels[0].ss_divider_index = ps->levels[0].ss_divider_index - 1;
1077 if (ps->levels[0].ss_divider_index == 0)
1078 ps->levels[0].ds_divider_index = 0;
1080 if (ps->levels[0].ds_divider_index == 0)
1081 ps->levels[0].ss_divider_index = 0;
1084 static void sumo_apply_state_adjust_rules(struct radeon_device *rdev,
1085 struct radeon_ps *new_rps,
1086 struct radeon_ps *old_rps)
1088 struct sumo_ps *ps = sumo_get_ps(new_rps);
1089 struct sumo_ps *current_ps = sumo_get_ps(old_rps);
1090 struct sumo_power_info *pi = sumo_get_pi(rdev);
1091 u32 min_voltage = 0; /* ??? */
1092 u32 min_sclk = pi->sys_info.min_sclk; /* XXX check against disp reqs */
1093 u32 sclk_in_sr = pi->sys_info.min_sclk; /* ??? */
1096 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_THERMAL)
1097 return sumo_patch_thermal_state(rdev, ps, current_ps);
1099 if (pi->enable_boost) {
1100 if (new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE)
1101 ps->flags |= SUMO_POWERSTATE_FLAGS_BOOST_STATE;
1104 if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UI_BATTERY) ||
1105 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_SDSTATE) ||
1106 (new_rps->class & ATOM_PPLIB_CLASSIFICATION_HDSTATE))
1107 ps->flags |= SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE;
1109 for (i = 0; i < ps->num_levels; i++) {
1110 if (ps->levels[i].vddc_index < min_voltage)
1111 ps->levels[i].vddc_index = min_voltage;
1113 if (ps->levels[i].sclk < min_sclk)
1114 ps->levels[i].sclk =
1115 sumo_get_valid_engine_clock(rdev, min_sclk);
1117 ps->levels[i].ss_divider_index =
1118 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, sclk_in_sr);
1120 ps->levels[i].ds_divider_index =
1121 sumo_get_sleep_divider_id_from_clock(rdev, ps->levels[i].sclk, SUMO_MINIMUM_ENGINE_CLOCK);
1123 if (ps->levels[i].ds_divider_index > ps->levels[i].ss_divider_index + 1)
1124 ps->levels[i].ds_divider_index = ps->levels[i].ss_divider_index + 1;
1126 if (ps->levels[i].ss_divider_index == ps->levels[i].ds_divider_index) {
1127 if (ps->levels[i].ss_divider_index > 1)
1128 ps->levels[i].ss_divider_index = ps->levels[i].ss_divider_index - 1;
1131 if (ps->levels[i].ss_divider_index == 0)
1132 ps->levels[i].ds_divider_index = 0;
1134 if (ps->levels[i].ds_divider_index == 0)
1135 ps->levels[i].ss_divider_index = 0;
1137 if (ps->flags & SUMO_POWERSTATE_FLAGS_FORCE_NBPS1_STATE)
1138 ps->levels[i].allow_gnb_slow = 1;
1139 else if ((new_rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE) ||
1140 (new_rps->class2 & ATOM_PPLIB_CLASSIFICATION2_MVC))
1141 ps->levels[i].allow_gnb_slow = 0;
1142 else if (i == ps->num_levels - 1)
1143 ps->levels[i].allow_gnb_slow = 0;
1145 ps->levels[i].allow_gnb_slow = 1;
1149 static void sumo_cleanup_asic(struct radeon_device *rdev)
1151 sumo_take_smu_control(rdev, false);
1154 static int sumo_set_thermal_temperature_range(struct radeon_device *rdev,
1155 int min_temp, int max_temp)
1157 int low_temp = 0 * 1000;
1158 int high_temp = 255 * 1000;
1160 if (low_temp < min_temp)
1161 low_temp = min_temp;
1162 if (high_temp > max_temp)
1163 high_temp = max_temp;
1164 if (high_temp < low_temp) {
1165 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
1169 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(49 + (high_temp / 1000)), ~DIG_THERM_INTH_MASK);
1170 WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(49 + (low_temp / 1000)), ~DIG_THERM_INTL_MASK);
1172 rdev->pm.dpm.thermal.min_temp = low_temp;
1173 rdev->pm.dpm.thermal.max_temp = high_temp;
1178 static void sumo_update_current_ps(struct radeon_device *rdev,
1179 struct radeon_ps *rps)
1181 struct sumo_ps *new_ps = sumo_get_ps(rps);
1182 struct sumo_power_info *pi = sumo_get_pi(rdev);
1184 pi->current_rps = *rps;
1185 pi->current_ps = *new_ps;
1186 pi->current_rps.ps_priv = &pi->current_ps;
1189 static void sumo_update_requested_ps(struct radeon_device *rdev,
1190 struct radeon_ps *rps)
1192 struct sumo_ps *new_ps = sumo_get_ps(rps);
1193 struct sumo_power_info *pi = sumo_get_pi(rdev);
1195 pi->requested_rps = *rps;
1196 pi->requested_ps = *new_ps;
1197 pi->requested_rps.ps_priv = &pi->requested_ps;
1200 int sumo_dpm_enable(struct radeon_device *rdev)
1202 struct sumo_power_info *pi = sumo_get_pi(rdev);
1205 if (sumo_dpm_enabled(rdev))
1208 ret = sumo_enable_clock_power_gating(rdev);
1211 sumo_program_bootup_state(rdev);
1212 sumo_init_bsp(rdev);
1213 sumo_reset_am(rdev);
1214 sumo_program_tp(rdev);
1215 sumo_program_bootup_at(rdev);
1216 sumo_start_am(rdev);
1217 if (pi->enable_auto_thermal_throttling) {
1218 sumo_program_ttp(rdev);
1219 sumo_program_ttt(rdev);
1221 sumo_program_dc_hto(rdev);
1222 sumo_program_power_level_enter_state(rdev);
1223 sumo_enable_voltage_scaling(rdev, true);
1224 sumo_program_sstp(rdev);
1225 sumo_program_vc(rdev, SUMO_VRC_DFLT);
1226 sumo_override_cnb_thermal_events(rdev);
1227 sumo_start_dpm(rdev);
1228 sumo_wait_for_level_0(rdev);
1229 if (pi->enable_sclk_ds)
1230 sumo_enable_sclk_ds(rdev, true);
1231 if (pi->enable_boost)
1232 sumo_enable_boost_timer(rdev);
1234 if (rdev->irq.installed &&
1235 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1236 ret = sumo_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
1239 rdev->irq.dpm_thermal = true;
1240 radeon_irq_set(rdev);
1243 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1248 void sumo_dpm_disable(struct radeon_device *rdev)
1250 struct sumo_power_info *pi = sumo_get_pi(rdev);
1252 if (!sumo_dpm_enabled(rdev))
1254 sumo_disable_clock_power_gating(rdev);
1255 if (pi->enable_sclk_ds)
1256 sumo_enable_sclk_ds(rdev, false);
1257 sumo_clear_vc(rdev);
1258 sumo_wait_for_level_0(rdev);
1259 sumo_stop_dpm(rdev);
1260 sumo_enable_voltage_scaling(rdev, false);
1262 if (rdev->irq.installed &&
1263 r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
1264 rdev->irq.dpm_thermal = false;
1265 radeon_irq_set(rdev);
1268 sumo_update_current_ps(rdev, rdev->pm.dpm.boot_ps);
1271 int sumo_dpm_pre_set_power_state(struct radeon_device *rdev)
1273 struct sumo_power_info *pi = sumo_get_pi(rdev);
1274 struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
1275 struct radeon_ps *new_ps = &requested_ps;
1277 sumo_update_requested_ps(rdev, new_ps);
1279 if (pi->enable_dynamic_patch_ps)
1280 sumo_apply_state_adjust_rules(rdev,
1287 int sumo_dpm_set_power_state(struct radeon_device *rdev)
1289 struct sumo_power_info *pi = sumo_get_pi(rdev);
1290 struct radeon_ps *new_ps = &pi->requested_rps;
1291 struct radeon_ps *old_ps = &pi->current_rps;
1294 sumo_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
1295 if (pi->enable_boost) {
1296 sumo_enable_boost(rdev, new_ps, false);
1297 sumo_patch_boost_state(rdev, new_ps);
1299 if (pi->enable_dpm) {
1300 sumo_pre_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1301 sumo_enable_power_level_0(rdev);
1302 sumo_set_forced_level_0(rdev);
1303 sumo_set_forced_mode_enabled(rdev);
1304 sumo_wait_for_level_0(rdev);
1305 sumo_program_power_levels_0_to_n(rdev, new_ps, old_ps);
1306 sumo_program_wl(rdev, new_ps);
1307 sumo_program_bsp(rdev, new_ps);
1308 sumo_program_at(rdev, new_ps);
1309 sumo_force_nbp_state(rdev, new_ps);
1310 sumo_set_forced_mode_disabled(rdev);
1311 sumo_set_forced_mode_enabled(rdev);
1312 sumo_set_forced_mode_disabled(rdev);
1313 sumo_post_notify_alt_vddnb_change(rdev, new_ps, old_ps);
1315 if (pi->enable_boost)
1316 sumo_enable_boost(rdev, new_ps, true);
1318 sumo_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
1323 void sumo_dpm_post_set_power_state(struct radeon_device *rdev)
1325 struct sumo_power_info *pi = sumo_get_pi(rdev);
1326 struct radeon_ps *new_ps = &pi->requested_rps;
1328 sumo_update_current_ps(rdev, new_ps);
1331 void sumo_dpm_reset_asic(struct radeon_device *rdev)
1333 sumo_program_bootup_state(rdev);
1334 sumo_enable_power_level_0(rdev);
1335 sumo_set_forced_level_0(rdev);
1336 sumo_set_forced_mode_enabled(rdev);
1337 sumo_wait_for_level_0(rdev);
1338 sumo_set_forced_mode_disabled(rdev);
1339 sumo_set_forced_mode_enabled(rdev);
1340 sumo_set_forced_mode_disabled(rdev);
1343 void sumo_dpm_setup_asic(struct radeon_device *rdev)
1345 struct sumo_power_info *pi = sumo_get_pi(rdev);
1347 sumo_initialize_m3_arb(rdev);
1348 pi->fw_version = sumo_get_running_fw_version(rdev);
1349 DRM_INFO("Found smc ucode version: 0x%08x\n", pi->fw_version);
1350 sumo_program_acpi_power_level(rdev);
1351 sumo_enable_acpi_pm(rdev);
1352 sumo_take_smu_control(rdev, true);
1355 void sumo_dpm_display_configuration_changed(struct radeon_device *rdev)
1361 struct _ATOM_POWERPLAY_INFO info;
1362 struct _ATOM_POWERPLAY_INFO_V2 info_2;
1363 struct _ATOM_POWERPLAY_INFO_V3 info_3;
1364 struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
1365 struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
1366 struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
1369 union pplib_clock_info {
1370 struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
1371 struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
1372 struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
1373 struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
1376 union pplib_power_state {
1377 struct _ATOM_PPLIB_STATE v1;
1378 struct _ATOM_PPLIB_STATE_V2 v2;
1381 static void sumo_patch_boot_state(struct radeon_device *rdev,
1384 struct sumo_power_info *pi = sumo_get_pi(rdev);
1388 ps->levels[0] = pi->boot_pl;
1391 static void sumo_parse_pplib_non_clock_info(struct radeon_device *rdev,
1392 struct radeon_ps *rps,
1393 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
1396 struct sumo_ps *ps = sumo_get_ps(rps);
1398 rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
1399 rps->class = le16_to_cpu(non_clock_info->usClassification);
1400 rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
1402 if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
1403 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
1404 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
1410 if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
1411 rdev->pm.dpm.boot_ps = rps;
1412 sumo_patch_boot_state(rdev, ps);
1414 if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
1415 rdev->pm.dpm.uvd_ps = rps;
1418 static void sumo_parse_pplib_clock_info(struct radeon_device *rdev,
1419 struct radeon_ps *rps, int index,
1420 union pplib_clock_info *clock_info)
1422 struct sumo_power_info *pi = sumo_get_pi(rdev);
1423 struct sumo_ps *ps = sumo_get_ps(rps);
1424 struct sumo_pl *pl = &ps->levels[index];
1427 sclk = le16_to_cpu(clock_info->sumo.usEngineClockLow);
1428 sclk |= clock_info->sumo.ucEngineClockHigh << 16;
1430 pl->vddc_index = clock_info->sumo.vddcIndex;
1431 pl->sclk_dpm_tdp_limit = clock_info->sumo.tdpLimit;
1433 ps->num_levels = index + 1;
1435 if (pi->enable_sclk_ds) {
1436 pl->ds_divider_index = 5;
1437 pl->ss_divider_index = 4;
1441 static int sumo_parse_power_table(struct radeon_device *rdev)
1443 struct radeon_mode_info *mode_info = &rdev->mode_info;
1444 struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
1445 union pplib_power_state *power_state;
1446 int i, j, k, non_clock_array_index, clock_array_index;
1447 union pplib_clock_info *clock_info;
1448 struct _StateArray *state_array;
1449 struct _ClockInfoArray *clock_info_array;
1450 struct _NonClockInfoArray *non_clock_info_array;
1451 union power_info *power_info;
1452 int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
1455 u8 *power_state_offset;
1458 if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
1459 &frev, &crev, &data_offset))
1461 power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
1463 state_array = (struct _StateArray *)
1464 (mode_info->atom_context->bios + data_offset +
1465 le16_to_cpu(power_info->pplib.usStateArrayOffset));
1466 clock_info_array = (struct _ClockInfoArray *)
1467 (mode_info->atom_context->bios + data_offset +
1468 le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
1469 non_clock_info_array = (struct _NonClockInfoArray *)
1470 (mode_info->atom_context->bios + data_offset +
1471 le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
1473 rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
1474 state_array->ucNumEntries, GFP_KERNEL);
1475 if (!rdev->pm.dpm.ps)
1477 power_state_offset = (u8 *)state_array->states;
1478 rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
1479 rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
1480 rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
1481 for (i = 0; i < state_array->ucNumEntries; i++) {
1482 power_state = (union pplib_power_state *)power_state_offset;
1483 non_clock_array_index = power_state->v2.nonClockInfoIndex;
1484 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
1485 &non_clock_info_array->nonClockInfo[non_clock_array_index];
1486 if (!rdev->pm.power_state[i].clock_info)
1488 ps = kzalloc(sizeof(struct sumo_ps), GFP_KERNEL);
1490 kfree(rdev->pm.dpm.ps);
1493 rdev->pm.dpm.ps[i].ps_priv = ps;
1495 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
1496 clock_array_index = power_state->v2.clockInfoIndex[j];
1497 if (k >= SUMO_MAX_HARDWARE_POWERLEVELS)
1499 clock_info = (union pplib_clock_info *)
1500 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
1501 sumo_parse_pplib_clock_info(rdev,
1502 &rdev->pm.dpm.ps[i], k,
1506 sumo_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
1508 non_clock_info_array->ucEntrySize);
1509 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
1511 rdev->pm.dpm.num_ps = state_array->ucNumEntries;
1515 u32 sumo_convert_vid2_to_vid7(struct radeon_device *rdev,
1516 struct sumo_vid_mapping_table *vid_mapping_table,
1521 for (i = 0; i < vid_mapping_table->num_entries; i++) {
1522 if (vid_mapping_table->entries[i].vid_2bit == vid_2bit)
1523 return vid_mapping_table->entries[i].vid_7bit;
1526 return vid_mapping_table->entries[vid_mapping_table->num_entries - 1].vid_7bit;
1529 static u16 sumo_convert_voltage_index_to_value(struct radeon_device *rdev,
1532 struct sumo_power_info *pi = sumo_get_pi(rdev);
1533 u32 vid_7bit = sumo_convert_vid2_to_vid7(rdev, &pi->sys_info.vid_mapping_table, vid_2bit);
1535 if (vid_7bit > 0x7C)
1538 return (15500 - vid_7bit * 125 + 5) / 10;
1541 static void sumo_construct_display_voltage_mapping_table(struct radeon_device *rdev,
1542 struct sumo_disp_clock_voltage_mapping_table *disp_clk_voltage_mapping_table,
1543 ATOM_CLK_VOLT_CAPABILITY *table)
1547 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1548 if (table[i].ulMaximumSupportedCLK == 0)
1551 disp_clk_voltage_mapping_table->display_clock_frequency[i] =
1552 table[i].ulMaximumSupportedCLK;
1555 disp_clk_voltage_mapping_table->num_max_voltage_levels = i;
1557 if (disp_clk_voltage_mapping_table->num_max_voltage_levels == 0) {
1558 disp_clk_voltage_mapping_table->display_clock_frequency[0] = 80000;
1559 disp_clk_voltage_mapping_table->num_max_voltage_levels = 1;
1563 void sumo_construct_sclk_voltage_mapping_table(struct radeon_device *rdev,
1564 struct sumo_sclk_voltage_mapping_table *sclk_voltage_mapping_table,
1565 ATOM_AVAILABLE_SCLK_LIST *table)
1571 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1572 if (table[i].ulSupportedSCLK > prev_sclk) {
1573 sclk_voltage_mapping_table->entries[n].sclk_frequency =
1574 table[i].ulSupportedSCLK;
1575 sclk_voltage_mapping_table->entries[n].vid_2bit =
1576 table[i].usVoltageIndex;
1577 prev_sclk = table[i].ulSupportedSCLK;
1582 sclk_voltage_mapping_table->num_max_dpm_entries = n;
1585 void sumo_construct_vid_mapping_table(struct radeon_device *rdev,
1586 struct sumo_vid_mapping_table *vid_mapping_table,
1587 ATOM_AVAILABLE_SCLK_LIST *table)
1591 for (i = 0; i < SUMO_MAX_HARDWARE_POWERLEVELS; i++) {
1592 if (table[i].ulSupportedSCLK != 0) {
1593 vid_mapping_table->entries[table[i].usVoltageIndex].vid_7bit =
1594 table[i].usVoltageID;
1595 vid_mapping_table->entries[table[i].usVoltageIndex].vid_2bit =
1596 table[i].usVoltageIndex;
1600 for (i = 0; i < SUMO_MAX_NUMBER_VOLTAGES; i++) {
1601 if (vid_mapping_table->entries[i].vid_7bit == 0) {
1602 for (j = i + 1; j < SUMO_MAX_NUMBER_VOLTAGES; j++) {
1603 if (vid_mapping_table->entries[j].vid_7bit != 0) {
1604 vid_mapping_table->entries[i] =
1605 vid_mapping_table->entries[j];
1606 vid_mapping_table->entries[j].vid_7bit = 0;
1611 if (j == SUMO_MAX_NUMBER_VOLTAGES)
1616 vid_mapping_table->num_entries = i;
1620 struct _ATOM_INTEGRATED_SYSTEM_INFO info;
1621 struct _ATOM_INTEGRATED_SYSTEM_INFO_V2 info_2;
1622 struct _ATOM_INTEGRATED_SYSTEM_INFO_V5 info_5;
1623 struct _ATOM_INTEGRATED_SYSTEM_INFO_V6 info_6;
1626 static int sumo_parse_sys_info_table(struct radeon_device *rdev)
1628 struct sumo_power_info *pi = sumo_get_pi(rdev);
1629 struct radeon_mode_info *mode_info = &rdev->mode_info;
1630 int index = GetIndexIntoMasterTable(DATA, IntegratedSystemInfo);
1631 union igp_info *igp_info;
1636 if (atom_parse_data_header(mode_info->atom_context, index, NULL,
1637 &frev, &crev, &data_offset)) {
1638 igp_info = (union igp_info *)(mode_info->atom_context->bios +
1642 DRM_ERROR("Unsupported IGP table: %d %d\n", frev, crev);
1645 pi->sys_info.bootup_sclk = le32_to_cpu(igp_info->info_6.ulBootUpEngineClock);
1646 pi->sys_info.min_sclk = le32_to_cpu(igp_info->info_6.ulMinEngineClock);
1647 pi->sys_info.bootup_uma_clk = le32_to_cpu(igp_info->info_6.ulBootUpUMAClock);
1648 pi->sys_info.bootup_nb_voltage_index =
1649 le16_to_cpu(igp_info->info_6.usBootUpNBVoltage);
1650 if (igp_info->info_6.ucHtcTmpLmt == 0)
1651 pi->sys_info.htc_tmp_lmt = 203;
1653 pi->sys_info.htc_tmp_lmt = igp_info->info_6.ucHtcTmpLmt;
1654 if (igp_info->info_6.ucHtcHystLmt == 0)
1655 pi->sys_info.htc_hyst_lmt = 5;
1657 pi->sys_info.htc_hyst_lmt = igp_info->info_6.ucHtcHystLmt;
1658 if (pi->sys_info.htc_tmp_lmt <= pi->sys_info.htc_hyst_lmt) {
1659 DRM_ERROR("The htcTmpLmt should be larger than htcHystLmt.\n");
1661 for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++) {
1662 pi->sys_info.csr_m3_arb_cntl_default[i] =
1663 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_DEFAULT[i]);
1664 pi->sys_info.csr_m3_arb_cntl_uvd[i] =
1665 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_UVD[i]);
1666 pi->sys_info.csr_m3_arb_cntl_fs3d[i] =
1667 le32_to_cpu(igp_info->info_6.ulCSR_M3_ARB_CNTL_FS3D[i]);
1669 pi->sys_info.sclk_dpm_boost_margin =
1670 le32_to_cpu(igp_info->info_6.SclkDpmBoostMargin);
1671 pi->sys_info.sclk_dpm_throttle_margin =
1672 le32_to_cpu(igp_info->info_6.SclkDpmThrottleMargin);
1673 pi->sys_info.sclk_dpm_tdp_limit_pg =
1674 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitPG);
1675 pi->sys_info.gnb_tdp_limit = le16_to_cpu(igp_info->info_6.GnbTdpLimit);
1676 pi->sys_info.sclk_dpm_tdp_limit_boost =
1677 le16_to_cpu(igp_info->info_6.SclkDpmTdpLimitBoost);
1678 pi->sys_info.boost_sclk = le32_to_cpu(igp_info->info_6.ulBoostEngineCLock);
1679 pi->sys_info.boost_vid_2bit = igp_info->info_6.ulBoostVid_2bit;
1680 if (igp_info->info_6.EnableBoost)
1681 pi->sys_info.enable_boost = true;
1683 pi->sys_info.enable_boost = false;
1684 sumo_construct_display_voltage_mapping_table(rdev,
1685 &pi->sys_info.disp_clk_voltage_mapping_table,
1686 igp_info->info_6.sDISPCLK_Voltage);
1687 sumo_construct_sclk_voltage_mapping_table(rdev,
1688 &pi->sys_info.sclk_voltage_mapping_table,
1689 igp_info->info_6.sAvail_SCLK);
1690 sumo_construct_vid_mapping_table(rdev, &pi->sys_info.vid_mapping_table,
1691 igp_info->info_6.sAvail_SCLK);
1697 static void sumo_construct_boot_and_acpi_state(struct radeon_device *rdev)
1699 struct sumo_power_info *pi = sumo_get_pi(rdev);
1701 pi->boot_pl.sclk = pi->sys_info.bootup_sclk;
1702 pi->boot_pl.vddc_index = pi->sys_info.bootup_nb_voltage_index;
1703 pi->boot_pl.ds_divider_index = 0;
1704 pi->boot_pl.ss_divider_index = 0;
1705 pi->boot_pl.allow_gnb_slow = 1;
1706 pi->acpi_pl = pi->boot_pl;
1707 pi->current_ps.num_levels = 1;
1708 pi->current_ps.levels[0] = pi->boot_pl;
1711 int sumo_dpm_init(struct radeon_device *rdev)
1713 struct sumo_power_info *pi;
1714 u32 hw_rev = (RREG32(HW_REV) & ATI_REV_ID_MASK) >> ATI_REV_ID_SHIFT;
1717 pi = kzalloc(sizeof(struct sumo_power_info), GFP_KERNEL);
1720 rdev->pm.dpm.priv = pi;
1722 pi->driver_nbps_policy_disable = false;
1723 if ((rdev->family == CHIP_PALM) && (hw_rev < 3))
1724 pi->disable_gfx_power_gating_in_uvd = true;
1726 pi->disable_gfx_power_gating_in_uvd = false;
1727 pi->enable_alt_vddnb = true;
1728 pi->enable_sclk_ds = true;
1729 pi->enable_dynamic_m3_arbiter = false;
1730 pi->enable_dynamic_patch_ps = true;
1731 pi->enable_gfx_power_gating = true;
1732 pi->enable_gfx_clock_gating = true;
1733 pi->enable_mg_clock_gating = true;
1734 pi->enable_auto_thermal_throttling = true;
1736 ret = sumo_parse_sys_info_table(rdev);
1740 sumo_construct_boot_and_acpi_state(rdev);
1742 ret = sumo_parse_power_table(rdev);
1746 pi->pasi = CYPRESS_HASI_DFLT;
1747 pi->asi = RV770_ASI_DFLT;
1748 pi->thermal_auto_throttling = pi->sys_info.htc_tmp_lmt;
1749 pi->enable_boost = pi->sys_info.enable_boost;
1750 pi->enable_dpm = true;
1755 void sumo_dpm_print_power_state(struct radeon_device *rdev,
1756 struct radeon_ps *rps)
1759 struct sumo_ps *ps = sumo_get_ps(rps);
1761 r600_dpm_print_class_info(rps->class, rps->class2);
1762 r600_dpm_print_cap_info(rps->caps);
1763 printk("\tuvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1764 for (i = 0; i < ps->num_levels; i++) {
1765 struct sumo_pl *pl = &ps->levels[i];
1766 printk("\t\tpower level %d sclk: %u vddc: %u\n",
1768 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1770 r600_dpm_print_ps_status(rdev, rps);
1773 void sumo_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
1776 struct sumo_power_info *pi = sumo_get_pi(rdev);
1777 struct radeon_ps *rps = rdev->pm.dpm.current_ps;
1778 struct sumo_ps *ps = sumo_get_ps(rps);
1781 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURR_INDEX_MASK) >>
1784 if (current_index == BOOST_DPM_LEVEL) {
1786 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1787 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1788 current_index, pl->sclk,
1789 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1790 } else if (current_index >= ps->num_levels) {
1791 seq_printf(m, "invalid dpm profile %d\n", current_index);
1793 pl = &ps->levels[current_index];
1794 seq_printf(m, "uvd vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
1795 seq_printf(m, "power level %d sclk: %u vddc: %u\n",
1796 current_index, pl->sclk,
1797 sumo_convert_voltage_index_to_value(rdev, pl->vddc_index));
1801 void sumo_dpm_fini(struct radeon_device *rdev)
1805 sumo_cleanup_asic(rdev); /* ??? */
1807 for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
1808 kfree(rdev->pm.dpm.ps[i].ps_priv);
1810 kfree(rdev->pm.dpm.ps);
1811 kfree(rdev->pm.dpm.priv);
1814 u32 sumo_dpm_get_sclk(struct radeon_device *rdev, bool low)
1816 struct sumo_power_info *pi = sumo_get_pi(rdev);
1817 struct sumo_ps *requested_state = sumo_get_ps(&pi->requested_rps);
1820 return requested_state->levels[0].sclk;
1822 return requested_state->levels[requested_state->num_levels - 1].sclk;
1825 u32 sumo_dpm_get_mclk(struct radeon_device *rdev, bool low)
1827 struct sumo_power_info *pi = sumo_get_pi(rdev);
1829 return pi->sys_info.bootup_uma_clk;