drivers/gpu/drm/i915/i915_irq.c

   1 /* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
   2  */
   3 /*
   4  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
   5  * All Rights Reserved.
   6  *
   7  * Permission is hereby granted, free of charge, to any person obtaining a
   8  * copy of this software and associated documentation files (the
   9  * "Software"), to deal in the Software without restriction, including
  10  * without limitation the rights to use, copy, modify, merge, publish,
  11  * distribute, sub license, and/or sell copies of the Software, and to
  12  * permit persons to whom the Software is furnished to do so, subject to
  13  * the following conditions:
  14  *
  15  * The above copyright notice and this permission notice (including the
  16  * next paragraph) shall be included in all copies or substantial portions
  17  * of the Software.
  18  *
  19  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
  20  * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  21  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
  22  * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
  23  * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
  24  * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
  25  * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
  26  *
  27  */
  28
  29 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30
  31 #include <linux/sysrq.h>
  32 #include <linux/slab.h>
  33 #include <drm/drmP.h>
  34 #include <drm/i915_drm.h>
  35 #include "i915_drv.h"
  36 #include "i915_trace.h"
  37 #include "intel_drv.h"
  38
  39 static const u32 hpd_ibx[] = {
  40         [HPD_CRT] = SDE_CRT_HOTPLUG,
  41         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
  42         [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
  43         [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
  44         [HPD_PORT_D] = SDE_PORTD_HOTPLUG
  45 };
  46
  47 static const u32 hpd_cpt[] = {
  48         [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
  49         [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
  50         [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
  51         [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
  52         [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
  53 };
  54
  55 static const u32 hpd_mask_i915[] = {
  56         [HPD_CRT] = CRT_HOTPLUG_INT_EN,
  57         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
  58         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
  59         [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
  60         [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
  61         [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
  62 };
  63
  64 static const u32 hpd_status_gen4[] = {
  65         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  66         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
  67         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
  68         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  69         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  70         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  71 };
  72
  73 static const u32 hpd_status_i965[] = {
  74          [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  75          [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I965,
  76          [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I965,
  77          [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  78          [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  79          [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  80 };
  81
  82 static const u32 hpd_status_i915[] = { /* i915 and valleyview are the same */
  83         [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
  84         [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
  85         [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
  86         [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
  87         [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
  88         [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
  89 };
  90
  91 static void ibx_hpd_irq_setup(struct drm_device *dev);
  92 static void i915_hpd_irq_setup(struct drm_device *dev);
  93
  94 /* For display hotplug interrupt */
  95 static void
  96 ironlake_enable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
  97 {
  98         if ((dev_priv->irq_mask & mask) != 0) {
  99                 dev_priv->irq_mask &= ~mask;
 100                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 101                 POSTING_READ(DEIMR);
 102         }
 103 }
 104
 105 static void
 106 ironlake_disable_display_irq(drm_i915_private_t *dev_priv, u32 mask)
 107 {
 108         if ((dev_priv->irq_mask & mask) != mask) {
 109                 dev_priv->irq_mask |= mask;
 110                 I915_WRITE(DEIMR, dev_priv->irq_mask);
 111                 POSTING_READ(DEIMR);
 112         }
 113 }
 114
 115 void
 116 i915_enable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 117 {
 118         u32 reg = PIPESTAT(pipe);
 119         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 120
 121         if ((pipestat & mask) == mask)
 122                 return;
 123
 124         /* Enable the interrupt, clear any pending status */
 125         pipestat |= mask | (mask >> 16);
 126         I915_WRITE(reg, pipestat);
 127         POSTING_READ(reg);
 128 }
 129
 130 void
 131 i915_disable_pipestat(drm_i915_private_t *dev_priv, int pipe, u32 mask)
 132 {
 133         u32 reg = PIPESTAT(pipe);
 134         u32 pipestat = I915_READ(reg) & 0x7fff0000;
 135
 136         if ((pipestat & mask) == 0)
 137                 return;
 138
 139         pipestat &= ~mask;
 140         I915_WRITE(reg, pipestat);
 141         POSTING_READ(reg);
 142 }
 143
 144 /**
 145  * intel_enable_asle - enable ASLE interrupt for OpRegion
 146  */
 147 void intel_enable_asle(struct drm_device *dev)
 148 {
 149         drm_i915_private_t *dev_priv = dev->dev_private;
 150         unsigned long irqflags;
 151
 152         /* FIXME: opregion/asle for VLV */
 153         if (IS_VALLEYVIEW(dev))
 154                 return;
 155
 156         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 157
 158         if (HAS_PCH_SPLIT(dev))
 159                 ironlake_enable_display_irq(dev_priv, DE_GSE);
 160         else {
 161                 i915_enable_pipestat(dev_priv, 1,
 162                                      PIPE_LEGACY_BLC_EVENT_ENABLE);
 163                 if (INTEL_INFO(dev)->gen >= 4)
 164                         i915_enable_pipestat(dev_priv, 0,
 165                                              PIPE_LEGACY_BLC_EVENT_ENABLE);
 166         }
 167
 168         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 169 }
 170
 171 /**
 172  * i915_pipe_enabled - check if a pipe is enabled
 173  * @dev: DRM device
 174  * @pipe: pipe to check
 175  *
 176  * Reading certain registers when the pipe is disabled can hang the chip.
 177  * Use this routine to make sure the PLL is running and the pipe is active
 178  * before reading such registers if unsure.
 179  */
 180 static int
 181 i915_pipe_enabled(struct drm_device *dev, int pipe)
 182 {
 183         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 184         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 185                                                                       pipe);
 186
 187         return I915_READ(PIPECONF(cpu_transcoder)) & PIPECONF_ENABLE;
 188 }
 189
 190 /* Called from drm generic code, passed a 'crtc', which
 191  * we use as a pipe index
 192  */
 193 static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
 194 {
 195         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 196         unsigned long high_frame;
 197         unsigned long low_frame;
 198         u32 high1, high2, low;
 199
 200         if (!i915_pipe_enabled(dev, pipe)) {
 201                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 202                                 "pipe %c\n", pipe_name(pipe));
 203                 return 0;
 204         }
 205
 206         high_frame = PIPEFRAME(pipe);
 207         low_frame = PIPEFRAMEPIXEL(pipe);
 208
 209         /*
 210          * High & low register fields aren't synchronized, so make sure
 211          * we get a low value that's stable across two reads of the high
 212          * register.
 213          */
 214         do {
 215                 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 216                 low   = I915_READ(low_frame)  & PIPE_FRAME_LOW_MASK;
 217                 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
 218         } while (high1 != high2);
 219
 220         high1 >>= PIPE_FRAME_HIGH_SHIFT;
 221         low >>= PIPE_FRAME_LOW_SHIFT;
 222         return (high1 << 8) | low;
 223 }
 224
 225 static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
 226 {
 227         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 228         int reg = PIPE_FRMCOUNT_GM45(pipe);
 229
 230         if (!i915_pipe_enabled(dev, pipe)) {
 231                 DRM_DEBUG_DRIVER("trying to get vblank count for disabled "
 232                                  "pipe %c\n", pipe_name(pipe));
 233                 return 0;
 234         }
 235
 236         return I915_READ(reg);
 237 }
 238
 239 static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
 240                              int *vpos, int *hpos)
 241 {
 242         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 243         u32 vbl = 0, position = 0;
 244         int vbl_start, vbl_end, htotal, vtotal;
 245         bool in_vbl = true;
 246         int ret = 0;
 247         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 248                                                                       pipe);
 249
 250         if (!i915_pipe_enabled(dev, pipe)) {
 251                 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
 252                                  "pipe %c\n", pipe_name(pipe));
 253                 return 0;
 254         }
 255
 256         /* Get vtotal. */
 257         vtotal = 1 + ((I915_READ(VTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 258
 259         if (INTEL_INFO(dev)->gen >= 4) {
 260                 /* No obvious pixelcount register. Only query vertical
 261                  * scanout position from Display scan line register.
 262                  */
 263                 position = I915_READ(PIPEDSL(pipe));
 264
 265                 /* Decode into vertical scanout position. Don't have
 266                  * horizontal scanout position.
 267                  */
 268                 *vpos = position & 0x1fff;
 269                 *hpos = 0;
 270         } else {
 271                 /* Have access to pixelcount since start of frame.
 272                  * We can split this into vertical and horizontal
 273                  * scanout position.
 274                  */
 275                 position = (I915_READ(PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
 276
 277                 htotal = 1 + ((I915_READ(HTOTAL(cpu_transcoder)) >> 16) & 0x1fff);
 278                 *vpos = position / htotal;
 279                 *hpos = position - (*vpos * htotal);
 280         }
 281
 282         /* Query vblank area. */
 283         vbl = I915_READ(VBLANK(cpu_transcoder));
 284
 285         /* Test position against vblank region. */
 286         vbl_start = vbl & 0x1fff;
 287         vbl_end = (vbl >> 16) & 0x1fff;
 288
 289         if ((*vpos < vbl_start) || (*vpos > vbl_end))
 290                 in_vbl = false;
 291
 292         /* Inside "upper part" of vblank area? Apply corrective offset: */
 293         if (in_vbl && (*vpos >= vbl_start))
 294                 *vpos = *vpos - vtotal;
 295
 296         /* Readouts valid? */
 297         if (vbl > 0)
 298                 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
 299
 300         /* In vblank? */
 301         if (in_vbl)
 302                 ret |= DRM_SCANOUTPOS_INVBL;
 303
 304         return ret;
 305 }
 306
 307 static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
 308                               int *max_error,
 309                               struct timeval *vblank_time,
 310                               unsigned flags)
 311 {
 312         struct drm_crtc *crtc;
 313
 314         if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
 315                 DRM_ERROR("Invalid crtc %d\n", pipe);
 316                 return -EINVAL;
 317         }
 318
 319         /* Get drm_crtc to timestamp: */
 320         crtc = intel_get_crtc_for_pipe(dev, pipe);
 321         if (crtc == NULL) {
 322                 DRM_ERROR("Invalid crtc %d\n", pipe);
 323                 return -EINVAL;
 324         }
 325
 326         if (!crtc->enabled) {
 327                 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
 328                 return -EBUSY;
 329         }
 330
 331         /* Helper routine in DRM core does all the work: */
 332         return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
 333                                                      vblank_time, flags,
 334                                                      crtc);
 335 }
 336
 337 /*
 338  * Handle hotplug events outside the interrupt handler proper.
 339  */
 340 #define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
 341
 342 static void i915_hotplug_work_func(struct work_struct *work)
 343 {
 344         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 345                                                     hotplug_work);
 346         struct drm_device *dev = dev_priv->dev;
 347         struct drm_mode_config *mode_config = &dev->mode_config;
 348         struct intel_connector *intel_connector;
 349         struct intel_encoder *intel_encoder;
 350         struct drm_connector *connector;
 351         unsigned long irqflags;
 352         bool hpd_disabled = false;
 353
 354         /* HPD irq before everything is fully set up. */
 355         if (!dev_priv->enable_hotplug_processing)
 356                 return;
 357
 358         mutex_lock(&mode_config->mutex);
 359         DRM_DEBUG_KMS("running encoder hotplug functions\n");
 360
 361         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 362         list_for_each_entry(connector, &mode_config->connector_list, head) {
 363                 intel_connector = to_intel_connector(connector);
 364                 intel_encoder = intel_connector->encoder;
 365                 if (intel_encoder->hpd_pin > HPD_NONE &&
 366                     dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
 367                     connector->polled == DRM_CONNECTOR_POLL_HPD) {
 368                         DRM_INFO("HPD interrupt storm detected on connector %s: "
 369                                  "switching from hotplug detection to polling\n",
 370                                 drm_get_connector_name(connector));
 371                         dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
 372                         connector->polled = DRM_CONNECTOR_POLL_CONNECT
 373                                 | DRM_CONNECTOR_POLL_DISCONNECT;
 374                         hpd_disabled = true;
 375                 }
 376         }
 377          /* if there were no outputs to poll, poll was disabled,
 378           * therefore make sure it's enabled when disabling HPD on
 379           * some connectors */
 380         if (hpd_disabled) {
 381                 drm_kms_helper_poll_enable(dev);
 382                 mod_timer(&dev_priv->hotplug_reenable_timer,
 383                           jiffies + msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
 384         }
 385
 386         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 387
 388         list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
 389                 if (intel_encoder->hot_plug)
 390                         intel_encoder->hot_plug(intel_encoder);
 391
 392         mutex_unlock(&mode_config->mutex);
 393
 394         /* Just fire off a uevent and let userspace tell us what to do */
 395         drm_helper_hpd_irq_event(dev);
 396 }
 397
 398 static void ironlake_handle_rps_change(struct drm_device *dev)
 399 {
 400         drm_i915_private_t *dev_priv = dev->dev_private;
 401         u32 busy_up, busy_down, max_avg, min_avg;
 402         u8 new_delay;
 403         unsigned long flags;
 404
 405         spin_lock_irqsave(&mchdev_lock, flags);
 406
 407         I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
 408
 409         new_delay = dev_priv->ips.cur_delay;
 410
 411         I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
 412         busy_up = I915_READ(RCPREVBSYTUPAVG);
 413         busy_down = I915_READ(RCPREVBSYTDNAVG);
 414         max_avg = I915_READ(RCBMAXAVG);
 415         min_avg = I915_READ(RCBMINAVG);
 416
 417         /* Handle RCS change request from hw */
 418         if (busy_up > max_avg) {
 419                 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
 420                         new_delay = dev_priv->ips.cur_delay - 1;
 421                 if (new_delay < dev_priv->ips.max_delay)
 422                         new_delay = dev_priv->ips.max_delay;
 423         } else if (busy_down < min_avg) {
 424                 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
 425                         new_delay = dev_priv->ips.cur_delay + 1;
 426                 if (new_delay > dev_priv->ips.min_delay)
 427                         new_delay = dev_priv->ips.min_delay;
 428         }
 429
 430         if (ironlake_set_drps(dev, new_delay))
 431                 dev_priv->ips.cur_delay = new_delay;
 432
 433         spin_unlock_irqrestore(&mchdev_lock, flags);
 434
 435         return;
 436 }
 437
 438 static void notify_ring(struct drm_device *dev,
 439                         struct intel_ring_buffer *ring)
 440 {
 441         struct drm_i915_private *dev_priv = dev->dev_private;
 442
 443         if (ring->obj == NULL)
 444                 return;
 445
 446         trace_i915_gem_request_complete(ring, ring->get_seqno(ring, false));
 447
 448         wake_up_all(&ring->irq_queue);
 449         if (i915_enable_hangcheck) {
 450                 dev_priv->gpu_error.hangcheck_count = 0;
 451                 mod_timer(&dev_priv->gpu_error.hangcheck_timer,
 452                           round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
 453         }
 454 }
 455
 456 static void gen6_pm_rps_work(struct work_struct *work)
 457 {
 458         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 459                                                     rps.work);
 460         u32 pm_iir, pm_imr;
 461         u8 new_delay;
 462
 463         spin_lock_irq(&dev_priv->rps.lock);
 464         pm_iir = dev_priv->rps.pm_iir;
 465         dev_priv->rps.pm_iir = 0;
 466         pm_imr = I915_READ(GEN6_PMIMR);
 467         I915_WRITE(GEN6_PMIMR, 0);
 468         spin_unlock_irq(&dev_priv->rps.lock);
 469
 470         if ((pm_iir & GEN6_PM_DEFERRED_EVENTS) == 0)
 471                 return;
 472
 473         mutex_lock(&dev_priv->rps.hw_lock);
 474
 475         if (pm_iir & GEN6_PM_RP_UP_THRESHOLD)
 476                 new_delay = dev_priv->rps.cur_delay + 1;
 477         else
 478                 new_delay = dev_priv->rps.cur_delay - 1;
 479
 480         /* sysfs frequency interfaces may have snuck in while servicing the
 481          * interrupt
 482          */
 483         if (!(new_delay > dev_priv->rps.max_delay ||
 484               new_delay < dev_priv->rps.min_delay)) {
 485                 if (IS_VALLEYVIEW(dev_priv->dev))
 486                         valleyview_set_rps(dev_priv->dev, new_delay);
 487                 else
 488                         gen6_set_rps(dev_priv->dev, new_delay);
 489         }
 490
 491         mutex_unlock(&dev_priv->rps.hw_lock);
 492 }
 493
 494
 495 /**
 496  * ivybridge_parity_work - Workqueue called when a parity error interrupt
 497  * occurred.
 498  * @work: workqueue struct
 499  *
 500  * Doesn't actually do anything except notify userspace. As a consequence of
 501  * this event, userspace should try to remap the bad rows since statistically
 502  * it is likely the same row is more likely to go bad again.
 503  */
 504 static void ivybridge_parity_work(struct work_struct *work)
 505 {
 506         drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
 507                                                     l3_parity.error_work);
 508         u32 error_status, row, bank, subbank;
 509         char *parity_event[5];
 510         uint32_t misccpctl;
 511         unsigned long flags;
 512
 513         /* We must turn off DOP level clock gating to access the L3 registers.
 514          * In order to prevent a get/put style interface, acquire struct mutex
 515          * any time we access those registers.
 516          */
 517         mutex_lock(&dev_priv->dev->struct_mutex);
 518
 519         misccpctl = I915_READ(GEN7_MISCCPCTL);
 520         I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
 521         POSTING_READ(GEN7_MISCCPCTL);
 522
 523         error_status = I915_READ(GEN7_L3CDERRST1);
 524         row = GEN7_PARITY_ERROR_ROW(error_status);
 525         bank = GEN7_PARITY_ERROR_BANK(error_status);
 526         subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
 527
 528         I915_WRITE(GEN7_L3CDERRST1, GEN7_PARITY_ERROR_VALID |
 529                                     GEN7_L3CDERRST1_ENABLE);
 530         POSTING_READ(GEN7_L3CDERRST1);
 531
 532         I915_WRITE(GEN7_MISCCPCTL, misccpctl);
 533
 534         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 535         dev_priv->gt_irq_mask &= ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 536         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 537         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 538
 539         mutex_unlock(&dev_priv->dev->struct_mutex);
 540
 541         parity_event[0] = "L3_PARITY_ERROR=1";
 542         parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
 543         parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
 544         parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
 545         parity_event[4] = NULL;
 546
 547         kobject_uevent_env(&dev_priv->dev->primary->kdev.kobj,
 548                            KOBJ_CHANGE, parity_event);
 549
 550         DRM_DEBUG("Parity error: Row = %d, Bank = %d, Sub bank = %d.\n",
 551                   row, bank, subbank);
 552
 553         kfree(parity_event[3]);
 554         kfree(parity_event[2]);
 555         kfree(parity_event[1]);
 556 }
 557
 558 static void ivybridge_handle_parity_error(struct drm_device *dev)
 559 {
 560         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 561         unsigned long flags;
 562
 563         if (!HAS_L3_GPU_CACHE(dev))
 564                 return;
 565
 566         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 567         dev_priv->gt_irq_mask |= GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
 568         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 569         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 570
 571         queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
 572 }
 573
 574 static void snb_gt_irq_handler(struct drm_device *dev,
 575                                struct drm_i915_private *dev_priv,
 576                                u32 gt_iir)
 577 {
 578
 579         if (gt_iir & (GEN6_RENDER_USER_INTERRUPT |
 580                       GEN6_RENDER_PIPE_CONTROL_NOTIFY_INTERRUPT))
 581                 notify_ring(dev, &dev_priv->ring[RCS]);
 582         if (gt_iir & GEN6_BSD_USER_INTERRUPT)
 583                 notify_ring(dev, &dev_priv->ring[VCS]);
 584         if (gt_iir & GEN6_BLITTER_USER_INTERRUPT)
 585                 notify_ring(dev, &dev_priv->ring[BCS]);
 586
 587         if (gt_iir & (GT_GEN6_BLT_CS_ERROR_INTERRUPT |
 588                       GT_GEN6_BSD_CS_ERROR_INTERRUPT |
 589                       GT_RENDER_CS_ERROR_INTERRUPT)) {
 590                 DRM_ERROR("GT error interrupt 0x%08x\n", gt_iir);
 591                 i915_handle_error(dev, false);
 592         }
 593
 594         if (gt_iir & GT_GEN7_L3_PARITY_ERROR_INTERRUPT)
 595                 ivybridge_handle_parity_error(dev);
 596 }
 597
 598 static void gen6_queue_rps_work(struct drm_i915_private *dev_priv,
 599                                 u32 pm_iir)
 600 {
 601         unsigned long flags;
 602
 603         /*
 604          * IIR bits should never already be set because IMR should
 605          * prevent an interrupt from being shown in IIR. The warning
 606          * displays a case where we've unsafely cleared
 607          * dev_priv->rps.pm_iir. Although missing an interrupt of the same
 608          * type is not a problem, it displays a problem in the logic.
 609          *
 610          * The mask bit in IMR is cleared by dev_priv->rps.work.
 611          */
 612
 613         spin_lock_irqsave(&dev_priv->rps.lock, flags);
 614         dev_priv->rps.pm_iir |= pm_iir;
 615         I915_WRITE(GEN6_PMIMR, dev_priv->rps.pm_iir);
 616         POSTING_READ(GEN6_PMIMR);
 617         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
 618
 619         queue_work(dev_priv->wq, &dev_priv->rps.work);
 620 }
 621
 622 #define HPD_STORM_DETECT_PERIOD 1000
 623 #define HPD_STORM_THRESHOLD 5
 624
 625 static inline bool hotplug_irq_storm_detect(struct drm_device *dev,
 626                                             u32 hotplug_trigger,
 627                                             const u32 *hpd)
 628 {
 629         drm_i915_private_t *dev_priv = dev->dev_private;
 630         unsigned long irqflags;
 631         int i;
 632         bool ret = false;
 633
 634         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 635
 636         for (i = 1; i < HPD_NUM_PINS; i++) {
 637
 638                 if (!(hpd[i] & hotplug_trigger) ||
 639                     dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
 640                         continue;
 641
 642                 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
 643                                    dev_priv->hpd_stats[i].hpd_last_jiffies
 644                                    + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
 645                         dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
 646                         dev_priv->hpd_stats[i].hpd_cnt = 0;
 647                 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
 648                         dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
 649                         DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
 650                         ret = true;
 651                 } else {
 652                         dev_priv->hpd_stats[i].hpd_cnt++;
 653                 }
 654         }
 655
 656         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 657
 658         return ret;
 659 }
 660
 661 static void gmbus_irq_handler(struct drm_device *dev)
 662 {
 663         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 664
 665         wake_up_all(&dev_priv->gmbus_wait_queue);
 666 }
 667
 668 static void dp_aux_irq_handler(struct drm_device *dev)
 669 {
 670         struct drm_i915_private *dev_priv = (drm_i915_private_t *) dev->dev_private;
 671
 672         wake_up_all(&dev_priv->gmbus_wait_queue);
 673 }
 674
 675 static irqreturn_t valleyview_irq_handler(int irq, void *arg)
 676 {
 677         struct drm_device *dev = (struct drm_device *) arg;
 678         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 679         u32 iir, gt_iir, pm_iir;
 680         irqreturn_t ret = IRQ_NONE;
 681         unsigned long irqflags;
 682         int pipe;
 683         u32 pipe_stats[I915_MAX_PIPES];
 684
 685         atomic_inc(&dev_priv->irq_received);
 686
 687         while (true) {
 688                 iir = I915_READ(VLV_IIR);
 689                 gt_iir = I915_READ(GTIIR);
 690                 pm_iir = I915_READ(GEN6_PMIIR);
 691
 692                 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
 693                         goto out;
 694
 695                 ret = IRQ_HANDLED;
 696
 697                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 698
 699                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
 700                 for_each_pipe(pipe) {
 701                         int reg = PIPESTAT(pipe);
 702                         pipe_stats[pipe] = I915_READ(reg);
 703
 704                         /*
 705                          * Clear the PIPE*STAT regs before the IIR
 706                          */
 707                         if (pipe_stats[pipe] & 0x8000ffff) {
 708                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
 709                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
 710                                                          pipe_name(pipe));
 711                                 I915_WRITE(reg, pipe_stats[pipe]);
 712                         }
 713                 }
 714                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
 715
 716                 for_each_pipe(pipe) {
 717                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS)
 718                                 drm_handle_vblank(dev, pipe);
 719
 720                         if (pipe_stats[pipe] & PLANE_FLIPDONE_INT_STATUS_VLV) {
 721                                 intel_prepare_page_flip(dev, pipe);
 722                                 intel_finish_page_flip(dev, pipe);
 723                         }
 724                 }
 725
 726                 /* Consume port.  Then clear IIR or we'll miss events */
 727                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
 728                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
 729                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
 730
 731                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
 732                                          hotplug_status);
 733                         if (hotplug_trigger) {
 734                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
 735                                         i915_hpd_irq_setup(dev);
 736                                 queue_work(dev_priv->wq,
 737                                            &dev_priv->hotplug_work);
 738                         }
 739                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
 740                         I915_READ(PORT_HOTPLUG_STAT);
 741                 }
 742
 743                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
 744                         gmbus_irq_handler(dev);
 745
 746                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 747                         gen6_queue_rps_work(dev_priv, pm_iir);
 748
 749                 I915_WRITE(GTIIR, gt_iir);
 750                 I915_WRITE(GEN6_PMIIR, pm_iir);
 751                 I915_WRITE(VLV_IIR, iir);
 752         }
 753
 754 out:
 755         return ret;
 756 }
 757
 758 static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
 759 {
 760         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 761         int pipe;
 762         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
 763
 764         if (hotplug_trigger) {
 765                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_ibx))
 766                         ibx_hpd_irq_setup(dev);
 767                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 768         }
 769         if (pch_iir & SDE_AUDIO_POWER_MASK) {
 770                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
 771                                SDE_AUDIO_POWER_SHIFT);
 772                 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
 773                                  port_name(port));
 774         }
 775
 776         if (pch_iir & SDE_AUX_MASK)
 777                 dp_aux_irq_handler(dev);
 778
 779         if (pch_iir & SDE_GMBUS)
 780                 gmbus_irq_handler(dev);
 781
 782         if (pch_iir & SDE_AUDIO_HDCP_MASK)
 783                 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
 784
 785         if (pch_iir & SDE_AUDIO_TRANS_MASK)
 786                 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
 787
 788         if (pch_iir & SDE_POISON)
 789                 DRM_ERROR("PCH poison interrupt\n");
 790
 791         if (pch_iir & SDE_FDI_MASK)
 792                 for_each_pipe(pipe)
 793                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 794                                          pipe_name(pipe),
 795                                          I915_READ(FDI_RX_IIR(pipe)));
 796
 797         if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
 798                 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
 799
 800         if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
 801                 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
 802
 803         if (pch_iir & SDE_TRANSB_FIFO_UNDER)
 804                 DRM_DEBUG_DRIVER("PCH transcoder B underrun interrupt\n");
 805         if (pch_iir & SDE_TRANSA_FIFO_UNDER)
 806                 DRM_DEBUG_DRIVER("PCH transcoder A underrun interrupt\n");
 807 }
 808
 809 static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
 810 {
 811         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 812         int pipe;
 813         u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
 814
 815         if (hotplug_trigger) {
 816                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_cpt))
 817                         ibx_hpd_irq_setup(dev);
 818                 queue_work(dev_priv->wq, &dev_priv->hotplug_work);
 819         }
 820         if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
 821                 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
 822                                SDE_AUDIO_POWER_SHIFT_CPT);
 823                 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
 824                                  port_name(port));
 825         }
 826
 827         if (pch_iir & SDE_AUX_MASK_CPT)
 828                 dp_aux_irq_handler(dev);
 829
 830         if (pch_iir & SDE_GMBUS_CPT)
 831                 gmbus_irq_handler(dev);
 832
 833         if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
 834                 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
 835
 836         if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
 837                 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
 838
 839         if (pch_iir & SDE_FDI_MASK_CPT)
 840                 for_each_pipe(pipe)
 841                         DRM_DEBUG_DRIVER("  pipe %c FDI IIR: 0x%08x\n",
 842                                          pipe_name(pipe),
 843                                          I915_READ(FDI_RX_IIR(pipe)));
 844 }
 845
 846 static irqreturn_t ivybridge_irq_handler(int irq, void *arg)
 847 {
 848         struct drm_device *dev = (struct drm_device *) arg;
 849         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 850         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier = 0;
 851         irqreturn_t ret = IRQ_NONE;
 852         int i;
 853
 854         atomic_inc(&dev_priv->irq_received);
 855
 856         /* disable master interrupt before clearing iir  */
 857         de_ier = I915_READ(DEIER);
 858         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 859
 860         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 861          * interrupts will will be stored on its back queue, and then we'll be
 862          * able to process them after we restore SDEIER (as soon as we restore
 863          * it, we'll get an interrupt if SDEIIR still has something to process
 864          * due to its back queue). */
 865         if (!HAS_PCH_NOP(dev)) {
 866                 sde_ier = I915_READ(SDEIER);
 867                 I915_WRITE(SDEIER, 0);
 868                 POSTING_READ(SDEIER);
 869         }
 870
 871         gt_iir = I915_READ(GTIIR);
 872         if (gt_iir) {
 873                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 874                 I915_WRITE(GTIIR, gt_iir);
 875                 ret = IRQ_HANDLED;
 876         }
 877
 878         de_iir = I915_READ(DEIIR);
 879         if (de_iir) {
 880                 if (de_iir & DE_AUX_CHANNEL_A_IVB)
 881                         dp_aux_irq_handler(dev);
 882
 883                 if (de_iir & DE_GSE_IVB)
 884                         intel_opregion_gse_intr(dev);
 885
 886                 for (i = 0; i < 3; i++) {
 887                         if (de_iir & (DE_PIPEA_VBLANK_IVB << (5 * i)))
 888                                 drm_handle_vblank(dev, i);
 889                         if (de_iir & (DE_PLANEA_FLIP_DONE_IVB << (5 * i))) {
 890                                 intel_prepare_page_flip(dev, i);
 891                                 intel_finish_page_flip_plane(dev, i);
 892                         }
 893                 }
 894
 895                 /* check event from PCH */
 896                 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
 897                         u32 pch_iir = I915_READ(SDEIIR);
 898
 899                         cpt_irq_handler(dev, pch_iir);
 900
 901                         /* clear PCH hotplug event before clear CPU irq */
 902                         I915_WRITE(SDEIIR, pch_iir);
 903                 }
 904
 905                 I915_WRITE(DEIIR, de_iir);
 906                 ret = IRQ_HANDLED;
 907         }
 908
 909         pm_iir = I915_READ(GEN6_PMIIR);
 910         if (pm_iir) {
 911                 if (pm_iir & GEN6_PM_DEFERRED_EVENTS)
 912                         gen6_queue_rps_work(dev_priv, pm_iir);
 913                 I915_WRITE(GEN6_PMIIR, pm_iir);
 914                 ret = IRQ_HANDLED;
 915         }
 916
 917         I915_WRITE(DEIER, de_ier);
 918         POSTING_READ(DEIER);
 919         if (!HAS_PCH_NOP(dev)) {
 920                 I915_WRITE(SDEIER, sde_ier);
 921                 POSTING_READ(SDEIER);
 922         }
 923
 924         return ret;
 925 }
 926
 927 static void ilk_gt_irq_handler(struct drm_device *dev,
 928                                struct drm_i915_private *dev_priv,
 929                                u32 gt_iir)
 930 {
 931         if (gt_iir & (GT_USER_INTERRUPT | GT_PIPE_NOTIFY))
 932                 notify_ring(dev, &dev_priv->ring[RCS]);
 933         if (gt_iir & GT_BSD_USER_INTERRUPT)
 934                 notify_ring(dev, &dev_priv->ring[VCS]);
 935 }
 936
 937 static irqreturn_t ironlake_irq_handler(int irq, void *arg)
 938 {
 939         struct drm_device *dev = (struct drm_device *) arg;
 940         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
 941         int ret = IRQ_NONE;
 942         u32 de_iir, gt_iir, de_ier, pm_iir, sde_ier;
 943
 944         atomic_inc(&dev_priv->irq_received);
 945
 946         /* disable master interrupt before clearing iir  */
 947         de_ier = I915_READ(DEIER);
 948         I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
 949         POSTING_READ(DEIER);
 950
 951         /* Disable south interrupts. We'll only write to SDEIIR once, so further
 952          * interrupts will will be stored on its back queue, and then we'll be
 953          * able to process them after we restore SDEIER (as soon as we restore
 954          * it, we'll get an interrupt if SDEIIR still has something to process
 955          * due to its back queue). */
 956         sde_ier = I915_READ(SDEIER);
 957         I915_WRITE(SDEIER, 0);
 958         POSTING_READ(SDEIER);
 959
 960         de_iir = I915_READ(DEIIR);
 961         gt_iir = I915_READ(GTIIR);
 962         pm_iir = I915_READ(GEN6_PMIIR);
 963
 964         if (de_iir == 0 && gt_iir == 0 && (!IS_GEN6(dev) || pm_iir == 0))
 965                 goto done;
 966
 967         ret = IRQ_HANDLED;
 968
 969         if (IS_GEN5(dev))
 970                 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
 971         else
 972                 snb_gt_irq_handler(dev, dev_priv, gt_iir);
 973
 974         if (de_iir & DE_AUX_CHANNEL_A)
 975                 dp_aux_irq_handler(dev);
 976
 977         if (de_iir & DE_GSE)
 978                 intel_opregion_gse_intr(dev);
 979
 980         if (de_iir & DE_PIPEA_VBLANK)
 981                 drm_handle_vblank(dev, 0);
 982
 983         if (de_iir & DE_PIPEB_VBLANK)
 984                 drm_handle_vblank(dev, 1);
 985
 986         if (de_iir & DE_PLANEA_FLIP_DONE) {
 987                 intel_prepare_page_flip(dev, 0);
 988                 intel_finish_page_flip_plane(dev, 0);
 989         }
 990
 991         if (de_iir & DE_PLANEB_FLIP_DONE) {
 992                 intel_prepare_page_flip(dev, 1);
 993                 intel_finish_page_flip_plane(dev, 1);
 994         }
 995
 996         /* check event from PCH */
 997         if (de_iir & DE_PCH_EVENT) {
 998                 u32 pch_iir = I915_READ(SDEIIR);
 999
1000                 if (HAS_PCH_CPT(dev))
1001                         cpt_irq_handler(dev, pch_iir);
1002                 else
1003                         ibx_irq_handler(dev, pch_iir);
1004
1005                 /* should clear PCH hotplug event before clear CPU irq */
1006                 I915_WRITE(SDEIIR, pch_iir);
1007         }
1008
1009         if (IS_GEN5(dev) &&  de_iir & DE_PCU_EVENT)
1010                 ironlake_handle_rps_change(dev);
1011
1012         if (IS_GEN6(dev) && pm_iir & GEN6_PM_DEFERRED_EVENTS)
1013                 gen6_queue_rps_work(dev_priv, pm_iir);
1014
1015         I915_WRITE(GTIIR, gt_iir);
1016         I915_WRITE(DEIIR, de_iir);
1017         I915_WRITE(GEN6_PMIIR, pm_iir);
1018
1019 done:
1020         I915_WRITE(DEIER, de_ier);
1021         POSTING_READ(DEIER);
1022         I915_WRITE(SDEIER, sde_ier);
1023         POSTING_READ(SDEIER);
1024
1025         return ret;
1026 }
1027
1028 /**
1029  * i915_error_work_func - do process context error handling work
1030  * @work: work struct
1031  *
1032  * Fire an error uevent so userspace can see that a hang or error
1033  * was detected.
1034  */
1035 static void i915_error_work_func(struct work_struct *work)
1036 {
1037         struct i915_gpu_error *error = container_of(work, struct i915_gpu_error,
1038                                                     work);
1039         drm_i915_private_t *dev_priv = container_of(error, drm_i915_private_t,
1040                                                     gpu_error);
1041         struct drm_device *dev = dev_priv->dev;
1042         struct intel_ring_buffer *ring;
1043         char *error_event[] = { "ERROR=1", NULL };
1044         char *reset_event[] = { "RESET=1", NULL };
1045         char *reset_done_event[] = { "ERROR=0", NULL };
1046         int i, ret;
1047
1048         kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE, error_event);
1049
1050         /*
1051          * Note that there's only one work item which does gpu resets, so we
1052          * need not worry about concurrent gpu resets potentially incrementing
1053          * error->reset_counter twice. We only need to take care of another
1054          * racing irq/hangcheck declaring the gpu dead for a second time. A
1055          * quick check for that is good enough: schedule_work ensures the
1056          * correct ordering between hang detection and this work item, and since
1057          * the reset in-progress bit is only ever set by code outside of this
1058          * work we don't need to worry about any other races.
1059          */
1060         if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
1061                 DRM_DEBUG_DRIVER("resetting chip\n");
1062                 kobject_uevent_env(&dev->primary->kdev.kobj, KOBJ_CHANGE,
1063                                    reset_event);
1064
1065                 ret = i915_reset(dev);
1066
1067                 if (ret == 0) {
1068                         /*
1069                          * After all the gem state is reset, increment the reset
1070                          * counter and wake up everyone waiting for the reset to
1071                          * complete.
1072                          *
1073                          * Since unlock operations are a one-sided barrier only,
1074                          * we need to insert a barrier here to order any seqno
1075                          * updates before
1076                          * the counter increment.
1077                          */
1078                         smp_mb__before_atomic_inc();
1079                         atomic_inc(&dev_priv->gpu_error.reset_counter);
1080
1081                         kobject_uevent_env(&dev->primary->kdev.kobj,
1082                                            KOBJ_CHANGE, reset_done_event);
1083                 } else {
1084                         atomic_set(&error->reset_counter, I915_WEDGED);
1085                 }
1086
1087                 for_each_ring(ring, dev_priv, i)
1088                         wake_up_all(&ring->irq_queue);
1089
1090                 intel_display_handle_reset(dev);
1091
1092                 wake_up_all(&dev_priv->gpu_error.reset_queue);
1093         }
1094 }
1095
1096 /* NB: please notice the memset */
1097 static void i915_get_extra_instdone(struct drm_device *dev,
1098                                     uint32_t *instdone)
1099 {
1100         struct drm_i915_private *dev_priv = dev->dev_private;
1101         memset(instdone, 0, sizeof(*instdone) * I915_NUM_INSTDONE_REG);
1102
1103         switch(INTEL_INFO(dev)->gen) {
1104         case 2:
1105         case 3:
1106                 instdone[0] = I915_READ(INSTDONE);
1107                 break;
1108         case 4:
1109         case 5:
1110         case 6:
1111                 instdone[0] = I915_READ(INSTDONE_I965);
1112                 instdone[1] = I915_READ(INSTDONE1);
1113                 break;
1114         default:
1115                 WARN_ONCE(1, "Unsupported platform\n");
1116         case 7:
1117                 instdone[0] = I915_READ(GEN7_INSTDONE_1);
1118                 instdone[1] = I915_READ(GEN7_SC_INSTDONE);
1119                 instdone[2] = I915_READ(GEN7_SAMPLER_INSTDONE);
1120                 instdone[3] = I915_READ(GEN7_ROW_INSTDONE);
1121                 break;
1122         }
1123 }
1124
1125 #ifdef CONFIG_DEBUG_FS
1126 static struct drm_i915_error_object *
1127 i915_error_object_create_sized(struct drm_i915_private *dev_priv,
1128                                struct drm_i915_gem_object *src,
1129                                const int num_pages)
1130 {
1131         struct drm_i915_error_object *dst;
1132         int i;
1133         u32 reloc_offset;
1134
1135         if (src == NULL || src->pages == NULL)
1136                 return NULL;
1137
1138         dst = kmalloc(sizeof(*dst) + num_pages * sizeof(u32 *), GFP_ATOMIC);
1139         if (dst == NULL)
1140                 return NULL;
1141
1142         reloc_offset = src->gtt_offset;
1143         for (i = 0; i < num_pages; i++) {
1144                 unsigned long flags;
1145                 void *d;
1146
1147                 d = kmalloc(PAGE_SIZE, GFP_ATOMIC);
1148                 if (d == NULL)
1149                         goto unwind;
1150
1151                 local_irq_save(flags);
1152                 if (reloc_offset < dev_priv->gtt.mappable_end &&
1153                     src->has_global_gtt_mapping) {
1154                         void __iomem *s;
1155
1156                         /* Simply ignore tiling or any overlapping fence.
1157                          * It's part of the error state, and this hopefully
1158                          * captures what the GPU read.
1159                          */
1160
1161                         s = io_mapping_map_atomic_wc(dev_priv->gtt.mappable,
1162                                                      reloc_offset);
1163                         memcpy_fromio(d, s, PAGE_SIZE);
1164                         io_mapping_unmap_atomic(s);
1165                 } else if (src->stolen) {
1166                         unsigned long offset;
1167
1168                         offset = dev_priv->mm.stolen_base;
1169                         offset += src->stolen->start;
1170                         offset += i << PAGE_SHIFT;
1171
1172                         memcpy_fromio(d, (void __iomem *) offset, PAGE_SIZE);
1173                 } else {
1174                         struct page *page;
1175                         void *s;
1176
1177                         page = i915_gem_object_get_page(src, i);
1178
1179                         drm_clflush_pages(&page, 1);
1180
1181                         s = kmap_atomic(page);
1182                         memcpy(d, s, PAGE_SIZE);
1183                         kunmap_atomic(s);
1184
1185                         drm_clflush_pages(&page, 1);
1186                 }
1187                 local_irq_restore(flags);
1188
1189                 dst->pages[i] = d;
1190
1191                 reloc_offset += PAGE_SIZE;
1192         }
1193         dst->page_count = num_pages;
1194         dst->gtt_offset = src->gtt_offset;
1195
1196         return dst;
1197
1198 unwind:
1199         while (i--)
1200                 kfree(dst->pages[i]);
1201         kfree(dst);
1202         return NULL;
1203 }
1204 #define i915_error_object_create(dev_priv, src) \
1205         i915_error_object_create_sized((dev_priv), (src), \
1206                                        (src)->base.size>>PAGE_SHIFT)
1207
1208 static void
1209 i915_error_object_free(struct drm_i915_error_object *obj)
1210 {
1211         int page;
1212
1213         if (obj == NULL)
1214                 return;
1215
1216         for (page = 0; page < obj->page_count; page++)
1217                 kfree(obj->pages[page]);
1218
1219         kfree(obj);
1220 }
1221
1222 void
1223 i915_error_state_free(struct kref *error_ref)
1224 {
1225         struct drm_i915_error_state *error = container_of(error_ref,
1226                                                           typeof(*error), ref);
1227         int i;
1228
1229         for (i = 0; i < ARRAY_SIZE(error->ring); i++) {
1230                 i915_error_object_free(error->ring[i].batchbuffer);
1231                 i915_error_object_free(error->ring[i].ringbuffer);
1232                 kfree(error->ring[i].requests);
1233         }
1234
1235         kfree(error->active_bo);
1236         kfree(error->overlay);
1237         kfree(error);
1238 }
1239 static void capture_bo(struct drm_i915_error_buffer *err,
1240                        struct drm_i915_gem_object *obj)
1241 {
1242         err->size = obj->base.size;
1243         err->name = obj->base.name;
1244         err->rseqno = obj->last_read_seqno;
1245         err->wseqno = obj->last_write_seqno;
1246         err->gtt_offset = obj->gtt_offset;
1247         err->read_domains = obj->base.read_domains;
1248         err->write_domain = obj->base.write_domain;
1249         err->fence_reg = obj->fence_reg;
1250         err->pinned = 0;
1251         if (obj->pin_count > 0)
1252                 err->pinned = 1;
1253         if (obj->user_pin_count > 0)
1254                 err->pinned = -1;
1255         err->tiling = obj->tiling_mode;
1256         err->dirty = obj->dirty;
1257         err->purgeable = obj->madv != I915_MADV_WILLNEED;
1258         err->ring = obj->ring ? obj->ring->id : -1;
1259         err->cache_level = obj->cache_level;
1260 }
1261
1262 static u32 capture_active_bo(struct drm_i915_error_buffer *err,
1263                              int count, struct list_head *head)
1264 {
1265         struct drm_i915_gem_object *obj;
1266         int i = 0;
1267
1268         list_for_each_entry(obj, head, mm_list) {
1269                 capture_bo(err++, obj);
1270                 if (++i == count)
1271                         break;
1272         }
1273
1274         return i;
1275 }
1276
1277 static u32 capture_pinned_bo(struct drm_i915_error_buffer *err,
1278                              int count, struct list_head *head)
1279 {
1280         struct drm_i915_gem_object *obj;
1281         int i = 0;
1282
1283         list_for_each_entry(obj, head, gtt_list) {
1284                 if (obj->pin_count == 0)
1285                         continue;
1286
1287                 capture_bo(err++, obj);
1288                 if (++i == count)
1289                         break;
1290         }
1291
1292         return i;
1293 }
1294
1295 static void i915_gem_record_fences(struct drm_device *dev,
1296                                    struct drm_i915_error_state *error)
1297 {
1298         struct drm_i915_private *dev_priv = dev->dev_private;
1299         int i;
1300
1301         /* Fences */
1302         switch (INTEL_INFO(dev)->gen) {
1303         case 7:
1304         case 6:
1305                 for (i = 0; i < dev_priv->num_fence_regs; i++)
1306                         error->fence[i] = I915_READ64(FENCE_REG_SANDYBRIDGE_0 + (i * 8));
1307                 break;
1308         case 5:
1309         case 4:
1310                 for (i = 0; i < 16; i++)
1311                         error->fence[i] = I915_READ64(FENCE_REG_965_0 + (i * 8));
1312                 break;
1313         case 3:
1314                 if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
1315                         for (i = 0; i < 8; i++)
1316                                 error->fence[i+8] = I915_READ(FENCE_REG_945_8 + (i * 4));
1317         case 2:
1318                 for (i = 0; i < 8; i++)
1319                         error->fence[i] = I915_READ(FENCE_REG_830_0 + (i * 4));
1320                 break;
1321
1322         default:
1323                 BUG();
1324         }
1325 }
1326
1327 static struct drm_i915_error_object *
1328 i915_error_first_batchbuffer(struct drm_i915_private *dev_priv,
1329                              struct intel_ring_buffer *ring)
1330 {
1331         struct drm_i915_gem_object *obj;
1332         u32 seqno;
1333
1334         if (!ring->get_seqno)
1335                 return NULL;
1336
1337         if (HAS_BROKEN_CS_TLB(dev_priv->dev)) {
1338                 u32 acthd = I915_READ(ACTHD);
1339
1340                 if (WARN_ON(ring->id != RCS))
1341                         return NULL;
1342
1343                 obj = ring->private;
1344                 if (acthd >= obj->gtt_offset &&
1345                     acthd < obj->gtt_offset + obj->base.size)
1346                         return i915_error_object_create(dev_priv, obj);
1347         }
1348
1349         seqno = ring->get_seqno(ring, false);
1350         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list) {
1351                 if (obj->ring != ring)
1352                         continue;
1353
1354                 if (i915_seqno_passed(seqno, obj->last_read_seqno))
1355                         continue;
1356
1357                 if ((obj->base.read_domains & I915_GEM_DOMAIN_COMMAND) == 0)
1358                         continue;
1359
1360                 /* We need to copy these to an anonymous buffer as the simplest
1361                  * method to avoid being overwritten by userspace.
1362                  */
1363                 return i915_error_object_create(dev_priv, obj);
1364         }
1365
1366         return NULL;
1367 }
1368
1369 static void i915_record_ring_state(struct drm_device *dev,
1370                                    struct drm_i915_error_state *error,
1371                                    struct intel_ring_buffer *ring)
1372 {
1373         struct drm_i915_private *dev_priv = dev->dev_private;
1374
1375         if (INTEL_INFO(dev)->gen >= 6) {
1376                 error->rc_psmi[ring->id] = I915_READ(ring->mmio_base + 0x50);
1377                 error->fault_reg[ring->id] = I915_READ(RING_FAULT_REG(ring));
1378                 error->semaphore_mboxes[ring->id][0]
1379                         = I915_READ(RING_SYNC_0(ring->mmio_base));
1380                 error->semaphore_mboxes[ring->id][1]
1381                         = I915_READ(RING_SYNC_1(ring->mmio_base));
1382                 error->semaphore_seqno[ring->id][0] = ring->sync_seqno[0];
1383                 error->semaphore_seqno[ring->id][1] = ring->sync_seqno[1];
1384         }
1385
1386         if (INTEL_INFO(dev)->gen >= 4) {
1387                 error->faddr[ring->id] = I915_READ(RING_DMA_FADD(ring->mmio_base));
1388                 error->ipeir[ring->id] = I915_READ(RING_IPEIR(ring->mmio_base));
1389                 error->ipehr[ring->id] = I915_READ(RING_IPEHR(ring->mmio_base));
1390                 error->instdone[ring->id] = I915_READ(RING_INSTDONE(ring->mmio_base));
1391                 error->instps[ring->id] = I915_READ(RING_INSTPS(ring->mmio_base));
1392                 if (ring->id == RCS)
1393                         error->bbaddr = I915_READ64(BB_ADDR);
1394         } else {
1395                 error->faddr[ring->id] = I915_READ(DMA_FADD_I8XX);
1396                 error->ipeir[ring->id] = I915_READ(IPEIR);
1397                 error->ipehr[ring->id] = I915_READ(IPEHR);
1398                 error->instdone[ring->id] = I915_READ(INSTDONE);
1399         }
1400
1401         error->waiting[ring->id] = waitqueue_active(&ring->irq_queue);
1402         error->instpm[ring->id] = I915_READ(RING_INSTPM(ring->mmio_base));
1403         error->seqno[ring->id] = ring->get_seqno(ring, false);
1404         error->acthd[ring->id] = intel_ring_get_active_head(ring);
1405         error->head[ring->id] = I915_READ_HEAD(ring);
1406         error->tail[ring->id] = I915_READ_TAIL(ring);
1407         error->ctl[ring->id] = I915_READ_CTL(ring);
1408
1409         error->cpu_ring_head[ring->id] = ring->head;
1410         error->cpu_ring_tail[ring->id] = ring->tail;
1411 }
1412
1413
1414 static void i915_gem_record_active_context(struct intel_ring_buffer *ring,
1415                                            struct drm_i915_error_state *error,
1416                                            struct drm_i915_error_ring *ering)
1417 {
1418         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1419         struct drm_i915_gem_object *obj;
1420
1421         /* Currently render ring is the only HW context user */
1422         if (ring->id != RCS || !error->ccid)
1423                 return;
1424
1425         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list) {
1426                 if ((error->ccid & PAGE_MASK) == obj->gtt_offset) {
1427                         ering->ctx = i915_error_object_create_sized(dev_priv,
1428                                                                     obj, 1);
1429                 }
1430         }
1431 }
1432
1433 static void i915_gem_record_rings(struct drm_device *dev,
1434                                   struct drm_i915_error_state *error)
1435 {
1436         struct drm_i915_private *dev_priv = dev->dev_private;
1437         struct intel_ring_buffer *ring;
1438         struct drm_i915_gem_request *request;
1439         int i, count;
1440
1441         for_each_ring(ring, dev_priv, i) {
1442                 i915_record_ring_state(dev, error, ring);
1443
1444                 error->ring[i].batchbuffer =
1445                         i915_error_first_batchbuffer(dev_priv, ring);
1446
1447                 error->ring[i].ringbuffer =
1448                         i915_error_object_create(dev_priv, ring->obj);
1449
1450
1451                 i915_gem_record_active_context(ring, error, &error->ring[i]);
1452
1453                 count = 0;
1454                 list_for_each_entry(request, &ring->request_list, list)
1455                         count++;
1456
1457                 error->ring[i].num_requests = count;
1458                 error->ring[i].requests =
1459                         kmalloc(count*sizeof(struct drm_i915_error_request),
1460                                 GFP_ATOMIC);
1461                 if (error->ring[i].requests == NULL) {
1462                         error->ring[i].num_requests = 0;
1463                         continue;
1464                 }
1465
1466                 count = 0;
1467                 list_for_each_entry(request, &ring->request_list, list) {
1468                         struct drm_i915_error_request *erq;
1469
1470                         erq = &error->ring[i].requests[count++];
1471                         erq->seqno = request->seqno;
1472                         erq->jiffies = request->emitted_jiffies;
1473                         erq->tail = request->tail;
1474                 }
1475         }
1476 }
1477
1478 /**
1479  * i915_capture_error_state - capture an error record for later analysis
1480  * @dev: drm device
1481  *
1482  * Should be called when an error is detected (either a hang or an error
1483  * interrupt) to capture error state from the time of the error.  Fills
1484  * out a structure which becomes available in debugfs for user level tools
1485  * to pick up.
1486  */
1487 static void i915_capture_error_state(struct drm_device *dev)
1488 {
1489         struct drm_i915_private *dev_priv = dev->dev_private;
1490         struct drm_i915_gem_object *obj;
1491         struct drm_i915_error_state *error;
1492         unsigned long flags;
1493         int i, pipe;
1494
1495         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1496         error = dev_priv->gpu_error.first_error;
1497         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1498         if (error)
1499                 return;
1500
1501         /* Account for pipe specific data like PIPE*STAT */
1502         error = kzalloc(sizeof(*error), GFP_ATOMIC);
1503         if (!error) {
1504                 DRM_DEBUG_DRIVER("out of memory, not capturing error state\n");
1505                 return;
1506         }
1507
1508         DRM_INFO("capturing error event; look for more information in "
1509                  "/sys/kernel/debug/dri/%d/i915_error_state\n",
1510                  dev->primary->index);
1511
1512         kref_init(&error->ref);
1513         error->eir = I915_READ(EIR);
1514         error->pgtbl_er = I915_READ(PGTBL_ER);
1515         if (HAS_HW_CONTEXTS(dev))
1516                 error->ccid = I915_READ(CCID);
1517
1518         if (HAS_PCH_SPLIT(dev))
1519                 error->ier = I915_READ(DEIER) | I915_READ(GTIER);
1520         else if (IS_VALLEYVIEW(dev))
1521                 error->ier = I915_READ(GTIER) | I915_READ(VLV_IER);
1522         else if (IS_GEN2(dev))
1523                 error->ier = I915_READ16(IER);
1524         else
1525                 error->ier = I915_READ(IER);
1526
1527         if (INTEL_INFO(dev)->gen >= 6)
1528                 error->derrmr = I915_READ(DERRMR);
1529
1530         if (IS_VALLEYVIEW(dev))
1531                 error->forcewake = I915_READ(FORCEWAKE_VLV);
1532         else if (INTEL_INFO(dev)->gen >= 7)
1533                 error->forcewake = I915_READ(FORCEWAKE_MT);
1534         else if (INTEL_INFO(dev)->gen == 6)
1535                 error->forcewake = I915_READ(FORCEWAKE);
1536
1537         if (!HAS_PCH_SPLIT(dev))
1538                 for_each_pipe(pipe)
1539                         error->pipestat[pipe] = I915_READ(PIPESTAT(pipe));
1540
1541         if (INTEL_INFO(dev)->gen >= 6) {
1542                 error->error = I915_READ(ERROR_GEN6);
1543                 error->done_reg = I915_READ(DONE_REG);
1544         }
1545
1546         if (INTEL_INFO(dev)->gen == 7)
1547                 error->err_int = I915_READ(GEN7_ERR_INT);
1548
1549         i915_get_extra_instdone(dev, error->extra_instdone);
1550
1551         i915_gem_record_fences(dev, error);
1552         i915_gem_record_rings(dev, error);
1553
1554         /* Record buffers on the active and pinned lists. */
1555         error->active_bo = NULL;
1556         error->pinned_bo = NULL;
1557
1558         i = 0;
1559         list_for_each_entry(obj, &dev_priv->mm.active_list, mm_list)
1560                 i++;
1561         error->active_bo_count = i;
1562         list_for_each_entry(obj, &dev_priv->mm.bound_list, gtt_list)
1563                 if (obj->pin_count)
1564                         i++;
1565         error->pinned_bo_count = i - error->active_bo_count;
1566
1567         error->active_bo = NULL;
1568         error->pinned_bo = NULL;
1569         if (i) {
1570                 error->active_bo = kmalloc(sizeof(*error->active_bo)*i,
1571                                            GFP_ATOMIC);
1572                 if (error->active_bo)
1573                         error->pinned_bo =
1574                                 error->active_bo + error->active_bo_count;
1575         }
1576
1577         if (error->active_bo)
1578                 error->active_bo_count =
1579                         capture_active_bo(error->active_bo,
1580                                           error->active_bo_count,
1581                                           &dev_priv->mm.active_list);
1582
1583         if (error->pinned_bo)
1584                 error->pinned_bo_count =
1585                         capture_pinned_bo(error->pinned_bo,
1586                                           error->pinned_bo_count,
1587                                           &dev_priv->mm.bound_list);
1588
1589         do_gettimeofday(&error->time);
1590
1591         error->overlay = intel_overlay_capture_error_state(dev);
1592         error->display = intel_display_capture_error_state(dev);
1593
1594         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1595         if (dev_priv->gpu_error.first_error == NULL) {
1596                 dev_priv->gpu_error.first_error = error;
1597                 error = NULL;
1598         }
1599         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1600
1601         if (error)
1602                 i915_error_state_free(&error->ref);
1603 }
1604
1605 void i915_destroy_error_state(struct drm_device *dev)
1606 {
1607         struct drm_i915_private *dev_priv = dev->dev_private;
1608         struct drm_i915_error_state *error;
1609         unsigned long flags;
1610
1611         spin_lock_irqsave(&dev_priv->gpu_error.lock, flags);
1612         error = dev_priv->gpu_error.first_error;
1613         dev_priv->gpu_error.first_error = NULL;
1614         spin_unlock_irqrestore(&dev_priv->gpu_error.lock, flags);
1615
1616         if (error)
1617                 kref_put(&error->ref, i915_error_state_free);
1618 }
1619 #else
1620 #define i915_capture_error_state(x)
1621 #endif
1622
1623 static void i915_report_and_clear_eir(struct drm_device *dev)
1624 {
1625         struct drm_i915_private *dev_priv = dev->dev_private;
1626         uint32_t instdone[I915_NUM_INSTDONE_REG];
1627         u32 eir = I915_READ(EIR);
1628         int pipe, i;
1629
1630         if (!eir)
1631                 return;
1632
1633         pr_err("render error detected, EIR: 0x%08x\n", eir);
1634
1635         i915_get_extra_instdone(dev, instdone);
1636
1637         if (IS_G4X(dev)) {
1638                 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
1639                         u32 ipeir = I915_READ(IPEIR_I965);
1640
1641                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1642                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1643                         for (i = 0; i < ARRAY_SIZE(instdone); i++)
1644                                 pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1645                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1646                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1647                         I915_WRITE(IPEIR_I965, ipeir);
1648                         POSTING_READ(IPEIR_I965);
1649                 }
1650                 if (eir & GM45_ERROR_PAGE_TABLE) {
1651                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1652                         pr_err("page table error\n");
1653                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1654                         I915_WRITE(PGTBL_ER, pgtbl_err);
1655                         POSTING_READ(PGTBL_ER);
1656                 }
1657         }
1658
1659         if (!IS_GEN2(dev)) {
1660                 if (eir & I915_ERROR_PAGE_TABLE) {
1661                         u32 pgtbl_err = I915_READ(PGTBL_ER);
1662                         pr_err("page table error\n");
1663                         pr_err("  PGTBL_ER: 0x%08x\n", pgtbl_err);
1664                         I915_WRITE(PGTBL_ER, pgtbl_err);
1665                         POSTING_READ(PGTBL_ER);
1666                 }
1667         }
1668
1669         if (eir & I915_ERROR_MEMORY_REFRESH) {
1670                 pr_err("memory refresh error:\n");
1671                 for_each_pipe(pipe)
1672                         pr_err("pipe %c stat: 0x%08x\n",
1673                                pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
1674                 /* pipestat has already been acked */
1675         }
1676         if (eir & I915_ERROR_INSTRUCTION) {
1677                 pr_err("instruction error\n");
1678                 pr_err("  INSTPM: 0x%08x\n", I915_READ(INSTPM));
1679                 for (i = 0; i < ARRAY_SIZE(instdone); i++)
1680                         pr_err("  INSTDONE_%d: 0x%08x\n", i, instdone[i]);
1681                 if (INTEL_INFO(dev)->gen < 4) {
1682                         u32 ipeir = I915_READ(IPEIR);
1683
1684                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR));
1685                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR));
1686                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD));
1687                         I915_WRITE(IPEIR, ipeir);
1688                         POSTING_READ(IPEIR);
1689                 } else {
1690                         u32 ipeir = I915_READ(IPEIR_I965);
1691
1692                         pr_err("  IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
1693                         pr_err("  IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
1694                         pr_err("  INSTPS: 0x%08x\n", I915_READ(INSTPS));
1695                         pr_err("  ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
1696                         I915_WRITE(IPEIR_I965, ipeir);
1697                         POSTING_READ(IPEIR_I965);
1698                 }
1699         }
1700
1701         I915_WRITE(EIR, eir);
1702         POSTING_READ(EIR);
1703         eir = I915_READ(EIR);
1704         if (eir) {
1705                 /*
1706                  * some errors might have become stuck,
1707                  * mask them.
1708                  */
1709                 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
1710                 I915_WRITE(EMR, I915_READ(EMR) | eir);
1711                 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
1712         }
1713 }
1714
1715 /**
1716  * i915_handle_error - handle an error interrupt
1717  * @dev: drm device
1718  *
1719  * Do some basic checking of regsiter state at error interrupt time and
1720  * dump it to the syslog.  Also call i915_capture_error_state() to make
1721  * sure we get a record and make it available in debugfs.  Fire a uevent
1722  * so userspace knows something bad happened (should trigger collection
1723  * of a ring dump etc.).
1724  */
1725 void i915_handle_error(struct drm_device *dev, bool wedged)
1726 {
1727         struct drm_i915_private *dev_priv = dev->dev_private;
1728         struct intel_ring_buffer *ring;
1729         int i;
1730
1731         i915_capture_error_state(dev);
1732         i915_report_and_clear_eir(dev);
1733
1734         if (wedged) {
1735                 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
1736                                 &dev_priv->gpu_error.reset_counter);
1737
1738                 /*
1739                  * Wakeup waiting processes so that the reset work item
1740                  * doesn't deadlock trying to grab various locks.
1741                  */
1742                 for_each_ring(ring, dev_priv, i)
1743                         wake_up_all(&ring->irq_queue);
1744         }
1745
1746         queue_work(dev_priv->wq, &dev_priv->gpu_error.work);
1747 }
1748
1749 static void __always_unused i915_pageflip_stall_check(struct drm_device *dev, int pipe)
1750 {
1751         drm_i915_private_t *dev_priv = dev->dev_private;
1752         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1753         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1754         struct drm_i915_gem_object *obj;
1755         struct intel_unpin_work *work;
1756         unsigned long flags;
1757         bool stall_detected;
1758
1759         /* Ignore early vblank irqs */
1760         if (intel_crtc == NULL)
1761                 return;
1762
1763         spin_lock_irqsave(&dev->event_lock, flags);
1764         work = intel_crtc->unpin_work;
1765
1766         if (work == NULL ||
1767             atomic_read(&work->pending) >= INTEL_FLIP_COMPLETE ||
1768             !work->enable_stall_check) {
1769                 /* Either the pending flip IRQ arrived, or we're too early. Don't check */
1770                 spin_unlock_irqrestore(&dev->event_lock, flags);
1771                 return;
1772         }
1773
1774         /* Potential stall - if we see that the flip has happened, assume a missed interrupt */
1775         obj = work->pending_flip_obj;
1776         if (INTEL_INFO(dev)->gen >= 4) {
1777                 int dspsurf = DSPSURF(intel_crtc->plane);
1778                 stall_detected = I915_HI_DISPBASE(I915_READ(dspsurf)) ==
1779                                         obj->gtt_offset;
1780         } else {
1781                 int dspaddr = DSPADDR(intel_crtc->plane);
1782                 stall_detected = I915_READ(dspaddr) == (obj->gtt_offset +
1783                                                         crtc->y * crtc->fb->pitches[0] +
1784                                                         crtc->x * crtc->fb->bits_per_pixel/8);
1785         }
1786
1787         spin_unlock_irqrestore(&dev->event_lock, flags);
1788
1789         if (stall_detected) {
1790                 DRM_DEBUG_DRIVER("Pageflip stall detected\n");
1791                 intel_prepare_page_flip(dev, intel_crtc->plane);
1792         }
1793 }
1794
1795 /* Called from drm generic code, passed 'crtc' which
1796  * we use as a pipe index
1797  */
1798 static int i915_enable_vblank(struct drm_device *dev, int pipe)
1799 {
1800         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1801         unsigned long irqflags;
1802
1803         if (!i915_pipe_enabled(dev, pipe))
1804                 return -EINVAL;
1805
1806         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1807         if (INTEL_INFO(dev)->gen >= 4)
1808                 i915_enable_pipestat(dev_priv, pipe,
1809                                      PIPE_START_VBLANK_INTERRUPT_ENABLE);
1810         else
1811                 i915_enable_pipestat(dev_priv, pipe,
1812                                      PIPE_VBLANK_INTERRUPT_ENABLE);
1813
1814         /* maintain vblank delivery even in deep C-states */
1815         if (dev_priv->info->gen == 3)
1816                 I915_WRITE(INSTPM, _MASKED_BIT_DISABLE(INSTPM_AGPBUSY_DIS));
1817         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1818
1819         return 0;
1820 }
1821
1822 static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
1823 {
1824         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1825         unsigned long irqflags;
1826
1827         if (!i915_pipe_enabled(dev, pipe))
1828                 return -EINVAL;
1829
1830         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1831         ironlake_enable_display_irq(dev_priv, (pipe == 0) ?
1832                                     DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1833         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1834
1835         return 0;
1836 }
1837
1838 static int ivybridge_enable_vblank(struct drm_device *dev, int pipe)
1839 {
1840         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1841         unsigned long irqflags;
1842
1843         if (!i915_pipe_enabled(dev, pipe))
1844                 return -EINVAL;
1845
1846         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1847         ironlake_enable_display_irq(dev_priv,
1848                                     DE_PIPEA_VBLANK_IVB << (5 * pipe));
1849         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1850
1851         return 0;
1852 }
1853
1854 static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
1855 {
1856         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1857         unsigned long irqflags;
1858         u32 imr;
1859
1860         if (!i915_pipe_enabled(dev, pipe))
1861                 return -EINVAL;
1862
1863         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1864         imr = I915_READ(VLV_IMR);
1865         if (pipe == 0)
1866                 imr &= ~I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1867         else
1868                 imr &= ~I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1869         I915_WRITE(VLV_IMR, imr);
1870         i915_enable_pipestat(dev_priv, pipe,
1871                              PIPE_START_VBLANK_INTERRUPT_ENABLE);
1872         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1873
1874         return 0;
1875 }
1876
1877 /* Called from drm generic code, passed 'crtc' which
1878  * we use as a pipe index
1879  */
1880 static void i915_disable_vblank(struct drm_device *dev, int pipe)
1881 {
1882         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1883         unsigned long irqflags;
1884
1885         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1886         if (dev_priv->info->gen == 3)
1887                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_DIS));
1888
1889         i915_disable_pipestat(dev_priv, pipe,
1890                               PIPE_VBLANK_INTERRUPT_ENABLE |
1891                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1892         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1893 }
1894
1895 static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
1896 {
1897         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1898         unsigned long irqflags;
1899
1900         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1901         ironlake_disable_display_irq(dev_priv, (pipe == 0) ?
1902                                      DE_PIPEA_VBLANK : DE_PIPEB_VBLANK);
1903         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1904 }
1905
1906 static void ivybridge_disable_vblank(struct drm_device *dev, int pipe)
1907 {
1908         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1909         unsigned long irqflags;
1910
1911         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1912         ironlake_disable_display_irq(dev_priv,
1913                                      DE_PIPEA_VBLANK_IVB << (pipe * 5));
1914         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1915 }
1916
1917 static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
1918 {
1919         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
1920         unsigned long irqflags;
1921         u32 imr;
1922
1923         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
1924         i915_disable_pipestat(dev_priv, pipe,
1925                               PIPE_START_VBLANK_INTERRUPT_ENABLE);
1926         imr = I915_READ(VLV_IMR);
1927         if (pipe == 0)
1928                 imr |= I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT;
1929         else
1930                 imr |= I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
1931         I915_WRITE(VLV_IMR, imr);
1932         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
1933 }
1934
1935 static u32
1936 ring_last_seqno(struct intel_ring_buffer *ring)
1937 {
1938         return list_entry(ring->request_list.prev,
1939                           struct drm_i915_gem_request, list)->seqno;
1940 }
1941
1942 static bool i915_hangcheck_ring_idle(struct intel_ring_buffer *ring, bool *err)
1943 {
1944         if (list_empty(&ring->request_list) ||
1945             i915_seqno_passed(ring->get_seqno(ring, false),
1946                               ring_last_seqno(ring))) {
1947                 /* Issue a wake-up to catch stuck h/w. */
1948                 if (waitqueue_active(&ring->irq_queue)) {
1949                         DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
1950                                   ring->name);
1951                         wake_up_all(&ring->irq_queue);
1952                         *err = true;
1953                 }
1954                 return true;
1955         }
1956         return false;
1957 }
1958
1959 static bool semaphore_passed(struct intel_ring_buffer *ring)
1960 {
1961         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1962         u32 acthd = intel_ring_get_active_head(ring) & HEAD_ADDR;
1963         struct intel_ring_buffer *signaller;
1964         u32 cmd, ipehr, acthd_min;
1965
1966         ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
1967         if ((ipehr & ~(0x3 << 16)) !=
1968             (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE | MI_SEMAPHORE_REGISTER))
1969                 return false;
1970
1971         /* ACTHD is likely pointing to the dword after the actual command,
1972          * so scan backwards until we find the MBOX.
1973          */
1974         acthd_min = max((int)acthd - 3 * 4, 0);
1975         do {
1976                 cmd = ioread32(ring->virtual_start + acthd);
1977                 if (cmd == ipehr)
1978                         break;
1979
1980                 acthd -= 4;
1981                 if (acthd < acthd_min)
1982                         return false;
1983         } while (1);
1984
1985         signaller = &dev_priv->ring[(ring->id + (((ipehr >> 17) & 1) + 1)) % 3];
1986         return i915_seqno_passed(signaller->get_seqno(signaller, false),
1987                                  ioread32(ring->virtual_start+acthd+4)+1);
1988 }
1989
1990 static bool kick_ring(struct intel_ring_buffer *ring)
1991 {
1992         struct drm_device *dev = ring->dev;
1993         struct drm_i915_private *dev_priv = dev->dev_private;
1994         u32 tmp = I915_READ_CTL(ring);
1995         if (tmp & RING_WAIT) {
1996                 DRM_ERROR("Kicking stuck wait on %s\n",
1997                           ring->name);
1998                 I915_WRITE_CTL(ring, tmp);
1999                 return true;
2000         }
2001
2002         if (INTEL_INFO(dev)->gen >= 6 &&
2003             tmp & RING_WAIT_SEMAPHORE &&
2004             semaphore_passed(ring)) {
2005                 DRM_ERROR("Kicking stuck semaphore on %s\n",
2006                           ring->name);
2007                 I915_WRITE_CTL(ring, tmp);
2008                 return true;
2009         }
2010         return false;
2011 }
2012
2013 static bool i915_hangcheck_hung(struct drm_device *dev)
2014 {
2015         drm_i915_private_t *dev_priv = dev->dev_private;
2016
2017         if (dev_priv->gpu_error.hangcheck_count++ > 1) {
2018                 bool hung = true;
2019
2020                 DRM_ERROR("Hangcheck timer elapsed... GPU hung\n");
2021                 i915_handle_error(dev, true);
2022
2023                 if (!IS_GEN2(dev)) {
2024                         struct intel_ring_buffer *ring;
2025                         int i;
2026
2027                         /* Is the chip hanging on a WAIT_FOR_EVENT?
2028                          * If so we can simply poke the RB_WAIT bit
2029                          * and break the hang. This should work on
2030                          * all but the second generation chipsets.
2031                          */
2032                         for_each_ring(ring, dev_priv, i)
2033                                 hung &= !kick_ring(ring);
2034                 }
2035
2036                 return hung;
2037         }
2038
2039         return false;
2040 }
2041
2042 /**
2043  * This is called when the chip hasn't reported back with completed
2044  * batchbuffers in a long time. The first time this is called we simply record
2045  * ACTHD. If ACTHD hasn't changed by the time the hangcheck timer elapses
2046  * again, we assume the chip is wedged and try to fix it.
2047  */
2048 void i915_hangcheck_elapsed(unsigned long data)
2049 {
2050         struct drm_device *dev = (struct drm_device *)data;
2051         drm_i915_private_t *dev_priv = dev->dev_private;
2052         uint32_t acthd[I915_NUM_RINGS], instdone[I915_NUM_INSTDONE_REG];
2053         struct intel_ring_buffer *ring;
2054         bool err = false, idle;
2055         int i;
2056
2057         if (!i915_enable_hangcheck)
2058                 return;
2059
2060         memset(acthd, 0, sizeof(acthd));
2061         idle = true;
2062         for_each_ring(ring, dev_priv, i) {
2063             idle &= i915_hangcheck_ring_idle(ring, &err);
2064             acthd[i] = intel_ring_get_active_head(ring);
2065         }
2066
2067         /* If all work is done then ACTHD clearly hasn't advanced. */
2068         if (idle) {
2069                 if (err) {
2070                         if (i915_hangcheck_hung(dev))
2071                                 return;
2072
2073                         goto repeat;
2074                 }
2075
2076                 dev_priv->gpu_error.hangcheck_count = 0;
2077                 return;
2078         }
2079
2080         i915_get_extra_instdone(dev, instdone);
2081         if (memcmp(dev_priv->gpu_error.last_acthd, acthd,
2082                    sizeof(acthd)) == 0 &&
2083             memcmp(dev_priv->gpu_error.prev_instdone, instdone,
2084                    sizeof(instdone)) == 0) {
2085                 if (i915_hangcheck_hung(dev))
2086                         return;
2087         } else {
2088                 dev_priv->gpu_error.hangcheck_count = 0;
2089
2090                 memcpy(dev_priv->gpu_error.last_acthd, acthd,
2091                        sizeof(acthd));
2092                 memcpy(dev_priv->gpu_error.prev_instdone, instdone,
2093                        sizeof(instdone));
2094         }
2095
2096 repeat:
2097         /* Reset timer case chip hangs without another request being added */
2098         mod_timer(&dev_priv->gpu_error.hangcheck_timer,
2099                   round_jiffies_up(jiffies + DRM_I915_HANGCHECK_JIFFIES));
2100 }
2101
2102 /* drm_dma.h hooks
2103 */
2104 static void ironlake_irq_preinstall(struct drm_device *dev)
2105 {
2106         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2107
2108         atomic_set(&dev_priv->irq_received, 0);
2109
2110         I915_WRITE(HWSTAM, 0xeffe);
2111
2112         /* XXX hotplug from PCH */
2113
2114         I915_WRITE(DEIMR, 0xffffffff);
2115         I915_WRITE(DEIER, 0x0);
2116         POSTING_READ(DEIER);
2117
2118         /* and GT */
2119         I915_WRITE(GTIMR, 0xffffffff);
2120         I915_WRITE(GTIER, 0x0);
2121         POSTING_READ(GTIER);
2122
2123         if (HAS_PCH_NOP(dev))
2124                 return;
2125
2126         /* south display irq */
2127         I915_WRITE(SDEIMR, 0xffffffff);
2128         /*
2129          * SDEIER is also touched by the interrupt handler to work around missed
2130          * PCH interrupts. Hence we can't update it after the interrupt handler
2131          * is enabled - instead we unconditionally enable all PCH interrupt
2132          * sources here, but then only unmask them as needed with SDEIMR.
2133          */
2134         I915_WRITE(SDEIER, 0xffffffff);
2135         POSTING_READ(SDEIER);
2136 }
2137
2138 static void valleyview_irq_preinstall(struct drm_device *dev)
2139 {
2140         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2141         int pipe;
2142
2143         atomic_set(&dev_priv->irq_received, 0);
2144
2145         /* VLV magic */
2146         I915_WRITE(VLV_IMR, 0);
2147         I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
2148         I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
2149         I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
2150
2151         /* and GT */
2152         I915_WRITE(GTIIR, I915_READ(GTIIR));
2153         I915_WRITE(GTIIR, I915_READ(GTIIR));
2154         I915_WRITE(GTIMR, 0xffffffff);
2155         I915_WRITE(GTIER, 0x0);
2156         POSTING_READ(GTIER);
2157
2158         I915_WRITE(DPINVGTT, 0xff);
2159
2160         I915_WRITE(PORT_HOTPLUG_EN, 0);
2161         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2162         for_each_pipe(pipe)
2163                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2164         I915_WRITE(VLV_IIR, 0xffffffff);
2165         I915_WRITE(VLV_IMR, 0xffffffff);
2166         I915_WRITE(VLV_IER, 0x0);
2167         POSTING_READ(VLV_IER);
2168 }
2169
2170 static void ibx_hpd_irq_setup(struct drm_device *dev)
2171 {
2172         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2173         struct drm_mode_config *mode_config = &dev->mode_config;
2174         struct intel_encoder *intel_encoder;
2175         u32 mask = ~I915_READ(SDEIMR);
2176         u32 hotplug;
2177
2178         if (HAS_PCH_IBX(dev)) {
2179                 mask &= ~SDE_HOTPLUG_MASK;
2180                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2181                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2182                                 mask |= hpd_ibx[intel_encoder->hpd_pin];
2183         } else {
2184                 mask &= ~SDE_HOTPLUG_MASK_CPT;
2185                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2186                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2187                                 mask |= hpd_cpt[intel_encoder->hpd_pin];
2188         }
2189
2190         I915_WRITE(SDEIMR, ~mask);
2191
2192         /*
2193          * Enable digital hotplug on the PCH, and configure the DP short pulse
2194          * duration to 2ms (which is the minimum in the Display Port spec)
2195          *
2196          * This register is the same on all known PCH chips.
2197          */
2198         hotplug = I915_READ(PCH_PORT_HOTPLUG);
2199         hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
2200         hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
2201         hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
2202         hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
2203         I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
2204 }
2205
2206 static void ibx_irq_postinstall(struct drm_device *dev)
2207 {
2208         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2209         u32 mask;
2210
2211         if (HAS_PCH_IBX(dev))
2212                 mask = SDE_GMBUS | SDE_AUX_MASK;
2213         else
2214                 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
2215
2216         if (HAS_PCH_NOP(dev))
2217                 return;
2218
2219         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2220         I915_WRITE(SDEIMR, ~mask);
2221 }
2222
2223 static int ironlake_irq_postinstall(struct drm_device *dev)
2224 {
2225         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2226         /* enable kind of interrupts always enabled */
2227         u32 display_mask = DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
2228                            DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
2229                            DE_AUX_CHANNEL_A;
2230         u32 render_irqs;
2231
2232         dev_priv->irq_mask = ~display_mask;
2233
2234         /* should always can generate irq */
2235         I915_WRITE(DEIIR, I915_READ(DEIIR));
2236         I915_WRITE(DEIMR, dev_priv->irq_mask);
2237         I915_WRITE(DEIER, display_mask | DE_PIPEA_VBLANK | DE_PIPEB_VBLANK);
2238         POSTING_READ(DEIER);
2239
2240         dev_priv->gt_irq_mask = ~0;
2241
2242         I915_WRITE(GTIIR, I915_READ(GTIIR));
2243         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2244
2245         if (IS_GEN6(dev))
2246                 render_irqs =
2247                         GT_USER_INTERRUPT |
2248                         GEN6_BSD_USER_INTERRUPT |
2249                         GEN6_BLITTER_USER_INTERRUPT;
2250         else
2251                 render_irqs =
2252                         GT_USER_INTERRUPT |
2253                         GT_PIPE_NOTIFY |
2254                         GT_BSD_USER_INTERRUPT;
2255         I915_WRITE(GTIER, render_irqs);
2256         POSTING_READ(GTIER);
2257
2258         ibx_irq_postinstall(dev);
2259
2260         if (IS_IRONLAKE_M(dev)) {
2261                 /* Clear & enable PCU event interrupts */
2262                 I915_WRITE(DEIIR, DE_PCU_EVENT);
2263                 I915_WRITE(DEIER, I915_READ(DEIER) | DE_PCU_EVENT);
2264                 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
2265         }
2266
2267         return 0;
2268 }
2269
2270 static int ivybridge_irq_postinstall(struct drm_device *dev)
2271 {
2272         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2273         /* enable kind of interrupts always enabled */
2274         u32 display_mask =
2275                 DE_MASTER_IRQ_CONTROL | DE_GSE_IVB | DE_PCH_EVENT_IVB |
2276                 DE_PLANEC_FLIP_DONE_IVB |
2277                 DE_PLANEB_FLIP_DONE_IVB |
2278                 DE_PLANEA_FLIP_DONE_IVB |
2279                 DE_AUX_CHANNEL_A_IVB;
2280         u32 render_irqs;
2281
2282         dev_priv->irq_mask = ~display_mask;
2283
2284         /* should always can generate irq */
2285         I915_WRITE(DEIIR, I915_READ(DEIIR));
2286         I915_WRITE(DEIMR, dev_priv->irq_mask);
2287         I915_WRITE(DEIER,
2288                    display_mask |
2289                    DE_PIPEC_VBLANK_IVB |
2290                    DE_PIPEB_VBLANK_IVB |
2291                    DE_PIPEA_VBLANK_IVB);
2292         POSTING_READ(DEIER);
2293
2294         dev_priv->gt_irq_mask = ~GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2295
2296         I915_WRITE(GTIIR, I915_READ(GTIIR));
2297         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2298
2299         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2300                 GEN6_BLITTER_USER_INTERRUPT | GT_GEN7_L3_PARITY_ERROR_INTERRUPT;
2301         I915_WRITE(GTIER, render_irqs);
2302         POSTING_READ(GTIER);
2303
2304         ibx_irq_postinstall(dev);
2305
2306         return 0;
2307 }
2308
2309 static int valleyview_irq_postinstall(struct drm_device *dev)
2310 {
2311         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2312         u32 enable_mask;
2313         u32 pipestat_enable = PLANE_FLIP_DONE_INT_EN_VLV;
2314         u32 render_irqs;
2315         u16 msid;
2316
2317         enable_mask = I915_DISPLAY_PORT_INTERRUPT;
2318         enable_mask |= I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2319                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2320                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2321                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2322
2323         /*
2324          *Leave vblank interrupts masked initially.  enable/disable will
2325          * toggle them based on usage.
2326          */
2327         dev_priv->irq_mask = (~enable_mask) |
2328                 I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT |
2329                 I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT;
2330
2331         /* Hack for broken MSIs on VLV */
2332         pci_write_config_dword(dev_priv->dev->pdev, 0x94, 0xfee00000);
2333         pci_read_config_word(dev->pdev, 0x98, &msid);
2334         msid &= 0xff; /* mask out delivery bits */
2335         msid |= (1<<14);
2336         pci_write_config_word(dev_priv->dev->pdev, 0x98, msid);
2337
2338         I915_WRITE(PORT_HOTPLUG_EN, 0);
2339         POSTING_READ(PORT_HOTPLUG_EN);
2340
2341         I915_WRITE(VLV_IMR, dev_priv->irq_mask);
2342         I915_WRITE(VLV_IER, enable_mask);
2343         I915_WRITE(VLV_IIR, 0xffffffff);
2344         I915_WRITE(PIPESTAT(0), 0xffff);
2345         I915_WRITE(PIPESTAT(1), 0xffff);
2346         POSTING_READ(VLV_IER);
2347
2348         i915_enable_pipestat(dev_priv, 0, pipestat_enable);
2349         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2350         i915_enable_pipestat(dev_priv, 1, pipestat_enable);
2351
2352         I915_WRITE(VLV_IIR, 0xffffffff);
2353         I915_WRITE(VLV_IIR, 0xffffffff);
2354
2355         I915_WRITE(GTIIR, I915_READ(GTIIR));
2356         I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
2357
2358         render_irqs = GT_USER_INTERRUPT | GEN6_BSD_USER_INTERRUPT |
2359                 GEN6_BLITTER_USER_INTERRUPT;
2360         I915_WRITE(GTIER, render_irqs);
2361         POSTING_READ(GTIER);
2362
2363         /* ack & enable invalid PTE error interrupts */
2364 #if 0 /* FIXME: add support to irq handler for checking these bits */
2365         I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
2366         I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
2367 #endif
2368
2369         I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
2370
2371         return 0;
2372 }
2373
2374 static void valleyview_irq_uninstall(struct drm_device *dev)
2375 {
2376         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2377         int pipe;
2378
2379         if (!dev_priv)
2380                 return;
2381
2382         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2383
2384         for_each_pipe(pipe)
2385                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2386
2387         I915_WRITE(HWSTAM, 0xffffffff);
2388         I915_WRITE(PORT_HOTPLUG_EN, 0);
2389         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2390         for_each_pipe(pipe)
2391                 I915_WRITE(PIPESTAT(pipe), 0xffff);
2392         I915_WRITE(VLV_IIR, 0xffffffff);
2393         I915_WRITE(VLV_IMR, 0xffffffff);
2394         I915_WRITE(VLV_IER, 0x0);
2395         POSTING_READ(VLV_IER);
2396 }
2397
2398 static void ironlake_irq_uninstall(struct drm_device *dev)
2399 {
2400         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2401
2402         if (!dev_priv)
2403                 return;
2404
2405         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2406
2407         I915_WRITE(HWSTAM, 0xffffffff);
2408
2409         I915_WRITE(DEIMR, 0xffffffff);
2410         I915_WRITE(DEIER, 0x0);
2411         I915_WRITE(DEIIR, I915_READ(DEIIR));
2412
2413         I915_WRITE(GTIMR, 0xffffffff);
2414         I915_WRITE(GTIER, 0x0);
2415         I915_WRITE(GTIIR, I915_READ(GTIIR));
2416
2417         if (HAS_PCH_NOP(dev))
2418                 return;
2419
2420         I915_WRITE(SDEIMR, 0xffffffff);
2421         I915_WRITE(SDEIER, 0x0);
2422         I915_WRITE(SDEIIR, I915_READ(SDEIIR));
2423 }
2424
2425 static void i8xx_irq_preinstall(struct drm_device * dev)
2426 {
2427         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2428         int pipe;
2429
2430         atomic_set(&dev_priv->irq_received, 0);
2431
2432         for_each_pipe(pipe)
2433                 I915_WRITE(PIPESTAT(pipe), 0);
2434         I915_WRITE16(IMR, 0xffff);
2435         I915_WRITE16(IER, 0x0);
2436         POSTING_READ16(IER);
2437 }
2438
2439 static int i8xx_irq_postinstall(struct drm_device *dev)
2440 {
2441         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2442
2443         I915_WRITE16(EMR,
2444                      ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2445
2446         /* Unmask the interrupts that we always want on. */
2447         dev_priv->irq_mask =
2448                 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2449                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2450                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2451                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2452                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2453         I915_WRITE16(IMR, dev_priv->irq_mask);
2454
2455         I915_WRITE16(IER,
2456                      I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2457                      I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2458                      I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2459                      I915_USER_INTERRUPT);
2460         POSTING_READ16(IER);
2461
2462         return 0;
2463 }
2464
2465 /*
2466  * Returns true when a page flip has completed.
2467  */
2468 static bool i8xx_handle_vblank(struct drm_device *dev,
2469                                int pipe, u16 iir)
2470 {
2471         drm_i915_private_t *dev_priv = dev->dev_private;
2472         u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(pipe);
2473
2474         if (!drm_handle_vblank(dev, pipe))
2475                 return false;
2476
2477         if ((iir & flip_pending) == 0)
2478                 return false;
2479
2480         intel_prepare_page_flip(dev, pipe);
2481
2482         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2483          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2484          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2485          * the flip is completed (no longer pending). Since this doesn't raise
2486          * an interrupt per se, we watch for the change at vblank.
2487          */
2488         if (I915_READ16(ISR) & flip_pending)
2489                 return false;
2490
2491         intel_finish_page_flip(dev, pipe);
2492
2493         return true;
2494 }
2495
2496 static irqreturn_t i8xx_irq_handler(int irq, void *arg)
2497 {
2498         struct drm_device *dev = (struct drm_device *) arg;
2499         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2500         u16 iir, new_iir;
2501         u32 pipe_stats[2];
2502         unsigned long irqflags;
2503         int irq_received;
2504         int pipe;
2505         u16 flip_mask =
2506                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2507                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2508
2509         atomic_inc(&dev_priv->irq_received);
2510
2511         iir = I915_READ16(IIR);
2512         if (iir == 0)
2513                 return IRQ_NONE;
2514
2515         while (iir & ~flip_mask) {
2516                 /* Can't rely on pipestat interrupt bit in iir as it might
2517                  * have been cleared after the pipestat interrupt was received.
2518                  * It doesn't set the bit in iir again, but it still produces
2519                  * interrupts (for non-MSI).
2520                  */
2521                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2522                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2523                         i915_handle_error(dev, false);
2524
2525                 for_each_pipe(pipe) {
2526                         int reg = PIPESTAT(pipe);
2527                         pipe_stats[pipe] = I915_READ(reg);
2528
2529                         /*
2530                          * Clear the PIPE*STAT regs before the IIR
2531                          */
2532                         if (pipe_stats[pipe] & 0x8000ffff) {
2533                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2534                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2535                                                          pipe_name(pipe));
2536                                 I915_WRITE(reg, pipe_stats[pipe]);
2537                                 irq_received = 1;
2538                         }
2539                 }
2540                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2541
2542                 I915_WRITE16(IIR, iir & ~flip_mask);
2543                 new_iir = I915_READ16(IIR); /* Flush posted writes */
2544
2545                 i915_update_dri1_breadcrumb(dev);
2546
2547                 if (iir & I915_USER_INTERRUPT)
2548                         notify_ring(dev, &dev_priv->ring[RCS]);
2549
2550                 if (pipe_stats[0] & PIPE_VBLANK_INTERRUPT_STATUS &&
2551                     i8xx_handle_vblank(dev, 0, iir))
2552                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(0);
2553
2554                 if (pipe_stats[1] & PIPE_VBLANK_INTERRUPT_STATUS &&
2555                     i8xx_handle_vblank(dev, 1, iir))
2556                         flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(1);
2557
2558                 iir = new_iir;
2559         }
2560
2561         return IRQ_HANDLED;
2562 }
2563
2564 static void i8xx_irq_uninstall(struct drm_device * dev)
2565 {
2566         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2567         int pipe;
2568
2569         for_each_pipe(pipe) {
2570                 /* Clear enable bits; then clear status bits */
2571                 I915_WRITE(PIPESTAT(pipe), 0);
2572                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2573         }
2574         I915_WRITE16(IMR, 0xffff);
2575         I915_WRITE16(IER, 0x0);
2576         I915_WRITE16(IIR, I915_READ16(IIR));
2577 }
2578
2579 static void i915_irq_preinstall(struct drm_device * dev)
2580 {
2581         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2582         int pipe;
2583
2584         atomic_set(&dev_priv->irq_received, 0);
2585
2586         if (I915_HAS_HOTPLUG(dev)) {
2587                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2588                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2589         }
2590
2591         I915_WRITE16(HWSTAM, 0xeffe);
2592         for_each_pipe(pipe)
2593                 I915_WRITE(PIPESTAT(pipe), 0);
2594         I915_WRITE(IMR, 0xffffffff);
2595         I915_WRITE(IER, 0x0);
2596         POSTING_READ(IER);
2597 }
2598
2599 static int i915_irq_postinstall(struct drm_device *dev)
2600 {
2601         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2602         u32 enable_mask;
2603
2604         I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
2605
2606         /* Unmask the interrupts that we always want on. */
2607         dev_priv->irq_mask =
2608                 ~(I915_ASLE_INTERRUPT |
2609                   I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2610                   I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2611                   I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2612                   I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2613                   I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2614
2615         enable_mask =
2616                 I915_ASLE_INTERRUPT |
2617                 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2618                 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2619                 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT |
2620                 I915_USER_INTERRUPT;
2621
2622         if (I915_HAS_HOTPLUG(dev)) {
2623                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2624                 POSTING_READ(PORT_HOTPLUG_EN);
2625
2626                 /* Enable in IER... */
2627                 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
2628                 /* and unmask in IMR */
2629                 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
2630         }
2631
2632         I915_WRITE(IMR, dev_priv->irq_mask);
2633         I915_WRITE(IER, enable_mask);
2634         POSTING_READ(IER);
2635
2636         intel_opregion_enable_asle(dev);
2637
2638         return 0;
2639 }
2640
2641 /*
2642  * Returns true when a page flip has completed.
2643  */
2644 static bool i915_handle_vblank(struct drm_device *dev,
2645                                int plane, int pipe, u32 iir)
2646 {
2647         drm_i915_private_t *dev_priv = dev->dev_private;
2648         u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
2649
2650         if (!drm_handle_vblank(dev, pipe))
2651                 return false;
2652
2653         if ((iir & flip_pending) == 0)
2654                 return false;
2655
2656         intel_prepare_page_flip(dev, plane);
2657
2658         /* We detect FlipDone by looking for the change in PendingFlip from '1'
2659          * to '0' on the following vblank, i.e. IIR has the Pendingflip
2660          * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
2661          * the flip is completed (no longer pending). Since this doesn't raise
2662          * an interrupt per se, we watch for the change at vblank.
2663          */
2664         if (I915_READ(ISR) & flip_pending)
2665                 return false;
2666
2667         intel_finish_page_flip(dev, pipe);
2668
2669         return true;
2670 }
2671
2672 static irqreturn_t i915_irq_handler(int irq, void *arg)
2673 {
2674         struct drm_device *dev = (struct drm_device *) arg;
2675         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2676         u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
2677         unsigned long irqflags;
2678         u32 flip_mask =
2679                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2680                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2681         int pipe, ret = IRQ_NONE;
2682
2683         atomic_inc(&dev_priv->irq_received);
2684
2685         iir = I915_READ(IIR);
2686         do {
2687                 bool irq_received = (iir & ~flip_mask) != 0;
2688                 bool blc_event = false;
2689
2690                 /* Can't rely on pipestat interrupt bit in iir as it might
2691                  * have been cleared after the pipestat interrupt was received.
2692                  * It doesn't set the bit in iir again, but it still produces
2693                  * interrupts (for non-MSI).
2694                  */
2695                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2696                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2697                         i915_handle_error(dev, false);
2698
2699                 for_each_pipe(pipe) {
2700                         int reg = PIPESTAT(pipe);
2701                         pipe_stats[pipe] = I915_READ(reg);
2702
2703                         /* Clear the PIPE*STAT regs before the IIR */
2704                         if (pipe_stats[pipe] & 0x8000ffff) {
2705                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2706                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2707                                                          pipe_name(pipe));
2708                                 I915_WRITE(reg, pipe_stats[pipe]);
2709                                 irq_received = true;
2710                         }
2711                 }
2712                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2713
2714                 if (!irq_received)
2715                         break;
2716
2717                 /* Consume port.  Then clear IIR or we'll miss events */
2718                 if ((I915_HAS_HOTPLUG(dev)) &&
2719                     (iir & I915_DISPLAY_PORT_INTERRUPT)) {
2720                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2721                         u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
2722
2723                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2724                                   hotplug_status);
2725                         if (hotplug_trigger) {
2726                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger, hpd_status_i915))
2727                                         i915_hpd_irq_setup(dev);
2728                                 queue_work(dev_priv->wq,
2729                                            &dev_priv->hotplug_work);
2730                         }
2731                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2732                         POSTING_READ(PORT_HOTPLUG_STAT);
2733                 }
2734
2735                 I915_WRITE(IIR, iir & ~flip_mask);
2736                 new_iir = I915_READ(IIR); /* Flush posted writes */
2737
2738                 if (iir & I915_USER_INTERRUPT)
2739                         notify_ring(dev, &dev_priv->ring[RCS]);
2740
2741                 for_each_pipe(pipe) {
2742                         int plane = pipe;
2743                         if (IS_MOBILE(dev))
2744                                 plane = !plane;
2745
2746                         if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
2747                             i915_handle_vblank(dev, plane, pipe, iir))
2748                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
2749
2750                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2751                                 blc_event = true;
2752                 }
2753
2754                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2755                         intel_opregion_asle_intr(dev);
2756
2757                 /* With MSI, interrupts are only generated when iir
2758                  * transitions from zero to nonzero.  If another bit got
2759                  * set while we were handling the existing iir bits, then
2760                  * we would never get another interrupt.
2761                  *
2762                  * This is fine on non-MSI as well, as if we hit this path
2763                  * we avoid exiting the interrupt handler only to generate
2764                  * another one.
2765                  *
2766                  * Note that for MSI this could cause a stray interrupt report
2767                  * if an interrupt landed in the time between writing IIR and
2768                  * the posting read.  This should be rare enough to never
2769                  * trigger the 99% of 100,000 interrupts test for disabling
2770                  * stray interrupts.
2771                  */
2772                 ret = IRQ_HANDLED;
2773                 iir = new_iir;
2774         } while (iir & ~flip_mask);
2775
2776         i915_update_dri1_breadcrumb(dev);
2777
2778         return ret;
2779 }
2780
2781 static void i915_irq_uninstall(struct drm_device * dev)
2782 {
2783         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2784         int pipe;
2785
2786         del_timer_sync(&dev_priv->hotplug_reenable_timer);
2787
2788         if (I915_HAS_HOTPLUG(dev)) {
2789                 I915_WRITE(PORT_HOTPLUG_EN, 0);
2790                 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2791         }
2792
2793         I915_WRITE16(HWSTAM, 0xffff);
2794         for_each_pipe(pipe) {
2795                 /* Clear enable bits; then clear status bits */
2796                 I915_WRITE(PIPESTAT(pipe), 0);
2797                 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
2798         }
2799         I915_WRITE(IMR, 0xffffffff);
2800         I915_WRITE(IER, 0x0);
2801
2802         I915_WRITE(IIR, I915_READ(IIR));
2803 }
2804
2805 static void i965_irq_preinstall(struct drm_device * dev)
2806 {
2807         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2808         int pipe;
2809
2810         atomic_set(&dev_priv->irq_received, 0);
2811
2812         I915_WRITE(PORT_HOTPLUG_EN, 0);
2813         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
2814
2815         I915_WRITE(HWSTAM, 0xeffe);
2816         for_each_pipe(pipe)
2817                 I915_WRITE(PIPESTAT(pipe), 0);
2818         I915_WRITE(IMR, 0xffffffff);
2819         I915_WRITE(IER, 0x0);
2820         POSTING_READ(IER);
2821 }
2822
2823 static int i965_irq_postinstall(struct drm_device *dev)
2824 {
2825         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2826         u32 enable_mask;
2827         u32 error_mask;
2828
2829         /* Unmask the interrupts that we always want on. */
2830         dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
2831                                I915_DISPLAY_PORT_INTERRUPT |
2832                                I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
2833                                I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
2834                                I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2835                                I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
2836                                I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2837
2838         enable_mask = ~dev_priv->irq_mask;
2839         enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2840                          I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
2841         enable_mask |= I915_USER_INTERRUPT;
2842
2843         if (IS_G4X(dev))
2844                 enable_mask |= I915_BSD_USER_INTERRUPT;
2845
2846         i915_enable_pipestat(dev_priv, 0, PIPE_GMBUS_EVENT_ENABLE);
2847
2848         /*
2849          * Enable some error detection, note the instruction error mask
2850          * bit is reserved, so we leave it masked.
2851          */
2852         if (IS_G4X(dev)) {
2853                 error_mask = ~(GM45_ERROR_PAGE_TABLE |
2854                                GM45_ERROR_MEM_PRIV |
2855                                GM45_ERROR_CP_PRIV |
2856                                I915_ERROR_MEMORY_REFRESH);
2857         } else {
2858                 error_mask = ~(I915_ERROR_PAGE_TABLE |
2859                                I915_ERROR_MEMORY_REFRESH);
2860         }
2861         I915_WRITE(EMR, error_mask);
2862
2863         I915_WRITE(IMR, dev_priv->irq_mask);
2864         I915_WRITE(IER, enable_mask);
2865         POSTING_READ(IER);
2866
2867         I915_WRITE(PORT_HOTPLUG_EN, 0);
2868         POSTING_READ(PORT_HOTPLUG_EN);
2869
2870         intel_opregion_enable_asle(dev);
2871
2872         return 0;
2873 }
2874
2875 static void i915_hpd_irq_setup(struct drm_device *dev)
2876 {
2877         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2878         struct drm_mode_config *mode_config = &dev->mode_config;
2879         struct intel_encoder *intel_encoder;
2880         u32 hotplug_en;
2881
2882         if (I915_HAS_HOTPLUG(dev)) {
2883                 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
2884                 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
2885                 /* Note HDMI and DP share hotplug bits */
2886                 /* enable bits are the same for all generations */
2887                 list_for_each_entry(intel_encoder, &mode_config->encoder_list, base.head)
2888                         if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
2889                                 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
2890                 /* Programming the CRT detection parameters tends
2891                    to generate a spurious hotplug event about three
2892                    seconds later.  So just do it once.
2893                 */
2894                 if (IS_G4X(dev))
2895                         hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
2896                 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
2897                 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
2898
2899                 /* Ignore TV since it's buggy */
2900                 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
2901         }
2902 }
2903
2904 static irqreturn_t i965_irq_handler(int irq, void *arg)
2905 {
2906         struct drm_device *dev = (struct drm_device *) arg;
2907         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
2908         u32 iir, new_iir;
2909         u32 pipe_stats[I915_MAX_PIPES];
2910         unsigned long irqflags;
2911         int irq_received;
2912         int ret = IRQ_NONE, pipe;
2913         u32 flip_mask =
2914                 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
2915                 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
2916
2917         atomic_inc(&dev_priv->irq_received);
2918
2919         iir = I915_READ(IIR);
2920
2921         for (;;) {
2922                 bool blc_event = false;
2923
2924                 irq_received = (iir & ~flip_mask) != 0;
2925
2926                 /* Can't rely on pipestat interrupt bit in iir as it might
2927                  * have been cleared after the pipestat interrupt was received.
2928                  * It doesn't set the bit in iir again, but it still produces
2929                  * interrupts (for non-MSI).
2930                  */
2931                 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
2932                 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
2933                         i915_handle_error(dev, false);
2934
2935                 for_each_pipe(pipe) {
2936                         int reg = PIPESTAT(pipe);
2937                         pipe_stats[pipe] = I915_READ(reg);
2938
2939                         /*
2940                          * Clear the PIPE*STAT regs before the IIR
2941                          */
2942                         if (pipe_stats[pipe] & 0x8000ffff) {
2943                                 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
2944                                         DRM_DEBUG_DRIVER("pipe %c underrun\n",
2945                                                          pipe_name(pipe));
2946                                 I915_WRITE(reg, pipe_stats[pipe]);
2947                                 irq_received = 1;
2948                         }
2949                 }
2950                 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2951
2952                 if (!irq_received)
2953                         break;
2954
2955                 ret = IRQ_HANDLED;
2956
2957                 /* Consume port.  Then clear IIR or we'll miss events */
2958                 if (iir & I915_DISPLAY_PORT_INTERRUPT) {
2959                         u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
2960                         u32 hotplug_trigger = hotplug_status & (IS_G4X(dev) ?
2961                                                                   HOTPLUG_INT_STATUS_G4X :
2962                                                                   HOTPLUG_INT_STATUS_I965);
2963
2964                         DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2965                                   hotplug_status);
2966                         if (hotplug_trigger) {
2967                                 if (hotplug_irq_storm_detect(dev, hotplug_trigger,
2968                                                             IS_G4X(dev) ? hpd_status_gen4 : hpd_status_i965))
2969                                         i915_hpd_irq_setup(dev);
2970                                 queue_work(dev_priv->wq,
2971                                            &dev_priv->hotplug_work);
2972                         }
2973                         I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
2974                         I915_READ(PORT_HOTPLUG_STAT);
2975                 }
2976
2977                 I915_WRITE(IIR, iir & ~flip_mask);
2978                 new_iir = I915_READ(IIR); /* Flush posted writes */
2979
2980                 if (iir & I915_USER_INTERRUPT)
2981                         notify_ring(dev, &dev_priv->ring[RCS]);
2982                 if (iir & I915_BSD_USER_INTERRUPT)
2983                         notify_ring(dev, &dev_priv->ring[VCS]);
2984
2985                 for_each_pipe(pipe) {
2986                         if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
2987                             i915_handle_vblank(dev, pipe, pipe, iir))
2988                                 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
2989
2990                         if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
2991                                 blc_event = true;
2992                 }
2993
2994
2995                 if (blc_event || (iir & I915_ASLE_INTERRUPT))
2996                         intel_opregion_asle_intr(dev);
2997
2998                 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
2999                         gmbus_irq_handler(dev);
3000
3001                 /* With MSI, interrupts are only generated when iir
3002                  * transitions from zero to nonzero.  If another bit got
3003                  * set while we were handling the existing iir bits, then
3004                  * we would never get another interrupt.
3005                  *
3006                  * This is fine on non-MSI as well, as if we hit this path
3007                  * we avoid exiting the interrupt handler only to generate
3008                  * another one.
3009                  *
3010                  * Note that for MSI this could cause a stray interrupt report
3011                  * if an interrupt landed in the time between writing IIR and
3012                  * the posting read.  This should be rare enough to never
3013                  * trigger the 99% of 100,000 interrupts test for disabling
3014                  * stray interrupts.
3015                  */
3016                 iir = new_iir;
3017         }
3018
3019         i915_update_dri1_breadcrumb(dev);
3020
3021         return ret;
3022 }
3023
3024 static void i965_irq_uninstall(struct drm_device * dev)
3025 {
3026         drm_i915_private_t *dev_priv = (drm_i915_private_t *) dev->dev_private;
3027         int pipe;
3028
3029         if (!dev_priv)
3030                 return;
3031
3032         del_timer_sync(&dev_priv->hotplug_reenable_timer);
3033
3034         I915_WRITE(PORT_HOTPLUG_EN, 0);
3035         I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3036
3037         I915_WRITE(HWSTAM, 0xffffffff);
3038         for_each_pipe(pipe)
3039                 I915_WRITE(PIPESTAT(pipe), 0);
3040         I915_WRITE(IMR, 0xffffffff);
3041         I915_WRITE(IER, 0x0);
3042
3043         for_each_pipe(pipe)
3044                 I915_WRITE(PIPESTAT(pipe),
3045                            I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
3046         I915_WRITE(IIR, I915_READ(IIR));
3047 }
3048
3049 static void i915_reenable_hotplug_timer_func(unsigned long data)
3050 {
3051         drm_i915_private_t *dev_priv = (drm_i915_private_t *)data;
3052         struct drm_device *dev = dev_priv->dev;
3053         struct drm_mode_config *mode_config = &dev->mode_config;
3054         unsigned long irqflags;
3055         int i;
3056
3057         spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
3058         for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
3059                 struct drm_connector *connector;
3060
3061                 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
3062                         continue;
3063
3064                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3065
3066                 list_for_each_entry(connector, &mode_config->connector_list, head) {
3067                         struct intel_connector *intel_connector = to_intel_connector(connector);
3068
3069                         if (intel_connector->encoder->hpd_pin == i) {
3070                                 if (connector->polled != intel_connector->polled)
3071                                         DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
3072                                                          drm_get_connector_name(connector));
3073                                 connector->polled = intel_connector->polled;
3074                                 if (!connector->polled)
3075                                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3076                         }
3077                 }
3078         }
3079         if (dev_priv->display.hpd_irq_setup)
3080                 dev_priv->display.hpd_irq_setup(dev);
3081         spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
3082 }
3083
3084 void intel_irq_init(struct drm_device *dev)
3085 {
3086         struct drm_i915_private *dev_priv = dev->dev_private;
3087
3088         INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
3089         INIT_WORK(&dev_priv->gpu_error.work, i915_error_work_func);
3090         INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
3091         INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
3092
3093         setup_timer(&dev_priv->gpu_error.hangcheck_timer,
3094                     i915_hangcheck_elapsed,
3095                     (unsigned long) dev);
3096         setup_timer(&dev_priv->hotplug_reenable_timer, i915_reenable_hotplug_timer_func,
3097                     (unsigned long) dev_priv);
3098
3099         pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
3100
3101         dev->driver->get_vblank_counter = i915_get_vblank_counter;
3102         dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
3103         if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
3104                 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
3105                 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
3106         }
3107
3108         if (drm_core_check_feature(dev, DRIVER_MODESET))
3109                 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
3110         else
3111                 dev->driver->get_vblank_timestamp = NULL;
3112         dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
3113
3114         if (IS_VALLEYVIEW(dev)) {
3115                 dev->driver->irq_handler = valleyview_irq_handler;
3116                 dev->driver->irq_preinstall = valleyview_irq_preinstall;
3117                 dev->driver->irq_postinstall = valleyview_irq_postinstall;
3118                 dev->driver->irq_uninstall = valleyview_irq_uninstall;
3119                 dev->driver->enable_vblank = valleyview_enable_vblank;
3120                 dev->driver->disable_vblank = valleyview_disable_vblank;
3121                 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3122         } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
3123                 /* Share pre & uninstall handlers with ILK/SNB */
3124                 dev->driver->irq_handler = ivybridge_irq_handler;
3125                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3126                 dev->driver->irq_postinstall = ivybridge_irq_postinstall;
3127                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3128                 dev->driver->enable_vblank = ivybridge_enable_vblank;
3129                 dev->driver->disable_vblank = ivybridge_disable_vblank;
3130                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3131         } else if (HAS_PCH_SPLIT(dev)) {
3132                 dev->driver->irq_handler = ironlake_irq_handler;
3133                 dev->driver->irq_preinstall = ironlake_irq_preinstall;
3134                 dev->driver->irq_postinstall = ironlake_irq_postinstall;
3135                 dev->driver->irq_uninstall = ironlake_irq_uninstall;
3136                 dev->driver->enable_vblank = ironlake_enable_vblank;
3137                 dev->driver->disable_vblank = ironlake_disable_vblank;
3138                 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
3139         } else {
3140                 if (INTEL_INFO(dev)->gen == 2) {
3141                         dev->driver->irq_preinstall = i8xx_irq_preinstall;
3142                         dev->driver->irq_postinstall = i8xx_irq_postinstall;
3143                         dev->driver->irq_handler = i8xx_irq_handler;
3144                         dev->driver->irq_uninstall = i8xx_irq_uninstall;
3145                 } else if (INTEL_INFO(dev)->gen == 3) {
3146                         dev->driver->irq_preinstall = i915_irq_preinstall;
3147                         dev->driver->irq_postinstall = i915_irq_postinstall;
3148                         dev->driver->irq_uninstall = i915_irq_uninstall;
3149                         dev->driver->irq_handler = i915_irq_handler;
3150                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3151                 } else {
3152                         dev->driver->irq_preinstall = i965_irq_preinstall;
3153                         dev->driver->irq_postinstall = i965_irq_postinstall;
3154                         dev->driver->irq_uninstall = i965_irq_uninstall;
3155                         dev->driver->irq_handler = i965_irq_handler;
3156                         dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
3157                 }
3158                 dev->driver->enable_vblank = i915_enable_vblank;
3159                 dev->driver->disable_vblank = i915_disable_vblank;
3160         }
3161 }
3162
3163 void intel_hpd_init(struct drm_device *dev)
3164 {
3165         struct drm_i915_private *dev_priv = dev->dev_private;
3166         struct drm_mode_config *mode_config = &dev->mode_config;
3167         struct drm_connector *connector;
3168         int i;
3169
3170         for (i = 1; i < HPD_NUM_PINS; i++) {
3171                 dev_priv->hpd_stats[i].hpd_cnt = 0;
3172                 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
3173         }
3174         list_for_each_entry(connector, &mode_config->connector_list, head) {
3175                 struct intel_connector *intel_connector = to_intel_connector(connector);
3176                 connector->polled = intel_connector->polled;
3177                 if (!connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
3178                         connector->polled = DRM_CONNECTOR_POLL_HPD;
3179         }
3180         if (dev_priv->display.hpd_irq_setup)
3181                 dev_priv->display.hpd_irq_setup(dev);
3182 }