2 * Copyright (C) 2001 Mike Corrigan & Dave Engebretsen, IBM Corporation
4 * Rewrite, cleanup, new allocation schemes, virtual merging:
5 * Copyright (C) 2004 Olof Johansson, IBM Corporation
6 * and Ben. Herrenschmidt, IBM Corporation
8 * Dynamic DMA mapping support, bus-independent parts.
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; either version 2 of the License, or
13 * (at your option) any later version.
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
26 #include <linux/init.h>
27 #include <linux/types.h>
28 #include <linux/slab.h>
30 #include <linux/spinlock.h>
31 #include <linux/string.h>
32 #include <linux/dma-mapping.h>
33 #include <linux/bitmap.h>
34 #include <linux/iommu-helper.h>
35 #include <linux/crash_dump.h>
36 #include <linux/hash.h>
39 #include <asm/iommu.h>
40 #include <asm/pci-bridge.h>
41 #include <asm/machdep.h>
42 #include <asm/kdump.h>
43 #include <asm/fadump.h>
49 static void __iommu_free(struct iommu_table *, dma_addr_t, unsigned int);
51 static int __init setup_iommu(char *str)
53 if (!strcmp(str, "novmerge"))
55 else if (!strcmp(str, "vmerge"))
60 __setup("iommu=", setup_iommu);
62 static DEFINE_PER_CPU(unsigned int, iommu_pool_hash);
65 * We precalculate the hash to avoid doing it on every allocation.
67 * The hash is important to spread CPUs across all the pools. For example,
68 * on a POWER7 with 4 way SMT we want interrupts on the primary threads and
69 * with 4 pools all primary threads would map to the same pool.
71 static int __init setup_iommu_pool_hash(void)
75 for_each_possible_cpu(i)
76 per_cpu(iommu_pool_hash, i) = hash_32(i, IOMMU_POOL_HASHBITS);
80 subsys_initcall(setup_iommu_pool_hash);
82 static unsigned long iommu_range_alloc(struct device *dev,
83 struct iommu_table *tbl,
85 unsigned long *handle,
87 unsigned int align_order)
89 unsigned long n, end, start;
91 int largealloc = npages > 15;
93 unsigned long align_mask;
94 unsigned long boundary_size;
97 struct iommu_pool *pool;
99 align_mask = 0xffffffffffffffffl >> (64 - align_order);
101 /* This allocator was derived from x86_64's bit string search */
104 if (unlikely(npages == 0)) {
105 if (printk_ratelimit())
107 return DMA_ERROR_CODE;
111 * We don't need to disable preemption here because any CPU can
112 * safely use any IOMMU pool.
114 pool_nr = __raw_get_cpu_var(iommu_pool_hash) & (tbl->nr_pools - 1);
117 pool = &(tbl->large_pool);
119 pool = &(tbl->pools[pool_nr]);
121 spin_lock_irqsave(&(pool->lock), flags);
124 if ((pass == 0) && handle && *handle)
131 /* The case below can happen if we have a small segment appended
132 * to a large, or when the previous alloc was at the very end of
133 * the available space. If so, go back to the initial start.
138 if (limit + tbl->it_offset > mask) {
139 limit = mask - tbl->it_offset + 1;
140 /* If we're constrained on address range, first try
141 * at the masked hint to avoid O(n) search complexity,
142 * but on second pass, start at 0 in pool 0.
144 if ((start & mask) >= limit || pass > 0) {
145 pool = &(tbl->pools[0]);
153 boundary_size = ALIGN(dma_get_seg_boundary(dev) + 1,
154 1 << IOMMU_PAGE_SHIFT);
156 boundary_size = ALIGN(1UL << 32, 1 << IOMMU_PAGE_SHIFT);
157 /* 4GB boundary for iseries_hv_alloc and iseries_hv_map */
159 n = iommu_area_alloc(tbl->it_map, limit, start, npages,
160 tbl->it_offset, boundary_size >> IOMMU_PAGE_SHIFT,
163 if (likely(pass == 0)) {
164 /* First try the pool from the start */
165 pool->hint = pool->start;
169 } else if (pass <= tbl->nr_pools) {
170 /* Now try scanning all the other pools */
171 spin_unlock(&(pool->lock));
172 pool_nr = (pool_nr + 1) & (tbl->nr_pools - 1);
173 pool = &tbl->pools[pool_nr];
174 spin_lock(&(pool->lock));
175 pool->hint = pool->start;
181 spin_unlock_irqrestore(&(pool->lock), flags);
182 return DMA_ERROR_CODE;
188 /* Bump the hint to a new block for small allocs. */
190 /* Don't bump to new block to avoid fragmentation */
193 /* Overflow will be taken care of at the next allocation */
194 pool->hint = (end + tbl->it_blocksize - 1) &
195 ~(tbl->it_blocksize - 1);
198 /* Update handle for SG allocations */
202 spin_unlock_irqrestore(&(pool->lock), flags);
207 static dma_addr_t iommu_alloc(struct device *dev, struct iommu_table *tbl,
208 void *page, unsigned int npages,
209 enum dma_data_direction direction,
210 unsigned long mask, unsigned int align_order,
211 struct dma_attrs *attrs)
214 dma_addr_t ret = DMA_ERROR_CODE;
217 entry = iommu_range_alloc(dev, tbl, npages, NULL, mask, align_order);
219 if (unlikely(entry == DMA_ERROR_CODE))
220 return DMA_ERROR_CODE;
222 entry += tbl->it_offset; /* Offset into real TCE table */
223 ret = entry << IOMMU_PAGE_SHIFT; /* Set the return dma address */
225 /* Put the TCEs in the HW table */
226 build_fail = ppc_md.tce_build(tbl, entry, npages,
227 (unsigned long)page & IOMMU_PAGE_MASK,
230 /* ppc_md.tce_build() only returns non-zero for transient errors.
231 * Clean up the table bitmap in this case and return
232 * DMA_ERROR_CODE. For all other errors the functionality is
235 if (unlikely(build_fail)) {
236 __iommu_free(tbl, ret, npages);
237 return DMA_ERROR_CODE;
240 /* Flush/invalidate TLB caches if necessary */
241 if (ppc_md.tce_flush)
242 ppc_md.tce_flush(tbl);
244 /* Make sure updates are seen by hardware */
250 static bool iommu_free_check(struct iommu_table *tbl, dma_addr_t dma_addr,
253 unsigned long entry, free_entry;
255 entry = dma_addr >> IOMMU_PAGE_SHIFT;
256 free_entry = entry - tbl->it_offset;
258 if (((free_entry + npages) > tbl->it_size) ||
259 (entry < tbl->it_offset)) {
260 if (printk_ratelimit()) {
261 printk(KERN_INFO "iommu_free: invalid entry\n");
262 printk(KERN_INFO "\tentry = 0x%lx\n", entry);
263 printk(KERN_INFO "\tdma_addr = 0x%llx\n", (u64)dma_addr);
264 printk(KERN_INFO "\tTable = 0x%llx\n", (u64)tbl);
265 printk(KERN_INFO "\tbus# = 0x%llx\n", (u64)tbl->it_busno);
266 printk(KERN_INFO "\tsize = 0x%llx\n", (u64)tbl->it_size);
267 printk(KERN_INFO "\tstartOff = 0x%llx\n", (u64)tbl->it_offset);
268 printk(KERN_INFO "\tindex = 0x%llx\n", (u64)tbl->it_index);
278 static struct iommu_pool *get_pool(struct iommu_table *tbl,
281 struct iommu_pool *p;
282 unsigned long largepool_start = tbl->large_pool.start;
284 /* The large pool is the last pool at the top of the table */
285 if (entry >= largepool_start) {
286 p = &tbl->large_pool;
288 unsigned int pool_nr = entry / tbl->poolsize;
290 BUG_ON(pool_nr > tbl->nr_pools);
291 p = &tbl->pools[pool_nr];
297 static void __iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
300 unsigned long entry, free_entry;
302 struct iommu_pool *pool;
304 entry = dma_addr >> IOMMU_PAGE_SHIFT;
305 free_entry = entry - tbl->it_offset;
307 pool = get_pool(tbl, free_entry);
309 if (!iommu_free_check(tbl, dma_addr, npages))
312 ppc_md.tce_free(tbl, entry, npages);
314 spin_lock_irqsave(&(pool->lock), flags);
315 bitmap_clear(tbl->it_map, free_entry, npages);
316 spin_unlock_irqrestore(&(pool->lock), flags);
319 static void iommu_free(struct iommu_table *tbl, dma_addr_t dma_addr,
322 __iommu_free(tbl, dma_addr, npages);
324 /* Make sure TLB cache is flushed if the HW needs it. We do
325 * not do an mb() here on purpose, it is not needed on any of
326 * the current platforms.
328 if (ppc_md.tce_flush)
329 ppc_md.tce_flush(tbl);
332 int iommu_map_sg(struct device *dev, struct iommu_table *tbl,
333 struct scatterlist *sglist, int nelems,
334 unsigned long mask, enum dma_data_direction direction,
335 struct dma_attrs *attrs)
337 dma_addr_t dma_next = 0, dma_addr;
338 struct scatterlist *s, *outs, *segstart;
339 int outcount, incount, i, build_fail = 0;
341 unsigned long handle;
342 unsigned int max_seg_size;
344 BUG_ON(direction == DMA_NONE);
346 if ((nelems == 0) || !tbl)
349 outs = s = segstart = &sglist[0];
354 /* Init first segment length for backout at failure */
355 outs->dma_length = 0;
357 DBG("sg mapping %d elements:\n", nelems);
359 max_seg_size = dma_get_max_seg_size(dev);
360 for_each_sg(sglist, s, nelems, i) {
361 unsigned long vaddr, npages, entry, slen;
369 /* Allocate iommu entries for that segment */
370 vaddr = (unsigned long) sg_virt(s);
371 npages = iommu_num_pages(vaddr, slen, IOMMU_PAGE_SIZE);
373 if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && slen >= PAGE_SIZE &&
374 (vaddr & ~PAGE_MASK) == 0)
375 align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
376 entry = iommu_range_alloc(dev, tbl, npages, &handle,
377 mask >> IOMMU_PAGE_SHIFT, align);
379 DBG(" - vaddr: %lx, size: %lx\n", vaddr, slen);
382 if (unlikely(entry == DMA_ERROR_CODE)) {
383 if (printk_ratelimit())
384 dev_info(dev, "iommu_alloc failed, tbl %p "
385 "vaddr %lx npages %lu\n", tbl, vaddr,
390 /* Convert entry to a dma_addr_t */
391 entry += tbl->it_offset;
392 dma_addr = entry << IOMMU_PAGE_SHIFT;
393 dma_addr |= (s->offset & ~IOMMU_PAGE_MASK);
395 DBG(" - %lu pages, entry: %lx, dma_addr: %lx\n",
396 npages, entry, dma_addr);
398 /* Insert into HW table */
399 build_fail = ppc_md.tce_build(tbl, entry, npages,
400 vaddr & IOMMU_PAGE_MASK,
402 if(unlikely(build_fail))
405 /* If we are in an open segment, try merging */
407 DBG(" - trying merge...\n");
408 /* We cannot merge if:
409 * - allocated dma_addr isn't contiguous to previous allocation
411 if (novmerge || (dma_addr != dma_next) ||
412 (outs->dma_length + s->length > max_seg_size)) {
413 /* Can't merge: create a new segment */
416 outs = sg_next(outs);
417 DBG(" can't merge, new segment.\n");
419 outs->dma_length += s->length;
420 DBG(" merged, new len: %ux\n", outs->dma_length);
425 /* This is a new segment, fill entries */
426 DBG(" - filling new segment.\n");
427 outs->dma_address = dma_addr;
428 outs->dma_length = slen;
431 /* Calculate next page pointer for contiguous check */
432 dma_next = dma_addr + slen;
434 DBG(" - dma next is: %lx\n", dma_next);
437 /* Flush/invalidate TLB caches if necessary */
438 if (ppc_md.tce_flush)
439 ppc_md.tce_flush(tbl);
441 DBG("mapped %d elements:\n", outcount);
443 /* For the sake of iommu_unmap_sg, we clear out the length in the
444 * next entry of the sglist if we didn't fill the list completely
446 if (outcount < incount) {
447 outs = sg_next(outs);
448 outs->dma_address = DMA_ERROR_CODE;
449 outs->dma_length = 0;
452 /* Make sure updates are seen by hardware */
458 for_each_sg(sglist, s, nelems, i) {
459 if (s->dma_length != 0) {
460 unsigned long vaddr, npages;
462 vaddr = s->dma_address & IOMMU_PAGE_MASK;
463 npages = iommu_num_pages(s->dma_address, s->dma_length,
465 __iommu_free(tbl, vaddr, npages);
466 s->dma_address = DMA_ERROR_CODE;
476 void iommu_unmap_sg(struct iommu_table *tbl, struct scatterlist *sglist,
477 int nelems, enum dma_data_direction direction,
478 struct dma_attrs *attrs)
480 struct scatterlist *sg;
482 BUG_ON(direction == DMA_NONE);
490 dma_addr_t dma_handle = sg->dma_address;
492 if (sg->dma_length == 0)
494 npages = iommu_num_pages(dma_handle, sg->dma_length,
496 __iommu_free(tbl, dma_handle, npages);
500 /* Flush/invalidate TLBs if necessary. As for iommu_free(), we
501 * do not do an mb() here, the affected platforms do not need it
504 if (ppc_md.tce_flush)
505 ppc_md.tce_flush(tbl);
508 static void iommu_table_clear(struct iommu_table *tbl)
511 * In case of firmware assisted dump system goes through clean
512 * reboot process at the time of system crash. Hence it's safe to
513 * clear the TCE entries if firmware assisted dump is active.
515 if (!is_kdump_kernel() || is_fadump_active()) {
516 /* Clear the table in case firmware left allocations in it */
517 ppc_md.tce_free(tbl, tbl->it_offset, tbl->it_size);
521 #ifdef CONFIG_CRASH_DUMP
522 if (ppc_md.tce_get) {
523 unsigned long index, tceval, tcecount = 0;
525 /* Reserve the existing mappings left by the first kernel. */
526 for (index = 0; index < tbl->it_size; index++) {
527 tceval = ppc_md.tce_get(tbl, index + tbl->it_offset);
529 * Freed TCE entry contains 0x7fffffffffffffff on JS20
531 if (tceval && (tceval != 0x7fffffffffffffffUL)) {
532 __set_bit(index, tbl->it_map);
537 if ((tbl->it_size - tcecount) < KDUMP_MIN_TCE_ENTRIES) {
538 printk(KERN_WARNING "TCE table is full; freeing ");
539 printk(KERN_WARNING "%d entries for the kdump boot\n",
540 KDUMP_MIN_TCE_ENTRIES);
541 for (index = tbl->it_size - KDUMP_MIN_TCE_ENTRIES;
542 index < tbl->it_size; index++)
543 __clear_bit(index, tbl->it_map);
550 * Build a iommu_table structure. This contains a bit map which
551 * is used to manage allocation of the tce space.
553 struct iommu_table *iommu_init_table(struct iommu_table *tbl, int nid)
556 static int welcomed = 0;
559 struct iommu_pool *p;
561 /* number of bytes needed for the bitmap */
562 sz = (tbl->it_size + 7) >> 3;
564 page = alloc_pages_node(nid, GFP_ATOMIC, get_order(sz));
566 panic("iommu_init_table: Can't allocate %ld bytes\n", sz);
567 tbl->it_map = page_address(page);
568 memset(tbl->it_map, 0, sz);
571 * Reserve page 0 so it will not be used for any mappings.
572 * This avoids buggy drivers that consider page 0 to be invalid
573 * to crash the machine or even lose data.
575 if (tbl->it_offset == 0)
576 set_bit(0, tbl->it_map);
578 /* We only split the IOMMU table if we have 1GB or more of space */
579 if ((tbl->it_size << IOMMU_PAGE_SHIFT) >= (1UL * 1024 * 1024 * 1024))
580 tbl->nr_pools = IOMMU_NR_POOLS;
584 /* We reserve the top 1/4 of the table for large allocations */
585 tbl->poolsize = (tbl->it_size * 3 / 4) / IOMMU_NR_POOLS;
587 for (i = 0; i < IOMMU_NR_POOLS; i++) {
589 spin_lock_init(&(p->lock));
590 p->start = tbl->poolsize * i;
592 p->end = p->start + tbl->poolsize;
595 p = &tbl->large_pool;
596 spin_lock_init(&(p->lock));
597 p->start = tbl->poolsize * i;
599 p->end = tbl->it_size;
601 iommu_table_clear(tbl);
604 printk(KERN_INFO "IOMMU table initialized, virtual merging %s\n",
605 novmerge ? "disabled" : "enabled");
612 void iommu_free_table(struct iommu_table *tbl, const char *node_name)
614 unsigned long bitmap_sz, i;
617 if (!tbl || !tbl->it_map) {
618 printk(KERN_ERR "%s: expected TCE map for %s\n", __func__,
623 /* verify that table contains no entries */
624 /* it_size is in entries, and we're examining 64 at a time */
625 for (i = 0; i < (tbl->it_size/64); i++) {
626 if (tbl->it_map[i] != 0) {
627 printk(KERN_WARNING "%s: Unexpected TCEs for %s\n",
628 __func__, node_name);
633 /* calculate bitmap size in bytes */
634 bitmap_sz = (tbl->it_size + 7) / 8;
637 order = get_order(bitmap_sz);
638 free_pages((unsigned long) tbl->it_map, order);
644 /* Creates TCEs for a user provided buffer. The user buffer must be
645 * contiguous real kernel storage (not vmalloc). The address passed here
646 * comprises a page address and offset into that page. The dma_addr_t
647 * returned will point to the same byte within the page as was passed in.
649 dma_addr_t iommu_map_page(struct device *dev, struct iommu_table *tbl,
650 struct page *page, unsigned long offset, size_t size,
651 unsigned long mask, enum dma_data_direction direction,
652 struct dma_attrs *attrs)
654 dma_addr_t dma_handle = DMA_ERROR_CODE;
657 unsigned int npages, align;
659 BUG_ON(direction == DMA_NONE);
661 vaddr = page_address(page) + offset;
662 uaddr = (unsigned long)vaddr;
663 npages = iommu_num_pages(uaddr, size, IOMMU_PAGE_SIZE);
667 if (IOMMU_PAGE_SHIFT < PAGE_SHIFT && size >= PAGE_SIZE &&
668 ((unsigned long)vaddr & ~PAGE_MASK) == 0)
669 align = PAGE_SHIFT - IOMMU_PAGE_SHIFT;
671 dma_handle = iommu_alloc(dev, tbl, vaddr, npages, direction,
672 mask >> IOMMU_PAGE_SHIFT, align,
674 if (dma_handle == DMA_ERROR_CODE) {
675 if (printk_ratelimit()) {
676 dev_info(dev, "iommu_alloc failed, tbl %p "
677 "vaddr %p npages %d\n", tbl, vaddr,
681 dma_handle |= (uaddr & ~IOMMU_PAGE_MASK);
687 void iommu_unmap_page(struct iommu_table *tbl, dma_addr_t dma_handle,
688 size_t size, enum dma_data_direction direction,
689 struct dma_attrs *attrs)
693 BUG_ON(direction == DMA_NONE);
696 npages = iommu_num_pages(dma_handle, size, IOMMU_PAGE_SIZE);
697 iommu_free(tbl, dma_handle, npages);
701 /* Allocates a contiguous real buffer and creates mappings over it.
702 * Returns the virtual address of the buffer and sets dma_handle
703 * to the dma address (mapping) of the first page.
705 void *iommu_alloc_coherent(struct device *dev, struct iommu_table *tbl,
706 size_t size, dma_addr_t *dma_handle,
707 unsigned long mask, gfp_t flag, int node)
712 unsigned int nio_pages, io_order;
715 size = PAGE_ALIGN(size);
716 order = get_order(size);
719 * Client asked for way too much space. This is checked later
720 * anyway. It is easier to debug here for the drivers than in
723 if (order >= IOMAP_MAX_ORDER) {
724 dev_info(dev, "iommu_alloc_consistent size too large: 0x%lx\n",
732 /* Alloc enough pages (and possibly more) */
733 page = alloc_pages_node(node, flag, order);
736 ret = page_address(page);
737 memset(ret, 0, size);
739 /* Set up tces to cover the allocated range */
740 nio_pages = size >> IOMMU_PAGE_SHIFT;
741 io_order = get_iommu_order(size);
742 mapping = iommu_alloc(dev, tbl, ret, nio_pages, DMA_BIDIRECTIONAL,
743 mask >> IOMMU_PAGE_SHIFT, io_order, NULL);
744 if (mapping == DMA_ERROR_CODE) {
745 free_pages((unsigned long)ret, order);
748 *dma_handle = mapping;
752 void iommu_free_coherent(struct iommu_table *tbl, size_t size,
753 void *vaddr, dma_addr_t dma_handle)
756 unsigned int nio_pages;
758 size = PAGE_ALIGN(size);
759 nio_pages = size >> IOMMU_PAGE_SHIFT;
760 iommu_free(tbl, dma_handle, nio_pages);
761 size = PAGE_ALIGN(size);
762 free_pages((unsigned long)vaddr, get_order(size));