drivers/gpu/drm/i915/intel_dp.c

   1 /*
   2  * Copyright © 2008 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Keith Packard <keithp@keithp.com>
  25  *
  26  */
  27
  28 #include <linux/i2c.h>
  29 #include <linux/slab.h>
  30 #include <linux/export.h>
  31 #include <drm/drmP.h>
  32 #include <drm/drm_crtc.h>
  33 #include <drm/drm_crtc_helper.h>
  34 #include <drm/drm_edid.h>
  35 #include "intel_drv.h"
  36 #include <drm/i915_drm.h>
  37 #include "i915_drv.h"
  38
  39 #define DP_LINK_CHECK_TIMEOUT   (10 * 1000)
  40
  41 /**
  42  * is_edp - is the given port attached to an eDP panel (either CPU or PCH)
  43  * @intel_dp: DP struct
  44  *
  45  * If a CPU or PCH DP output is attached to an eDP panel, this function
  46  * will return true, and false otherwise.
  47  */
  48 static bool is_edp(struct intel_dp *intel_dp)
  49 {
  50         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  51
  52         return intel_dig_port->base.type == INTEL_OUTPUT_EDP;
  53 }
  54
  55 /**
  56  * is_pch_edp - is the port on the PCH and attached to an eDP panel?
  57  * @intel_dp: DP struct
  58  *
  59  * Returns true if the given DP struct corresponds to a PCH DP port attached
  60  * to an eDP panel, false otherwise.  Helpful for determining whether we
  61  * may need FDI resources for a given DP output or not.
  62  */
  63 static bool is_pch_edp(struct intel_dp *intel_dp)
  64 {
  65         return intel_dp->is_pch_edp;
  66 }
  67
  68 /**
  69  * is_cpu_edp - is the port on the CPU and attached to an eDP panel?
  70  * @intel_dp: DP struct
  71  *
  72  * Returns true if the given DP struct corresponds to a CPU eDP port.
  73  */
  74 static bool is_cpu_edp(struct intel_dp *intel_dp)
  75 {
  76         return is_edp(intel_dp) && !is_pch_edp(intel_dp);
  77 }
  78
  79 static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp)
  80 {
  81         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
  82
  83         return intel_dig_port->base.base.dev;
  84 }
  85
  86 static struct intel_dp *intel_attached_dp(struct drm_connector *connector)
  87 {
  88         return enc_to_intel_dp(&intel_attached_encoder(connector)->base);
  89 }
  90
  91 /**
  92  * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP?
  93  * @encoder: DRM encoder
  94  *
  95  * Return true if @encoder corresponds to a PCH attached eDP panel.  Needed
  96  * by intel_display.c.
  97  */
  98 bool intel_encoder_is_pch_edp(struct drm_encoder *encoder)
  99 {
 100         struct intel_dp *intel_dp;
 101
 102         if (!encoder)
 103                 return false;
 104
 105         intel_dp = enc_to_intel_dp(encoder);
 106
 107         return is_pch_edp(intel_dp);
 108 }
 109
 110 static void intel_dp_link_down(struct intel_dp *intel_dp);
 111
 112 void
 113 intel_edp_link_config(struct intel_encoder *intel_encoder,
 114                        int *lane_num, int *link_bw)
 115 {
 116         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 117
 118         *lane_num = intel_dp->lane_count;
 119         *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw);
 120 }
 121
 122 int
 123 intel_edp_target_clock(struct intel_encoder *intel_encoder,
 124                        struct drm_display_mode *mode)
 125 {
 126         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
 127         struct intel_connector *intel_connector = intel_dp->attached_connector;
 128
 129         if (intel_connector->panel.fixed_mode)
 130                 return intel_connector->panel.fixed_mode->clock;
 131         else
 132                 return mode->clock;
 133 }
 134
 135 static int
 136 intel_dp_max_link_bw(struct intel_dp *intel_dp)
 137 {
 138         int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE];
 139
 140         switch (max_link_bw) {
 141         case DP_LINK_BW_1_62:
 142         case DP_LINK_BW_2_7:
 143                 break;
 144         default:
 145                 max_link_bw = DP_LINK_BW_1_62;
 146                 break;
 147         }
 148         return max_link_bw;
 149 }
 150
 151 /*
 152  * The units on the numbers in the next two are... bizarre.  Examples will
 153  * make it clearer; this one parallels an example in the eDP spec.
 154  *
 155  * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as:
 156  *
 157  *     270000 * 1 * 8 / 10 == 216000
 158  *
 159  * The actual data capacity of that configuration is 2.16Gbit/s, so the
 160  * units are decakilobits.  ->clock in a drm_display_mode is in kilohertz -
 161  * or equivalently, kilopixels per second - so for 1680x1050R it'd be
 162  * 119000.  At 18bpp that's 2142000 kilobits per second.
 163  *
 164  * Thus the strange-looking division by 10 in intel_dp_link_required, to
 165  * get the result in decakilobits instead of kilobits.
 166  */
 167
 168 static int
 169 intel_dp_link_required(int pixel_clock, int bpp)
 170 {
 171         return (pixel_clock * bpp + 9) / 10;
 172 }
 173
 174 static int
 175 intel_dp_max_data_rate(int max_link_clock, int max_lanes)
 176 {
 177         return (max_link_clock * max_lanes * 8) / 10;
 178 }
 179
 180 static bool
 181 intel_dp_adjust_dithering(struct intel_dp *intel_dp,
 182                           struct drm_display_mode *mode,
 183                           bool adjust_mode)
 184 {
 185         int max_link_clock =
 186                 drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp));
 187         int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd);
 188         int max_rate, mode_rate;
 189
 190         mode_rate = intel_dp_link_required(mode->clock, 24);
 191         max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes);
 192
 193         if (mode_rate > max_rate) {
 194                 mode_rate = intel_dp_link_required(mode->clock, 18);
 195                 if (mode_rate > max_rate)
 196                         return false;
 197
 198                 if (adjust_mode)
 199                         mode->private_flags
 200                                 |= INTEL_MODE_DP_FORCE_6BPC;
 201
 202                 return true;
 203         }
 204
 205         return true;
 206 }
 207
 208 static int
 209 intel_dp_mode_valid(struct drm_connector *connector,
 210                     struct drm_display_mode *mode)
 211 {
 212         struct intel_dp *intel_dp = intel_attached_dp(connector);
 213         struct intel_connector *intel_connector = to_intel_connector(connector);
 214         struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
 215
 216         if (is_edp(intel_dp) && fixed_mode) {
 217                 if (mode->hdisplay > fixed_mode->hdisplay)
 218                         return MODE_PANEL;
 219
 220                 if (mode->vdisplay > fixed_mode->vdisplay)
 221                         return MODE_PANEL;
 222         }
 223
 224         if (!intel_dp_adjust_dithering(intel_dp, mode, false))
 225                 return MODE_CLOCK_HIGH;
 226
 227         if (mode->clock < 10000)
 228                 return MODE_CLOCK_LOW;
 229
 230         if (mode->flags & DRM_MODE_FLAG_DBLCLK)
 231                 return MODE_H_ILLEGAL;
 232
 233         return MODE_OK;
 234 }
 235
 236 static uint32_t
 237 pack_aux(uint8_t *src, int src_bytes)
 238 {
 239         int     i;
 240         uint32_t v = 0;
 241
 242         if (src_bytes > 4)
 243                 src_bytes = 4;
 244         for (i = 0; i < src_bytes; i++)
 245                 v |= ((uint32_t) src[i]) << ((3-i) * 8);
 246         return v;
 247 }
 248
 249 static void
 250 unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes)
 251 {
 252         int i;
 253         if (dst_bytes > 4)
 254                 dst_bytes = 4;
 255         for (i = 0; i < dst_bytes; i++)
 256                 dst[i] = src >> ((3-i) * 8);
 257 }
 258
 259 /* hrawclock is 1/4 the FSB frequency */
 260 static int
 261 intel_hrawclk(struct drm_device *dev)
 262 {
 263         struct drm_i915_private *dev_priv = dev->dev_private;
 264         uint32_t clkcfg;
 265
 266         /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */
 267         if (IS_VALLEYVIEW(dev))
 268                 return 200;
 269
 270         clkcfg = I915_READ(CLKCFG);
 271         switch (clkcfg & CLKCFG_FSB_MASK) {
 272         case CLKCFG_FSB_400:
 273                 return 100;
 274         case CLKCFG_FSB_533:
 275                 return 133;
 276         case CLKCFG_FSB_667:
 277                 return 166;
 278         case CLKCFG_FSB_800:
 279                 return 200;
 280         case CLKCFG_FSB_1067:
 281                 return 266;
 282         case CLKCFG_FSB_1333:
 283                 return 333;
 284         /* these two are just a guess; one of them might be right */
 285         case CLKCFG_FSB_1600:
 286         case CLKCFG_FSB_1600_ALT:
 287                 return 400;
 288         default:
 289                 return 133;
 290         }
 291 }
 292
 293 static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp)
 294 {
 295         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 296         struct drm_i915_private *dev_priv = dev->dev_private;
 297
 298         return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0;
 299 }
 300
 301 static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp)
 302 {
 303         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 304         struct drm_i915_private *dev_priv = dev->dev_private;
 305
 306         return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0;
 307 }
 308
 309 static void
 310 intel_dp_check_edp(struct intel_dp *intel_dp)
 311 {
 312         struct drm_device *dev = intel_dp_to_dev(intel_dp);
 313         struct drm_i915_private *dev_priv = dev->dev_private;
 314
 315         if (!is_edp(intel_dp))
 316                 return;
 317         if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) {
 318                 WARN(1, "eDP powered off while attempting aux channel communication.\n");
 319                 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n",
 320                               I915_READ(PCH_PP_STATUS),
 321                               I915_READ(PCH_PP_CONTROL));
 322         }
 323 }
 324
 325 static uint32_t
 326 intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq)
 327 {
 328         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 329         struct drm_device *dev = intel_dig_port->base.base.dev;
 330         struct drm_i915_private *dev_priv = dev->dev_private;
 331         uint32_t ch_ctl = intel_dp->output_reg + 0x10;
 332         uint32_t status;
 333         bool done;
 334
 335         if (HAS_DDI(dev)) {
 336                 switch (intel_dig_port->port) {
 337                 case PORT_A:
 338                         ch_ctl = DPA_AUX_CH_CTL;
 339                         break;
 340                 case PORT_B:
 341                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 342                         break;
 343                 case PORT_C:
 344                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 345                         break;
 346                 case PORT_D:
 347                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 348                         break;
 349                 default:
 350                         BUG();
 351                 }
 352         }
 353
 354 #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 355         if (has_aux_irq)
 356                 done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, 10);
 357         else
 358                 done = wait_for_atomic(C, 10) == 0;
 359         if (!done)
 360                 DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n",
 361                           has_aux_irq);
 362 #undef C
 363
 364         return status;
 365 }
 366
 367 static int
 368 intel_dp_aux_ch(struct intel_dp *intel_dp,
 369                 uint8_t *send, int send_bytes,
 370                 uint8_t *recv, int recv_size)
 371 {
 372         uint32_t output_reg = intel_dp->output_reg;
 373         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
 374         struct drm_device *dev = intel_dig_port->base.base.dev;
 375         struct drm_i915_private *dev_priv = dev->dev_private;
 376         uint32_t ch_ctl = output_reg + 0x10;
 377         uint32_t ch_data = ch_ctl + 4;
 378         int i, ret, recv_bytes;
 379         uint32_t status;
 380         uint32_t aux_clock_divider;
 381         int try, precharge;
 382         bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev);
 383
 384         /* dp aux is extremely sensitive to irq latency, hence request the
 385          * lowest possible wakeup latency and so prevent the cpu from going into
 386          * deep sleep states.
 387          */
 388         pm_qos_update_request(&dev_priv->pm_qos, 0);
 389
 390         if (HAS_DDI(dev)) {
 391                 switch (intel_dig_port->port) {
 392                 case PORT_A:
 393                         ch_ctl = DPA_AUX_CH_CTL;
 394                         ch_data = DPA_AUX_CH_DATA1;
 395                         break;
 396                 case PORT_B:
 397                         ch_ctl = PCH_DPB_AUX_CH_CTL;
 398                         ch_data = PCH_DPB_AUX_CH_DATA1;
 399                         break;
 400                 case PORT_C:
 401                         ch_ctl = PCH_DPC_AUX_CH_CTL;
 402                         ch_data = PCH_DPC_AUX_CH_DATA1;
 403                         break;
 404                 case PORT_D:
 405                         ch_ctl = PCH_DPD_AUX_CH_CTL;
 406                         ch_data = PCH_DPD_AUX_CH_DATA1;
 407                         break;
 408                 default:
 409                         BUG();
 410                 }
 411         }
 412
 413         intel_dp_check_edp(intel_dp);
 414         /* The clock divider is based off the hrawclk,
 415          * and would like to run at 2MHz. So, take the
 416          * hrawclk value and divide by 2 and use that
 417          *
 418          * Note that PCH attached eDP panels should use a 125MHz input
 419          * clock divider.
 420          */
 421         if (is_cpu_edp(intel_dp)) {
 422                 if (HAS_DDI(dev))
 423                         aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1;
 424                 else if (IS_VALLEYVIEW(dev))
 425                         aux_clock_divider = 100;
 426                 else if (IS_GEN6(dev) || IS_GEN7(dev))
 427                         aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */
 428                 else
 429                         aux_clock_divider = 225; /* eDP input clock at 450Mhz */
 430         } else if (HAS_PCH_SPLIT(dev))
 431                 aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2);
 432         else
 433                 aux_clock_divider = intel_hrawclk(dev) / 2;
 434
 435         if (IS_GEN6(dev))
 436                 precharge = 3;
 437         else
 438                 precharge = 5;
 439
 440         /* Try to wait for any previous AUX channel activity */
 441         for (try = 0; try < 3; try++) {
 442                 status = I915_READ_NOTRACE(ch_ctl);
 443                 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0)
 444                         break;
 445                 msleep(1);
 446         }
 447
 448         if (try == 3) {
 449                 WARN(1, "dp_aux_ch not started status 0x%08x\n",
 450                      I915_READ(ch_ctl));
 451                 ret = -EBUSY;
 452                 goto out;
 453         }
 454
 455         /* Must try at least 3 times according to DP spec */
 456         for (try = 0; try < 5; try++) {
 457                 /* Load the send data into the aux channel data registers */
 458                 for (i = 0; i < send_bytes; i += 4)
 459                         I915_WRITE(ch_data + i,
 460                                    pack_aux(send + i, send_bytes - i));
 461
 462                 /* Send the command and wait for it to complete */
 463                 I915_WRITE(ch_ctl,
 464                            DP_AUX_CH_CTL_SEND_BUSY |
 465                            (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) |
 466                            DP_AUX_CH_CTL_TIME_OUT_400us |
 467                            (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
 468                            (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
 469                            (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) |
 470                            DP_AUX_CH_CTL_DONE |
 471                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 472                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 473
 474                 status = intel_dp_aux_wait_done(intel_dp, has_aux_irq);
 475
 476                 /* Clear done status and any errors */
 477                 I915_WRITE(ch_ctl,
 478                            status |
 479                            DP_AUX_CH_CTL_DONE |
 480                            DP_AUX_CH_CTL_TIME_OUT_ERROR |
 481                            DP_AUX_CH_CTL_RECEIVE_ERROR);
 482
 483                 if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR |
 484                               DP_AUX_CH_CTL_RECEIVE_ERROR))
 485                         continue;
 486                 if (status & DP_AUX_CH_CTL_DONE)
 487                         break;
 488         }
 489
 490         if ((status & DP_AUX_CH_CTL_DONE) == 0) {
 491                 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status);
 492                 ret = -EBUSY;
 493                 goto out;
 494         }
 495
 496         /* Check for timeout or receive error.
 497          * Timeouts occur when the sink is not connected
 498          */
 499         if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) {
 500                 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status);
 501                 ret = -EIO;
 502                 goto out;
 503         }
 504
 505         /* Timeouts occur when the device isn't connected, so they're
 506          * "normal" -- don't fill the kernel log with these */
 507         if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) {
 508                 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status);
 509                 ret = -ETIMEDOUT;
 510                 goto out;
 511         }
 512
 513         /* Unload any bytes sent back from the other side */
 514         recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >>
 515                       DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
 516         if (recv_bytes > recv_size)
 517                 recv_bytes = recv_size;
 518
 519         for (i = 0; i < recv_bytes; i += 4)
 520                 unpack_aux(I915_READ(ch_data + i),
 521                            recv + i, recv_bytes - i);
 522
 523         ret = recv_bytes;
 524 out:
 525         pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE);
 526
 527         return ret;
 528 }
 529
 530 /* Write data to the aux channel in native mode */
 531 static int
 532 intel_dp_aux_native_write(struct intel_dp *intel_dp,
 533                           uint16_t address, uint8_t *send, int send_bytes)
 534 {
 535         int ret;
 536         uint8_t msg[20];
 537         int msg_bytes;
 538         uint8_t ack;
 539
 540         intel_dp_check_edp(intel_dp);
 541         if (send_bytes > 16)
 542                 return -1;
 543         msg[0] = AUX_NATIVE_WRITE << 4;
 544         msg[1] = address >> 8;
 545         msg[2] = address & 0xff;
 546         msg[3] = send_bytes - 1;
 547         memcpy(&msg[4], send, send_bytes);
 548         msg_bytes = send_bytes + 4;
 549         for (;;) {
 550                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1);
 551                 if (ret < 0)
 552                         return ret;
 553                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK)
 554                         break;
 555                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 556                         udelay(100);
 557                 else
 558                         return -EIO;
 559         }
 560         return send_bytes;
 561 }
 562
 563 /* Write a single byte to the aux channel in native mode */
 564 static int
 565 intel_dp_aux_native_write_1(struct intel_dp *intel_dp,
 566                             uint16_t address, uint8_t byte)
 567 {
 568         return intel_dp_aux_native_write(intel_dp, address, &byte, 1);
 569 }
 570
 571 /* read bytes from a native aux channel */
 572 static int
 573 intel_dp_aux_native_read(struct intel_dp *intel_dp,
 574                          uint16_t address, uint8_t *recv, int recv_bytes)
 575 {
 576         uint8_t msg[4];
 577         int msg_bytes;
 578         uint8_t reply[20];
 579         int reply_bytes;
 580         uint8_t ack;
 581         int ret;
 582
 583         intel_dp_check_edp(intel_dp);
 584         msg[0] = AUX_NATIVE_READ << 4;
 585         msg[1] = address >> 8;
 586         msg[2] = address & 0xff;
 587         msg[3] = recv_bytes - 1;
 588
 589         msg_bytes = 4;
 590         reply_bytes = recv_bytes + 1;
 591
 592         for (;;) {
 593                 ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes,
 594                                       reply, reply_bytes);
 595                 if (ret == 0)
 596                         return -EPROTO;
 597                 if (ret < 0)
 598                         return ret;
 599                 ack = reply[0];
 600                 if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) {
 601                         memcpy(recv, reply + 1, ret - 1);
 602                         return ret - 1;
 603                 }
 604                 else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER)
 605                         udelay(100);
 606                 else
 607                         return -EIO;
 608         }
 609 }
 610
 611 static int
 612 intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode,
 613                     uint8_t write_byte, uint8_t *read_byte)
 614 {
 615         struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data;
 616         struct intel_dp *intel_dp = container_of(adapter,
 617                                                 struct intel_dp,
 618                                                 adapter);
 619         uint16_t address = algo_data->address;
 620         uint8_t msg[5];
 621         uint8_t reply[2];
 622         unsigned retry;
 623         int msg_bytes;
 624         int reply_bytes;
 625         int ret;
 626
 627         intel_dp_check_edp(intel_dp);
 628         /* Set up the command byte */
 629         if (mode & MODE_I2C_READ)
 630                 msg[0] = AUX_I2C_READ << 4;
 631         else
 632                 msg[0] = AUX_I2C_WRITE << 4;
 633
 634         if (!(mode & MODE_I2C_STOP))
 635                 msg[0] |= AUX_I2C_MOT << 4;
 636
 637         msg[1] = address >> 8;
 638         msg[2] = address;
 639
 640         switch (mode) {
 641         case MODE_I2C_WRITE:
 642                 msg[3] = 0;
 643                 msg[4] = write_byte;
 644                 msg_bytes = 5;
 645                 reply_bytes = 1;
 646                 break;
 647         case MODE_I2C_READ:
 648                 msg[3] = 0;
 649                 msg_bytes = 4;
 650                 reply_bytes = 2;
 651                 break;
 652         default:
 653                 msg_bytes = 3;
 654                 reply_bytes = 1;
 655                 break;
 656         }
 657
 658         for (retry = 0; retry < 5; retry++) {
 659                 ret = intel_dp_aux_ch(intel_dp,
 660                                       msg, msg_bytes,
 661                                       reply, reply_bytes);
 662                 if (ret < 0) {
 663                         DRM_DEBUG_KMS("aux_ch failed %d\n", ret);
 664                         return ret;
 665                 }
 666
 667                 switch (reply[0] & AUX_NATIVE_REPLY_MASK) {
 668                 case AUX_NATIVE_REPLY_ACK:
 669                         /* I2C-over-AUX Reply field is only valid
 670                          * when paired with AUX ACK.
 671                          */
 672                         break;
 673                 case AUX_NATIVE_REPLY_NACK:
 674                         DRM_DEBUG_KMS("aux_ch native nack\n");
 675                         return -EREMOTEIO;
 676                 case AUX_NATIVE_REPLY_DEFER:
 677                         udelay(100);
 678                         continue;
 679                 default:
 680                         DRM_ERROR("aux_ch invalid native reply 0x%02x\n",
 681                                   reply[0]);
 682                         return -EREMOTEIO;
 683                 }
 684
 685                 switch (reply[0] & AUX_I2C_REPLY_MASK) {
 686                 case AUX_I2C_REPLY_ACK:
 687                         if (mode == MODE_I2C_READ) {
 688                                 *read_byte = reply[1];
 689                         }
 690                         return reply_bytes - 1;
 691                 case AUX_I2C_REPLY_NACK:
 692                         DRM_DEBUG_KMS("aux_i2c nack\n");
 693                         return -EREMOTEIO;
 694                 case AUX_I2C_REPLY_DEFER:
 695                         DRM_DEBUG_KMS("aux_i2c defer\n");
 696                         udelay(100);
 697                         break;
 698                 default:
 699                         DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]);
 700                         return -EREMOTEIO;
 701                 }
 702         }
 703
 704         DRM_ERROR("too many retries, giving up\n");
 705         return -EREMOTEIO;
 706 }
 707
 708 static int
 709 intel_dp_i2c_init(struct intel_dp *intel_dp,
 710                   struct intel_connector *intel_connector, const char *name)
 711 {
 712         int     ret;
 713
 714         DRM_DEBUG_KMS("i2c_init %s\n", name);
 715         intel_dp->algo.running = false;
 716         intel_dp->algo.address = 0;
 717         intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch;
 718
 719         memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter));
 720         intel_dp->adapter.owner = THIS_MODULE;
 721         intel_dp->adapter.class = I2C_CLASS_DDC;
 722         strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1);
 723         intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0';
 724         intel_dp->adapter.algo_data = &intel_dp->algo;
 725         intel_dp->adapter.dev.parent = &intel_connector->base.kdev;
 726
 727         ironlake_edp_panel_vdd_on(intel_dp);
 728         ret = i2c_dp_aux_add_bus(&intel_dp->adapter);
 729         ironlake_edp_panel_vdd_off(intel_dp, false);
 730         return ret;
 731 }
 732
 733 bool
 734 intel_dp_mode_fixup(struct drm_encoder *encoder,
 735                     const struct drm_display_mode *mode,
 736                     struct drm_display_mode *adjusted_mode)
 737 {
 738         struct drm_device *dev = encoder->dev;
 739         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 740         struct intel_connector *intel_connector = intel_dp->attached_connector;
 741         int lane_count, clock;
 742         int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd);
 743         int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0;
 744         int bpp, mode_rate;
 745         static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 };
 746
 747         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
 748                 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
 749                                        adjusted_mode);
 750                 intel_pch_panel_fitting(dev,
 751                                         intel_connector->panel.fitting_mode,
 752                                         mode, adjusted_mode);
 753         }
 754
 755         if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK)
 756                 return false;
 757
 758         DRM_DEBUG_KMS("DP link computation with max lane count %i "
 759                       "max bw %02x pixel clock %iKHz\n",
 760                       max_lane_count, bws[max_clock], adjusted_mode->clock);
 761
 762         if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true))
 763                 return false;
 764
 765         bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24;
 766
 767         if (intel_dp->color_range_auto) {
 768                 /*
 769                  * See:
 770                  * CEA-861-E - 5.1 Default Encoding Parameters
 771                  * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry
 772                  */
 773                 if (bpp != 18 && drm_mode_cea_vic(adjusted_mode) > 1)
 774                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
 775                 else
 776                         intel_dp->color_range = 0;
 777         }
 778
 779         if (intel_dp->color_range)
 780                 adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE;
 781
 782         mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp);
 783
 784         for (clock = 0; clock <= max_clock; clock++) {
 785                 for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) {
 786                         int link_bw_clock =
 787                                 drm_dp_bw_code_to_link_rate(bws[clock]);
 788                         int link_avail = intel_dp_max_data_rate(link_bw_clock,
 789                                                                 lane_count);
 790
 791                         if (mode_rate <= link_avail) {
 792                                 intel_dp->link_bw = bws[clock];
 793                                 intel_dp->lane_count = lane_count;
 794                                 adjusted_mode->clock = link_bw_clock;
 795                                 DRM_DEBUG_KMS("DP link bw %02x lane "
 796                                                 "count %d clock %d bpp %d\n",
 797                                        intel_dp->link_bw, intel_dp->lane_count,
 798                                        adjusted_mode->clock, bpp);
 799                                 DRM_DEBUG_KMS("DP link bw required %i available %i\n",
 800                                               mode_rate, link_avail);
 801                                 return true;
 802                         }
 803                 }
 804         }
 805
 806         return false;
 807 }
 808
 809 void
 810 intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode,
 811                  struct drm_display_mode *adjusted_mode)
 812 {
 813         struct drm_device *dev = crtc->dev;
 814         struct intel_encoder *intel_encoder;
 815         struct intel_dp *intel_dp;
 816         struct drm_i915_private *dev_priv = dev->dev_private;
 817         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 818         int lane_count = 4;
 819         struct intel_link_m_n m_n;
 820         int pipe = intel_crtc->pipe;
 821         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
 822
 823         /*
 824          * Find the lane count in the intel_encoder private
 825          */
 826         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
 827                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
 828
 829                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
 830                     intel_encoder->type == INTEL_OUTPUT_EDP)
 831                 {
 832                         lane_count = intel_dp->lane_count;
 833                         break;
 834                 }
 835         }
 836
 837         /*
 838          * Compute the GMCH and Link ratios. The '3' here is
 839          * the number of bytes_per_pixel post-LUT, which we always
 840          * set up for 8-bits of R/G/B, or 3 bytes total.
 841          */
 842         intel_link_compute_m_n(intel_crtc->bpp, lane_count,
 843                                mode->clock, adjusted_mode->clock, &m_n);
 844
 845         if (HAS_DDI(dev)) {
 846                 I915_WRITE(PIPE_DATA_M1(cpu_transcoder),
 847                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 848                 I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
 849                 I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
 850                 I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
 851         } else if (HAS_PCH_SPLIT(dev)) {
 852                 I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 853                 I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n);
 854                 I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m);
 855                 I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n);
 856         } else if (IS_VALLEYVIEW(dev)) {
 857                 I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m);
 858                 I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n);
 859                 I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m);
 860                 I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n);
 861         } else {
 862                 I915_WRITE(PIPE_GMCH_DATA_M(pipe),
 863                            TU_SIZE(m_n.tu) | m_n.gmch_m);
 864                 I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n);
 865                 I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m);
 866                 I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n);
 867         }
 868 }
 869
 870 void intel_dp_init_link_config(struct intel_dp *intel_dp)
 871 {
 872         memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE);
 873         intel_dp->link_configuration[0] = intel_dp->link_bw;
 874         intel_dp->link_configuration[1] = intel_dp->lane_count;
 875         intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B;
 876         /*
 877          * Check for DPCD version > 1.1 and enhanced framing support
 878          */
 879         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
 880             (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) {
 881                 intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
 882         }
 883 }
 884
 885 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
 886 {
 887         struct drm_device *dev = crtc->dev;
 888         struct drm_i915_private *dev_priv = dev->dev_private;
 889         u32 dpa_ctl;
 890
 891         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
 892         dpa_ctl = I915_READ(DP_A);
 893         dpa_ctl &= ~DP_PLL_FREQ_MASK;
 894
 895         if (clock < 200000) {
 896                 /* For a long time we've carried around a ILK-DevA w/a for the
 897                  * 160MHz clock. If we're really unlucky, it's still required.
 898                  */
 899                 DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n");
 900                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
 901         } else {
 902                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
 903         }
 904
 905         I915_WRITE(DP_A, dpa_ctl);
 906
 907         POSTING_READ(DP_A);
 908         udelay(500);
 909 }
 910
 911 static void
 912 intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode,
 913                   struct drm_display_mode *adjusted_mode)
 914 {
 915         struct drm_device *dev = encoder->dev;
 916         struct drm_i915_private *dev_priv = dev->dev_private;
 917         struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
 918         struct drm_crtc *crtc = encoder->crtc;
 919         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 920
 921         /*
 922          * There are four kinds of DP registers:
 923          *
 924          *      IBX PCH
 925          *      SNB CPU
 926          *      IVB CPU
 927          *      CPT PCH
 928          *
 929          * IBX PCH and CPU are the same for almost everything,
 930          * except that the CPU DP PLL is configured in this
 931          * register
 932          *
 933          * CPT PCH is quite different, having many bits moved
 934          * to the TRANS_DP_CTL register instead. That
 935          * configuration happens (oddly) in ironlake_pch_enable
 936          */
 937
 938         /* Preserve the BIOS-computed detected bit. This is
 939          * supposed to be read-only.
 940          */
 941         intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED;
 942
 943         /* Handle DP bits in common between all three register formats */
 944         intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0;
 945
 946         switch (intel_dp->lane_count) {
 947         case 1:
 948                 intel_dp->DP |= DP_PORT_WIDTH_1;
 949                 break;
 950         case 2:
 951                 intel_dp->DP |= DP_PORT_WIDTH_2;
 952                 break;
 953         case 4:
 954                 intel_dp->DP |= DP_PORT_WIDTH_4;
 955                 break;
 956         }
 957         if (intel_dp->has_audio) {
 958                 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n",
 959                                  pipe_name(intel_crtc->pipe));
 960                 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE;
 961                 intel_write_eld(encoder, adjusted_mode);
 962         }
 963
 964         intel_dp_init_link_config(intel_dp);
 965
 966         /* Split out the IBX/CPU vs CPT settings */
 967
 968         if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) {
 969                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 970                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 971                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 972                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 973                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
 974
 975                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 976                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 977
 978                 intel_dp->DP |= intel_crtc->pipe << 29;
 979
 980                 /* don't miss out required setting for eDP */
 981                 if (adjusted_mode->clock < 200000)
 982                         intel_dp->DP |= DP_PLL_FREQ_160MHZ;
 983                 else
 984                         intel_dp->DP |= DP_PLL_FREQ_270MHZ;
 985         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
 986                 if (!HAS_PCH_SPLIT(dev))
 987                         intel_dp->DP |= intel_dp->color_range;
 988
 989                 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
 990                         intel_dp->DP |= DP_SYNC_HS_HIGH;
 991                 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
 992                         intel_dp->DP |= DP_SYNC_VS_HIGH;
 993                 intel_dp->DP |= DP_LINK_TRAIN_OFF;
 994
 995                 if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN)
 996                         intel_dp->DP |= DP_ENHANCED_FRAMING;
 997
 998                 if (intel_crtc->pipe == 1)
 999                         intel_dp->DP |= DP_PIPEB_SELECT;
1000
1001                 if (is_cpu_edp(intel_dp)) {
1002                         /* don't miss out required setting for eDP */
1003                         if (adjusted_mode->clock < 200000)
1004                                 intel_dp->DP |= DP_PLL_FREQ_160MHZ;
1005                         else
1006                                 intel_dp->DP |= DP_PLL_FREQ_270MHZ;
1007                 }
1008         } else {
1009                 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT;
1010         }
1011
1012         if (is_cpu_edp(intel_dp))
1013                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
1014 }
1015
1016 #define IDLE_ON_MASK            (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1017 #define IDLE_ON_VALUE           (PP_ON | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_ON_IDLE)
1018
1019 #define IDLE_OFF_MASK           (PP_ON | 0        | PP_SEQUENCE_MASK | 0                     | PP_SEQUENCE_STATE_MASK)
1020 #define IDLE_OFF_VALUE          (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1021
1022 #define IDLE_CYCLE_MASK         (PP_ON | 0        | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK)
1023 #define IDLE_CYCLE_VALUE        (0     | 0        | PP_SEQUENCE_NONE | 0                     | PP_SEQUENCE_STATE_OFF_IDLE)
1024
1025 static void ironlake_wait_panel_status(struct intel_dp *intel_dp,
1026                                        u32 mask,
1027                                        u32 value)
1028 {
1029         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1030         struct drm_i915_private *dev_priv = dev->dev_private;
1031
1032         DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n",
1033                       mask, value,
1034                       I915_READ(PCH_PP_STATUS),
1035                       I915_READ(PCH_PP_CONTROL));
1036
1037         if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) {
1038                 DRM_ERROR("Panel status timeout: status %08x control %08x\n",
1039                           I915_READ(PCH_PP_STATUS),
1040                           I915_READ(PCH_PP_CONTROL));
1041         }
1042 }
1043
1044 static void ironlake_wait_panel_on(struct intel_dp *intel_dp)
1045 {
1046         DRM_DEBUG_KMS("Wait for panel power on\n");
1047         ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE);
1048 }
1049
1050 static void ironlake_wait_panel_off(struct intel_dp *intel_dp)
1051 {
1052         DRM_DEBUG_KMS("Wait for panel power off time\n");
1053         ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE);
1054 }
1055
1056 static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp)
1057 {
1058         DRM_DEBUG_KMS("Wait for panel power cycle\n");
1059         ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE);
1060 }
1061
1062
1063 /* Read the current pp_control value, unlocking the register if it
1064  * is locked
1065  */
1066
1067 static  u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv)
1068 {
1069         u32     control = I915_READ(PCH_PP_CONTROL);
1070
1071         control &= ~PANEL_UNLOCK_MASK;
1072         control |= PANEL_UNLOCK_REGS;
1073         return control;
1074 }
1075
1076 void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp)
1077 {
1078         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1079         struct drm_i915_private *dev_priv = dev->dev_private;
1080         u32 pp;
1081
1082         if (!is_edp(intel_dp))
1083                 return;
1084         DRM_DEBUG_KMS("Turn eDP VDD on\n");
1085
1086         WARN(intel_dp->want_panel_vdd,
1087              "eDP VDD already requested on\n");
1088
1089         intel_dp->want_panel_vdd = true;
1090
1091         if (ironlake_edp_have_panel_vdd(intel_dp)) {
1092                 DRM_DEBUG_KMS("eDP VDD already on\n");
1093                 return;
1094         }
1095
1096         if (!ironlake_edp_have_panel_power(intel_dp))
1097                 ironlake_wait_panel_power_cycle(intel_dp);
1098
1099         pp = ironlake_get_pp_control(dev_priv);
1100         pp |= EDP_FORCE_VDD;
1101         I915_WRITE(PCH_PP_CONTROL, pp);
1102         POSTING_READ(PCH_PP_CONTROL);
1103         DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1104                       I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1105
1106         /*
1107          * If the panel wasn't on, delay before accessing aux channel
1108          */
1109         if (!ironlake_edp_have_panel_power(intel_dp)) {
1110                 DRM_DEBUG_KMS("eDP was not running\n");
1111                 msleep(intel_dp->panel_power_up_delay);
1112         }
1113 }
1114
1115 static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp)
1116 {
1117         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1118         struct drm_i915_private *dev_priv = dev->dev_private;
1119         u32 pp;
1120
1121         WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
1122
1123         if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) {
1124                 pp = ironlake_get_pp_control(dev_priv);
1125                 pp &= ~EDP_FORCE_VDD;
1126                 I915_WRITE(PCH_PP_CONTROL, pp);
1127                 POSTING_READ(PCH_PP_CONTROL);
1128
1129                 /* Make sure sequencer is idle before allowing subsequent activity */
1130                 DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n",
1131                               I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL));
1132
1133                 msleep(intel_dp->panel_power_down_delay);
1134         }
1135 }
1136
1137 static void ironlake_panel_vdd_work(struct work_struct *__work)
1138 {
1139         struct intel_dp *intel_dp = container_of(to_delayed_work(__work),
1140                                                  struct intel_dp, panel_vdd_work);
1141         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1142
1143         mutex_lock(&dev->mode_config.mutex);
1144         ironlake_panel_vdd_off_sync(intel_dp);
1145         mutex_unlock(&dev->mode_config.mutex);
1146 }
1147
1148 void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync)
1149 {
1150         if (!is_edp(intel_dp))
1151                 return;
1152
1153         DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd);
1154         WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on");
1155
1156         intel_dp->want_panel_vdd = false;
1157
1158         if (sync) {
1159                 ironlake_panel_vdd_off_sync(intel_dp);
1160         } else {
1161                 /*
1162                  * Queue the timer to fire a long
1163                  * time from now (relative to the power down delay)
1164                  * to keep the panel power up across a sequence of operations
1165                  */
1166                 schedule_delayed_work(&intel_dp->panel_vdd_work,
1167                                       msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5));
1168         }
1169 }
1170
1171 void ironlake_edp_panel_on(struct intel_dp *intel_dp)
1172 {
1173         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1174         struct drm_i915_private *dev_priv = dev->dev_private;
1175         u32 pp;
1176
1177         if (!is_edp(intel_dp))
1178                 return;
1179
1180         DRM_DEBUG_KMS("Turn eDP power on\n");
1181
1182         if (ironlake_edp_have_panel_power(intel_dp)) {
1183                 DRM_DEBUG_KMS("eDP power already on\n");
1184                 return;
1185         }
1186
1187         ironlake_wait_panel_power_cycle(intel_dp);
1188
1189         pp = ironlake_get_pp_control(dev_priv);
1190         if (IS_GEN5(dev)) {
1191                 /* ILK workaround: disable reset around power sequence */
1192                 pp &= ~PANEL_POWER_RESET;
1193                 I915_WRITE(PCH_PP_CONTROL, pp);
1194                 POSTING_READ(PCH_PP_CONTROL);
1195         }
1196
1197         pp |= POWER_TARGET_ON;
1198         if (!IS_GEN5(dev))
1199                 pp |= PANEL_POWER_RESET;
1200
1201         I915_WRITE(PCH_PP_CONTROL, pp);
1202         POSTING_READ(PCH_PP_CONTROL);
1203
1204         ironlake_wait_panel_on(intel_dp);
1205
1206         if (IS_GEN5(dev)) {
1207                 pp |= PANEL_POWER_RESET; /* restore panel reset bit */
1208                 I915_WRITE(PCH_PP_CONTROL, pp);
1209                 POSTING_READ(PCH_PP_CONTROL);
1210         }
1211 }
1212
1213 void ironlake_edp_panel_off(struct intel_dp *intel_dp)
1214 {
1215         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1216         struct drm_i915_private *dev_priv = dev->dev_private;
1217         u32 pp;
1218
1219         if (!is_edp(intel_dp))
1220                 return;
1221
1222         DRM_DEBUG_KMS("Turn eDP power off\n");
1223
1224         WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n");
1225
1226         pp = ironlake_get_pp_control(dev_priv);
1227         /* We need to switch off panel power _and_ force vdd, for otherwise some
1228          * panels get very unhappy and cease to work. */
1229         pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE);
1230         I915_WRITE(PCH_PP_CONTROL, pp);
1231         POSTING_READ(PCH_PP_CONTROL);
1232
1233         intel_dp->want_panel_vdd = false;
1234
1235         ironlake_wait_panel_off(intel_dp);
1236 }
1237
1238 void ironlake_edp_backlight_on(struct intel_dp *intel_dp)
1239 {
1240         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1241         struct drm_device *dev = intel_dig_port->base.base.dev;
1242         struct drm_i915_private *dev_priv = dev->dev_private;
1243         int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe;
1244         u32 pp;
1245
1246         if (!is_edp(intel_dp))
1247                 return;
1248
1249         DRM_DEBUG_KMS("\n");
1250         /*
1251          * If we enable the backlight right away following a panel power
1252          * on, we may see slight flicker as the panel syncs with the eDP
1253          * link.  So delay a bit to make sure the image is solid before
1254          * allowing it to appear.
1255          */
1256         msleep(intel_dp->backlight_on_delay);
1257         pp = ironlake_get_pp_control(dev_priv);
1258         pp |= EDP_BLC_ENABLE;
1259         I915_WRITE(PCH_PP_CONTROL, pp);
1260         POSTING_READ(PCH_PP_CONTROL);
1261
1262         intel_panel_enable_backlight(dev, pipe);
1263 }
1264
1265 void ironlake_edp_backlight_off(struct intel_dp *intel_dp)
1266 {
1267         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1268         struct drm_i915_private *dev_priv = dev->dev_private;
1269         u32 pp;
1270
1271         if (!is_edp(intel_dp))
1272                 return;
1273
1274         intel_panel_disable_backlight(dev);
1275
1276         DRM_DEBUG_KMS("\n");
1277         pp = ironlake_get_pp_control(dev_priv);
1278         pp &= ~EDP_BLC_ENABLE;
1279         I915_WRITE(PCH_PP_CONTROL, pp);
1280         POSTING_READ(PCH_PP_CONTROL);
1281         msleep(intel_dp->backlight_off_delay);
1282 }
1283
1284 static void ironlake_edp_pll_on(struct intel_dp *intel_dp)
1285 {
1286         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1287         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1288         struct drm_device *dev = crtc->dev;
1289         struct drm_i915_private *dev_priv = dev->dev_private;
1290         u32 dpa_ctl;
1291
1292         assert_pipe_disabled(dev_priv,
1293                              to_intel_crtc(crtc)->pipe);
1294
1295         DRM_DEBUG_KMS("\n");
1296         dpa_ctl = I915_READ(DP_A);
1297         WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n");
1298         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1299
1300         /* We don't adjust intel_dp->DP while tearing down the link, to
1301          * facilitate link retraining (e.g. after hotplug). Hence clear all
1302          * enable bits here to ensure that we don't enable too much. */
1303         intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE);
1304         intel_dp->DP |= DP_PLL_ENABLE;
1305         I915_WRITE(DP_A, intel_dp->DP);
1306         POSTING_READ(DP_A);
1307         udelay(200);
1308 }
1309
1310 static void ironlake_edp_pll_off(struct intel_dp *intel_dp)
1311 {
1312         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1313         struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
1314         struct drm_device *dev = crtc->dev;
1315         struct drm_i915_private *dev_priv = dev->dev_private;
1316         u32 dpa_ctl;
1317
1318         assert_pipe_disabled(dev_priv,
1319                              to_intel_crtc(crtc)->pipe);
1320
1321         dpa_ctl = I915_READ(DP_A);
1322         WARN((dpa_ctl & DP_PLL_ENABLE) == 0,
1323              "dp pll off, should be on\n");
1324         WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n");
1325
1326         /* We can't rely on the value tracked for the DP register in
1327          * intel_dp->DP because link_down must not change that (otherwise link
1328          * re-training will fail. */
1329         dpa_ctl &= ~DP_PLL_ENABLE;
1330         I915_WRITE(DP_A, dpa_ctl);
1331         POSTING_READ(DP_A);
1332         udelay(200);
1333 }
1334
1335 /* If the sink supports it, try to set the power state appropriately */
1336 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode)
1337 {
1338         int ret, i;
1339
1340         /* Should have a valid DPCD by this point */
1341         if (intel_dp->dpcd[DP_DPCD_REV] < 0x11)
1342                 return;
1343
1344         if (mode != DRM_MODE_DPMS_ON) {
1345                 ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER,
1346                                                   DP_SET_POWER_D3);
1347                 if (ret != 1)
1348                         DRM_DEBUG_DRIVER("failed to write sink power state\n");
1349         } else {
1350                 /*
1351                  * When turning on, we need to retry for 1ms to give the sink
1352                  * time to wake up.
1353                  */
1354                 for (i = 0; i < 3; i++) {
1355                         ret = intel_dp_aux_native_write_1(intel_dp,
1356                                                           DP_SET_POWER,
1357                                                           DP_SET_POWER_D0);
1358                         if (ret == 1)
1359                                 break;
1360                         msleep(1);
1361                 }
1362         }
1363 }
1364
1365 static bool intel_dp_get_hw_state(struct intel_encoder *encoder,
1366                                   enum pipe *pipe)
1367 {
1368         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1369         struct drm_device *dev = encoder->base.dev;
1370         struct drm_i915_private *dev_priv = dev->dev_private;
1371         u32 tmp = I915_READ(intel_dp->output_reg);
1372
1373         if (!(tmp & DP_PORT_EN))
1374                 return false;
1375
1376         if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) {
1377                 *pipe = PORT_TO_PIPE_CPT(tmp);
1378         } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) {
1379                 *pipe = PORT_TO_PIPE(tmp);
1380         } else {
1381                 u32 trans_sel;
1382                 u32 trans_dp;
1383                 int i;
1384
1385                 switch (intel_dp->output_reg) {
1386                 case PCH_DP_B:
1387                         trans_sel = TRANS_DP_PORT_SEL_B;
1388                         break;
1389                 case PCH_DP_C:
1390                         trans_sel = TRANS_DP_PORT_SEL_C;
1391                         break;
1392                 case PCH_DP_D:
1393                         trans_sel = TRANS_DP_PORT_SEL_D;
1394                         break;
1395                 default:
1396                         return true;
1397                 }
1398
1399                 for_each_pipe(i) {
1400                         trans_dp = I915_READ(TRANS_DP_CTL(i));
1401                         if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) {
1402                                 *pipe = i;
1403                                 return true;
1404                         }
1405                 }
1406
1407                 DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n",
1408                               intel_dp->output_reg);
1409         }
1410
1411         return true;
1412 }
1413
1414 static void intel_disable_dp(struct intel_encoder *encoder)
1415 {
1416         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1417
1418         /* Make sure the panel is off before trying to change the mode. But also
1419          * ensure that we have vdd while we switch off the panel. */
1420         ironlake_edp_panel_vdd_on(intel_dp);
1421         ironlake_edp_backlight_off(intel_dp);
1422         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1423         ironlake_edp_panel_off(intel_dp);
1424
1425         /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */
1426         if (!is_cpu_edp(intel_dp))
1427                 intel_dp_link_down(intel_dp);
1428 }
1429
1430 static void intel_post_disable_dp(struct intel_encoder *encoder)
1431 {
1432         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1433
1434         if (is_cpu_edp(intel_dp)) {
1435                 intel_dp_link_down(intel_dp);
1436                 ironlake_edp_pll_off(intel_dp);
1437         }
1438 }
1439
1440 static void intel_enable_dp(struct intel_encoder *encoder)
1441 {
1442         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1443         struct drm_device *dev = encoder->base.dev;
1444         struct drm_i915_private *dev_priv = dev->dev_private;
1445         uint32_t dp_reg = I915_READ(intel_dp->output_reg);
1446
1447         if (WARN_ON(dp_reg & DP_PORT_EN))
1448                 return;
1449
1450         ironlake_edp_panel_vdd_on(intel_dp);
1451         intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON);
1452         intel_dp_start_link_train(intel_dp);
1453         ironlake_edp_panel_on(intel_dp);
1454         ironlake_edp_panel_vdd_off(intel_dp, true);
1455         intel_dp_complete_link_train(intel_dp);
1456         ironlake_edp_backlight_on(intel_dp);
1457 }
1458
1459 static void intel_pre_enable_dp(struct intel_encoder *encoder)
1460 {
1461         struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1462
1463         if (is_cpu_edp(intel_dp))
1464                 ironlake_edp_pll_on(intel_dp);
1465 }
1466
1467 /*
1468  * Native read with retry for link status and receiver capability reads for
1469  * cases where the sink may still be asleep.
1470  */
1471 static bool
1472 intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address,
1473                                uint8_t *recv, int recv_bytes)
1474 {
1475         int ret, i;
1476
1477         /*
1478          * Sinks are *supposed* to come up within 1ms from an off state,
1479          * but we're also supposed to retry 3 times per the spec.
1480          */
1481         for (i = 0; i < 3; i++) {
1482                 ret = intel_dp_aux_native_read(intel_dp, address, recv,
1483                                                recv_bytes);
1484                 if (ret == recv_bytes)
1485                         return true;
1486                 msleep(1);
1487         }
1488
1489         return false;
1490 }
1491
1492 /*
1493  * Fetch AUX CH registers 0x202 - 0x207 which contain
1494  * link status information
1495  */
1496 static bool
1497 intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1498 {
1499         return intel_dp_aux_native_read_retry(intel_dp,
1500                                               DP_LANE0_1_STATUS,
1501                                               link_status,
1502                                               DP_LINK_STATUS_SIZE);
1503 }
1504
1505 #if 0
1506 static char     *voltage_names[] = {
1507         "0.4V", "0.6V", "0.8V", "1.2V"
1508 };
1509 static char     *pre_emph_names[] = {
1510         "0dB", "3.5dB", "6dB", "9.5dB"
1511 };
1512 static char     *link_train_names[] = {
1513         "pattern 1", "pattern 2", "idle", "off"
1514 };
1515 #endif
1516
1517 /*
1518  * These are source-specific values; current Intel hardware supports
1519  * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB
1520  */
1521
1522 static uint8_t
1523 intel_dp_voltage_max(struct intel_dp *intel_dp)
1524 {
1525         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1526
1527         if (IS_GEN7(dev) && is_cpu_edp(intel_dp))
1528                 return DP_TRAIN_VOLTAGE_SWING_800;
1529         else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp))
1530                 return DP_TRAIN_VOLTAGE_SWING_1200;
1531         else
1532                 return DP_TRAIN_VOLTAGE_SWING_800;
1533 }
1534
1535 static uint8_t
1536 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing)
1537 {
1538         struct drm_device *dev = intel_dp_to_dev(intel_dp);
1539
1540         if (HAS_DDI(dev)) {
1541                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1542                 case DP_TRAIN_VOLTAGE_SWING_400:
1543                         return DP_TRAIN_PRE_EMPHASIS_9_5;
1544                 case DP_TRAIN_VOLTAGE_SWING_600:
1545                         return DP_TRAIN_PRE_EMPHASIS_6;
1546                 case DP_TRAIN_VOLTAGE_SWING_800:
1547                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1548                 case DP_TRAIN_VOLTAGE_SWING_1200:
1549                 default:
1550                         return DP_TRAIN_PRE_EMPHASIS_0;
1551                 }
1552         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1553                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1554                 case DP_TRAIN_VOLTAGE_SWING_400:
1555                         return DP_TRAIN_PRE_EMPHASIS_6;
1556                 case DP_TRAIN_VOLTAGE_SWING_600:
1557                 case DP_TRAIN_VOLTAGE_SWING_800:
1558                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1559                 default:
1560                         return DP_TRAIN_PRE_EMPHASIS_0;
1561                 }
1562         } else {
1563                 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) {
1564                 case DP_TRAIN_VOLTAGE_SWING_400:
1565                         return DP_TRAIN_PRE_EMPHASIS_6;
1566                 case DP_TRAIN_VOLTAGE_SWING_600:
1567                         return DP_TRAIN_PRE_EMPHASIS_6;
1568                 case DP_TRAIN_VOLTAGE_SWING_800:
1569                         return DP_TRAIN_PRE_EMPHASIS_3_5;
1570                 case DP_TRAIN_VOLTAGE_SWING_1200:
1571                 default:
1572                         return DP_TRAIN_PRE_EMPHASIS_0;
1573                 }
1574         }
1575 }
1576
1577 static void
1578 intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE])
1579 {
1580         uint8_t v = 0;
1581         uint8_t p = 0;
1582         int lane;
1583         uint8_t voltage_max;
1584         uint8_t preemph_max;
1585
1586         for (lane = 0; lane < intel_dp->lane_count; lane++) {
1587                 uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane);
1588                 uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane);
1589
1590                 if (this_v > v)
1591                         v = this_v;
1592                 if (this_p > p)
1593                         p = this_p;
1594         }
1595
1596         voltage_max = intel_dp_voltage_max(intel_dp);
1597         if (v >= voltage_max)
1598                 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
1599
1600         preemph_max = intel_dp_pre_emphasis_max(intel_dp, v);
1601         if (p >= preemph_max)
1602                 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
1603
1604         for (lane = 0; lane < 4; lane++)
1605                 intel_dp->train_set[lane] = v | p;
1606 }
1607
1608 static uint32_t
1609 intel_gen4_signal_levels(uint8_t train_set)
1610 {
1611         uint32_t        signal_levels = 0;
1612
1613         switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) {
1614         case DP_TRAIN_VOLTAGE_SWING_400:
1615         default:
1616                 signal_levels |= DP_VOLTAGE_0_4;
1617                 break;
1618         case DP_TRAIN_VOLTAGE_SWING_600:
1619                 signal_levels |= DP_VOLTAGE_0_6;
1620                 break;
1621         case DP_TRAIN_VOLTAGE_SWING_800:
1622                 signal_levels |= DP_VOLTAGE_0_8;
1623                 break;
1624         case DP_TRAIN_VOLTAGE_SWING_1200:
1625                 signal_levels |= DP_VOLTAGE_1_2;
1626                 break;
1627         }
1628         switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) {
1629         case DP_TRAIN_PRE_EMPHASIS_0:
1630         default:
1631                 signal_levels |= DP_PRE_EMPHASIS_0;
1632                 break;
1633         case DP_TRAIN_PRE_EMPHASIS_3_5:
1634                 signal_levels |= DP_PRE_EMPHASIS_3_5;
1635                 break;
1636         case DP_TRAIN_PRE_EMPHASIS_6:
1637                 signal_levels |= DP_PRE_EMPHASIS_6;
1638                 break;
1639         case DP_TRAIN_PRE_EMPHASIS_9_5:
1640                 signal_levels |= DP_PRE_EMPHASIS_9_5;
1641                 break;
1642         }
1643         return signal_levels;
1644 }
1645
1646 /* Gen6's DP voltage swing and pre-emphasis control */
1647 static uint32_t
1648 intel_gen6_edp_signal_levels(uint8_t train_set)
1649 {
1650         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1651                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1652         switch (signal_levels) {
1653         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1654         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1655                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1656         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1657                 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B;
1658         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1659         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1660                 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B;
1661         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1662         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1663                 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B;
1664         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1665         case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0:
1666                 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B;
1667         default:
1668                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1669                               "0x%x\n", signal_levels);
1670                 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B;
1671         }
1672 }
1673
1674 /* Gen7's DP voltage swing and pre-emphasis control */
1675 static uint32_t
1676 intel_gen7_edp_signal_levels(uint8_t train_set)
1677 {
1678         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1679                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1680         switch (signal_levels) {
1681         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1682                 return EDP_LINK_TRAIN_400MV_0DB_IVB;
1683         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1684                 return EDP_LINK_TRAIN_400MV_3_5DB_IVB;
1685         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1686                 return EDP_LINK_TRAIN_400MV_6DB_IVB;
1687
1688         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1689                 return EDP_LINK_TRAIN_600MV_0DB_IVB;
1690         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1691                 return EDP_LINK_TRAIN_600MV_3_5DB_IVB;
1692
1693         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1694                 return EDP_LINK_TRAIN_800MV_0DB_IVB;
1695         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1696                 return EDP_LINK_TRAIN_800MV_3_5DB_IVB;
1697
1698         default:
1699                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1700                               "0x%x\n", signal_levels);
1701                 return EDP_LINK_TRAIN_500MV_0DB_IVB;
1702         }
1703 }
1704
1705 /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */
1706 static uint32_t
1707 intel_hsw_signal_levels(uint8_t train_set)
1708 {
1709         int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK |
1710                                          DP_TRAIN_PRE_EMPHASIS_MASK);
1711         switch (signal_levels) {
1712         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0:
1713                 return DDI_BUF_EMP_400MV_0DB_HSW;
1714         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5:
1715                 return DDI_BUF_EMP_400MV_3_5DB_HSW;
1716         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6:
1717                 return DDI_BUF_EMP_400MV_6DB_HSW;
1718         case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5:
1719                 return DDI_BUF_EMP_400MV_9_5DB_HSW;
1720
1721         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0:
1722                 return DDI_BUF_EMP_600MV_0DB_HSW;
1723         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5:
1724                 return DDI_BUF_EMP_600MV_3_5DB_HSW;
1725         case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6:
1726                 return DDI_BUF_EMP_600MV_6DB_HSW;
1727
1728         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0:
1729                 return DDI_BUF_EMP_800MV_0DB_HSW;
1730         case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5:
1731                 return DDI_BUF_EMP_800MV_3_5DB_HSW;
1732         default:
1733                 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:"
1734                               "0x%x\n", signal_levels);
1735                 return DDI_BUF_EMP_400MV_0DB_HSW;
1736         }
1737 }
1738
1739 /* Properly updates "DP" with the correct signal levels. */
1740 static void
1741 intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP)
1742 {
1743         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1744         struct drm_device *dev = intel_dig_port->base.base.dev;
1745         uint32_t signal_levels, mask;
1746         uint8_t train_set = intel_dp->train_set[0];
1747
1748         if (HAS_DDI(dev)) {
1749                 signal_levels = intel_hsw_signal_levels(train_set);
1750                 mask = DDI_BUF_EMP_MASK;
1751         } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) {
1752                 signal_levels = intel_gen7_edp_signal_levels(train_set);
1753                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB;
1754         } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) {
1755                 signal_levels = intel_gen6_edp_signal_levels(train_set);
1756                 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB;
1757         } else {
1758                 signal_levels = intel_gen4_signal_levels(train_set);
1759                 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK;
1760         }
1761
1762         DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels);
1763
1764         *DP = (*DP & ~mask) | signal_levels;
1765 }
1766
1767 static bool
1768 intel_dp_set_link_train(struct intel_dp *intel_dp,
1769                         uint32_t dp_reg_value,
1770                         uint8_t dp_train_pat)
1771 {
1772         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
1773         struct drm_device *dev = intel_dig_port->base.base.dev;
1774         struct drm_i915_private *dev_priv = dev->dev_private;
1775         enum port port = intel_dig_port->port;
1776         int ret;
1777         uint32_t temp;
1778
1779         if (HAS_DDI(dev)) {
1780                 temp = I915_READ(DP_TP_CTL(port));
1781
1782                 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE)
1783                         temp |= DP_TP_CTL_SCRAMBLE_DISABLE;
1784                 else
1785                         temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE;
1786
1787                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1788                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1789                 case DP_TRAINING_PATTERN_DISABLE:
1790
1791                         if (port != PORT_A) {
1792                                 temp |= DP_TP_CTL_LINK_TRAIN_IDLE;
1793                                 I915_WRITE(DP_TP_CTL(port), temp);
1794
1795                                 if (wait_for((I915_READ(DP_TP_STATUS(port)) &
1796                                               DP_TP_STATUS_IDLE_DONE), 1))
1797                                         DRM_ERROR("Timed out waiting for DP idle patterns\n");
1798
1799                                 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK;
1800                         }
1801
1802                         temp |= DP_TP_CTL_LINK_TRAIN_NORMAL;
1803
1804                         break;
1805                 case DP_TRAINING_PATTERN_1:
1806                         temp |= DP_TP_CTL_LINK_TRAIN_PAT1;
1807                         break;
1808                 case DP_TRAINING_PATTERN_2:
1809                         temp |= DP_TP_CTL_LINK_TRAIN_PAT2;
1810                         break;
1811                 case DP_TRAINING_PATTERN_3:
1812                         temp |= DP_TP_CTL_LINK_TRAIN_PAT3;
1813                         break;
1814                 }
1815                 I915_WRITE(DP_TP_CTL(port), temp);
1816
1817         } else if (HAS_PCH_CPT(dev) &&
1818                    (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
1819                 dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT;
1820
1821                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1822                 case DP_TRAINING_PATTERN_DISABLE:
1823                         dp_reg_value |= DP_LINK_TRAIN_OFF_CPT;
1824                         break;
1825                 case DP_TRAINING_PATTERN_1:
1826                         dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT;
1827                         break;
1828                 case DP_TRAINING_PATTERN_2:
1829                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1830                         break;
1831                 case DP_TRAINING_PATTERN_3:
1832                         DRM_ERROR("DP training pattern 3 not supported\n");
1833                         dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT;
1834                         break;
1835                 }
1836
1837         } else {
1838                 dp_reg_value &= ~DP_LINK_TRAIN_MASK;
1839
1840                 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) {
1841                 case DP_TRAINING_PATTERN_DISABLE:
1842                         dp_reg_value |= DP_LINK_TRAIN_OFF;
1843                         break;
1844                 case DP_TRAINING_PATTERN_1:
1845                         dp_reg_value |= DP_LINK_TRAIN_PAT_1;
1846                         break;
1847                 case DP_TRAINING_PATTERN_2:
1848                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1849                         break;
1850                 case DP_TRAINING_PATTERN_3:
1851                         DRM_ERROR("DP training pattern 3 not supported\n");
1852                         dp_reg_value |= DP_LINK_TRAIN_PAT_2;
1853                         break;
1854                 }
1855         }
1856
1857         I915_WRITE(intel_dp->output_reg, dp_reg_value);
1858         POSTING_READ(intel_dp->output_reg);
1859
1860         intel_dp_aux_native_write_1(intel_dp,
1861                                     DP_TRAINING_PATTERN_SET,
1862                                     dp_train_pat);
1863
1864         if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) !=
1865             DP_TRAINING_PATTERN_DISABLE) {
1866                 ret = intel_dp_aux_native_write(intel_dp,
1867                                                 DP_TRAINING_LANE0_SET,
1868                                                 intel_dp->train_set,
1869                                                 intel_dp->lane_count);
1870                 if (ret != intel_dp->lane_count)
1871                         return false;
1872         }
1873
1874         return true;
1875 }
1876
1877 /* Enable corresponding port and start training pattern 1 */
1878 void
1879 intel_dp_start_link_train(struct intel_dp *intel_dp)
1880 {
1881         struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base;
1882         struct drm_device *dev = encoder->dev;
1883         int i;
1884         uint8_t voltage;
1885         bool clock_recovery = false;
1886         int voltage_tries, loop_tries;
1887         uint32_t DP = intel_dp->DP;
1888
1889         if (HAS_DDI(dev))
1890                 intel_ddi_prepare_link_retrain(encoder);
1891
1892         /* Write the link configuration data */
1893         intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET,
1894                                   intel_dp->link_configuration,
1895                                   DP_LINK_CONFIGURATION_SIZE);
1896
1897         DP |= DP_PORT_EN;
1898
1899         memset(intel_dp->train_set, 0, 4);
1900         voltage = 0xff;
1901         voltage_tries = 0;
1902         loop_tries = 0;
1903         clock_recovery = false;
1904         for (;;) {
1905                 /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */
1906                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1907
1908                 intel_dp_set_signal_levels(intel_dp, &DP);
1909
1910                 /* Set training pattern 1 */
1911                 if (!intel_dp_set_link_train(intel_dp, DP,
1912                                              DP_TRAINING_PATTERN_1 |
1913                                              DP_LINK_SCRAMBLING_DISABLE))
1914                         break;
1915
1916                 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd);
1917                 if (!intel_dp_get_link_status(intel_dp, link_status)) {
1918                         DRM_ERROR("failed to get link status\n");
1919                         break;
1920                 }
1921
1922                 if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1923                         DRM_DEBUG_KMS("clock recovery OK\n");
1924                         clock_recovery = true;
1925                         break;
1926                 }
1927
1928                 /* Check to see if we've tried the max voltage */
1929                 for (i = 0; i < intel_dp->lane_count; i++)
1930                         if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0)
1931                                 break;
1932                 if (i == intel_dp->lane_count && voltage_tries == 5) {
1933                         ++loop_tries;
1934                         if (loop_tries == 5) {
1935                                 DRM_DEBUG_KMS("too many full retries, give up\n");
1936                                 break;
1937                         }
1938                         memset(intel_dp->train_set, 0, 4);
1939                         voltage_tries = 0;
1940                         continue;
1941                 }
1942
1943                 /* Check to see if we've tried the same voltage 5 times */
1944                 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) {
1945                         ++voltage_tries;
1946                         if (voltage_tries == 5) {
1947                                 DRM_DEBUG_KMS("too many voltage retries, give up\n");
1948                                 break;
1949                         }
1950                 } else
1951                         voltage_tries = 0;
1952                 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
1953
1954                 /* Compute new intel_dp->train_set as requested by target */
1955                 intel_get_adjust_train(intel_dp, link_status);
1956         }
1957
1958         intel_dp->DP = DP;
1959 }
1960
1961 void
1962 intel_dp_complete_link_train(struct intel_dp *intel_dp)
1963 {
1964         bool channel_eq = false;
1965         int tries, cr_tries;
1966         uint32_t DP = intel_dp->DP;
1967
1968         /* channel equalization */
1969         tries = 0;
1970         cr_tries = 0;
1971         channel_eq = false;
1972         for (;;) {
1973                 uint8_t     link_status[DP_LINK_STATUS_SIZE];
1974
1975                 if (cr_tries > 5) {
1976                         DRM_ERROR("failed to train DP, aborting\n");
1977                         intel_dp_link_down(intel_dp);
1978                         break;
1979                 }
1980
1981                 intel_dp_set_signal_levels(intel_dp, &DP);
1982
1983                 /* channel eq pattern */
1984                 if (!intel_dp_set_link_train(intel_dp, DP,
1985                                              DP_TRAINING_PATTERN_2 |
1986                                              DP_LINK_SCRAMBLING_DISABLE))
1987                         break;
1988
1989                 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd);
1990                 if (!intel_dp_get_link_status(intel_dp, link_status))
1991                         break;
1992
1993                 /* Make sure clock is still ok */
1994                 if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) {
1995                         intel_dp_start_link_train(intel_dp);
1996                         cr_tries++;
1997                         continue;
1998                 }
1999
2000                 if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2001                         channel_eq = true;
2002                         break;
2003                 }
2004
2005                 /* Try 5 times, then try clock recovery if that fails */
2006                 if (tries > 5) {
2007                         intel_dp_link_down(intel_dp);
2008                         intel_dp_start_link_train(intel_dp);
2009                         tries = 0;
2010                         cr_tries++;
2011                         continue;
2012                 }
2013
2014                 /* Compute new intel_dp->train_set as requested by target */
2015                 intel_get_adjust_train(intel_dp, link_status);
2016                 ++tries;
2017         }
2018
2019         if (channel_eq)
2020                 DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n");
2021
2022         intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE);
2023 }
2024
2025 static void
2026 intel_dp_link_down(struct intel_dp *intel_dp)
2027 {
2028         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2029         struct drm_device *dev = intel_dig_port->base.base.dev;
2030         struct drm_i915_private *dev_priv = dev->dev_private;
2031         struct intel_crtc *intel_crtc =
2032                 to_intel_crtc(intel_dig_port->base.base.crtc);
2033         uint32_t DP = intel_dp->DP;
2034
2035         /*
2036          * DDI code has a strict mode set sequence and we should try to respect
2037          * it, otherwise we might hang the machine in many different ways. So we
2038          * really should be disabling the port only on a complete crtc_disable
2039          * sequence. This function is just called under two conditions on DDI
2040          * code:
2041          * - Link train failed while doing crtc_enable, and on this case we
2042          *   really should respect the mode set sequence and wait for a
2043          *   crtc_disable.
2044          * - Someone turned the monitor off and intel_dp_check_link_status
2045          *   called us. We don't need to disable the whole port on this case, so
2046          *   when someone turns the monitor on again,
2047          *   intel_ddi_prepare_link_retrain will take care of redoing the link
2048          *   train.
2049          */
2050         if (HAS_DDI(dev))
2051                 return;
2052
2053         if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0))
2054                 return;
2055
2056         DRM_DEBUG_KMS("\n");
2057
2058         if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) {
2059                 DP &= ~DP_LINK_TRAIN_MASK_CPT;
2060                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT);
2061         } else {
2062                 DP &= ~DP_LINK_TRAIN_MASK;
2063                 I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE);
2064         }
2065         POSTING_READ(intel_dp->output_reg);
2066
2067         /* We don't really know why we're doing this */
2068         intel_wait_for_vblank(dev, intel_crtc->pipe);
2069
2070         if (HAS_PCH_IBX(dev) &&
2071             I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) {
2072                 struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
2073
2074                 /* Hardware workaround: leaving our transcoder select
2075                  * set to transcoder B while it's off will prevent the
2076                  * corresponding HDMI output on transcoder A.
2077                  *
2078                  * Combine this with another hardware workaround:
2079                  * transcoder select bit can only be cleared while the
2080                  * port is enabled.
2081                  */
2082                 DP &= ~DP_PIPEB_SELECT;
2083                 I915_WRITE(intel_dp->output_reg, DP);
2084
2085                 /* Changes to enable or select take place the vblank
2086                  * after being written.
2087                  */
2088                 if (WARN_ON(crtc == NULL)) {
2089                         /* We should never try to disable a port without a crtc
2090                          * attached. For paranoia keep the code around for a
2091                          * bit. */
2092                         POSTING_READ(intel_dp->output_reg);
2093                         msleep(50);
2094                 } else
2095                         intel_wait_for_vblank(dev, intel_crtc->pipe);
2096         }
2097
2098         DP &= ~DP_AUDIO_OUTPUT_ENABLE;
2099         I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN);
2100         POSTING_READ(intel_dp->output_reg);
2101         msleep(intel_dp->panel_power_down_delay);
2102 }
2103
2104 static bool
2105 intel_dp_get_dpcd(struct intel_dp *intel_dp)
2106 {
2107         char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3];
2108
2109         if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd,
2110                                            sizeof(intel_dp->dpcd)) == 0)
2111                 return false; /* aux transfer failed */
2112
2113         hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd),
2114                            32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false);
2115         DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump);
2116
2117         if (intel_dp->dpcd[DP_DPCD_REV] == 0)
2118                 return false; /* DPCD not present */
2119
2120         if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] &
2121               DP_DWN_STRM_PORT_PRESENT))
2122                 return true; /* native DP sink */
2123
2124         if (intel_dp->dpcd[DP_DPCD_REV] == 0x10)
2125                 return true; /* no per-port downstream info */
2126
2127         if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0,
2128                                            intel_dp->downstream_ports,
2129                                            DP_MAX_DOWNSTREAM_PORTS) == 0)
2130                 return false; /* downstream port status fetch failed */
2131
2132         return true;
2133 }
2134
2135 static void
2136 intel_dp_probe_oui(struct intel_dp *intel_dp)
2137 {
2138         u8 buf[3];
2139
2140         if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT))
2141                 return;
2142
2143         ironlake_edp_panel_vdd_on(intel_dp);
2144
2145         if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3))
2146                 DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n",
2147                               buf[0], buf[1], buf[2]);
2148
2149         if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3))
2150                 DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n",
2151                               buf[0], buf[1], buf[2]);
2152
2153         ironlake_edp_panel_vdd_off(intel_dp, false);
2154 }
2155
2156 static bool
2157 intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector)
2158 {
2159         int ret;
2160
2161         ret = intel_dp_aux_native_read_retry(intel_dp,
2162                                              DP_DEVICE_SERVICE_IRQ_VECTOR,
2163                                              sink_irq_vector, 1);
2164         if (!ret)
2165                 return false;
2166
2167         return true;
2168 }
2169
2170 static void
2171 intel_dp_handle_test_request(struct intel_dp *intel_dp)
2172 {
2173         /* NAK by default */
2174         intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK);
2175 }
2176
2177 /*
2178  * According to DP spec
2179  * 5.1.2:
2180  *  1. Read DPCD
2181  *  2. Configure link according to Receiver Capabilities
2182  *  3. Use Link Training from 2.5.3.3 and 3.5.1.3
2183  *  4. Check link status on receipt of hot-plug interrupt
2184  */
2185
2186 void
2187 intel_dp_check_link_status(struct intel_dp *intel_dp)
2188 {
2189         struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base;
2190         u8 sink_irq_vector;
2191         u8 link_status[DP_LINK_STATUS_SIZE];
2192
2193         if (!intel_encoder->connectors_active)
2194                 return;
2195
2196         if (WARN_ON(!intel_encoder->base.crtc))
2197                 return;
2198
2199         /* Try to read receiver status if the link appears to be up */
2200         if (!intel_dp_get_link_status(intel_dp, link_status)) {
2201                 intel_dp_link_down(intel_dp);
2202                 return;
2203         }
2204
2205         /* Now read the DPCD to see if it's actually running */
2206         if (!intel_dp_get_dpcd(intel_dp)) {
2207                 intel_dp_link_down(intel_dp);
2208                 return;
2209         }
2210
2211         /* Try to read the source of the interrupt */
2212         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 &&
2213             intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) {
2214                 /* Clear interrupt source */
2215                 intel_dp_aux_native_write_1(intel_dp,
2216                                             DP_DEVICE_SERVICE_IRQ_VECTOR,
2217                                             sink_irq_vector);
2218
2219                 if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST)
2220                         intel_dp_handle_test_request(intel_dp);
2221                 if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ))
2222                         DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n");
2223         }
2224
2225         if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) {
2226                 DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n",
2227                               drm_get_encoder_name(&intel_encoder->base));
2228                 intel_dp_start_link_train(intel_dp);
2229                 intel_dp_complete_link_train(intel_dp);
2230         }
2231 }
2232
2233 /* XXX this is probably wrong for multiple downstream ports */
2234 static enum drm_connector_status
2235 intel_dp_detect_dpcd(struct intel_dp *intel_dp)
2236 {
2237         uint8_t *dpcd = intel_dp->dpcd;
2238         bool hpd;
2239         uint8_t type;
2240
2241         if (!intel_dp_get_dpcd(intel_dp))
2242                 return connector_status_disconnected;
2243
2244         /* if there's no downstream port, we're done */
2245         if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT))
2246                 return connector_status_connected;
2247
2248         /* If we're HPD-aware, SINK_COUNT changes dynamically */
2249         hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD);
2250         if (hpd) {
2251                 uint8_t reg;
2252                 if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT,
2253                                                     &reg, 1))
2254                         return connector_status_unknown;
2255                 return DP_GET_SINK_COUNT(reg) ? connector_status_connected
2256                                               : connector_status_disconnected;
2257         }
2258
2259         /* If no HPD, poke DDC gently */
2260         if (drm_probe_ddc(&intel_dp->adapter))
2261                 return connector_status_connected;
2262
2263         /* Well we tried, say unknown for unreliable port types */
2264         type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK;
2265         if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID)
2266                 return connector_status_unknown;
2267
2268         /* Anything else is out of spec, warn and ignore */
2269         DRM_DEBUG_KMS("Broken DP branch device, ignoring\n");
2270         return connector_status_disconnected;
2271 }
2272
2273 static enum drm_connector_status
2274 ironlake_dp_detect(struct intel_dp *intel_dp)
2275 {
2276         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2277         struct drm_i915_private *dev_priv = dev->dev_private;
2278         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2279         enum drm_connector_status status;
2280
2281         /* Can't disconnect eDP, but you can close the lid... */
2282         if (is_edp(intel_dp)) {
2283                 status = intel_panel_detect(dev);
2284                 if (status == connector_status_unknown)
2285                         status = connector_status_connected;
2286                 return status;
2287         }
2288
2289         if (!ibx_digital_port_connected(dev_priv, intel_dig_port))
2290                 return connector_status_disconnected;
2291
2292         return intel_dp_detect_dpcd(intel_dp);
2293 }
2294
2295 static enum drm_connector_status
2296 g4x_dp_detect(struct intel_dp *intel_dp)
2297 {
2298         struct drm_device *dev = intel_dp_to_dev(intel_dp);
2299         struct drm_i915_private *dev_priv = dev->dev_private;
2300         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2301         uint32_t bit;
2302
2303         switch (intel_dig_port->port) {
2304         case PORT_B:
2305                 bit = PORTB_HOTPLUG_LIVE_STATUS;
2306                 break;
2307         case PORT_C:
2308                 bit = PORTC_HOTPLUG_LIVE_STATUS;
2309                 break;
2310         case PORT_D:
2311                 bit = PORTD_HOTPLUG_LIVE_STATUS;
2312                 break;
2313         default:
2314                 return connector_status_unknown;
2315         }
2316
2317         if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0)
2318                 return connector_status_disconnected;
2319
2320         return intel_dp_detect_dpcd(intel_dp);
2321 }
2322
2323 static struct edid *
2324 intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter)
2325 {
2326         struct intel_connector *intel_connector = to_intel_connector(connector);
2327
2328         /* use cached edid if we have one */
2329         if (intel_connector->edid) {
2330                 struct edid *edid;
2331                 int size;
2332
2333                 /* invalid edid */
2334                 if (IS_ERR(intel_connector->edid))
2335                         return NULL;
2336
2337                 size = (intel_connector->edid->extensions + 1) * EDID_LENGTH;
2338                 edid = kmalloc(size, GFP_KERNEL);
2339                 if (!edid)
2340                         return NULL;
2341
2342                 memcpy(edid, intel_connector->edid, size);
2343                 return edid;
2344         }
2345
2346         return drm_get_edid(connector, adapter);
2347 }
2348
2349 static int
2350 intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter)
2351 {
2352         struct intel_connector *intel_connector = to_intel_connector(connector);
2353
2354         /* use cached edid if we have one */
2355         if (intel_connector->edid) {
2356                 /* invalid edid */
2357                 if (IS_ERR(intel_connector->edid))
2358                         return 0;
2359
2360                 return intel_connector_update_modes(connector,
2361                                                     intel_connector->edid);
2362         }
2363
2364         return intel_ddc_get_modes(connector, adapter);
2365 }
2366
2367 static enum drm_connector_status
2368 intel_dp_detect(struct drm_connector *connector, bool force)
2369 {
2370         struct intel_dp *intel_dp = intel_attached_dp(connector);
2371         struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
2372         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2373         struct drm_device *dev = connector->dev;
2374         enum drm_connector_status status;
2375         struct edid *edid = NULL;
2376
2377         intel_dp->has_audio = false;
2378
2379         if (HAS_PCH_SPLIT(dev))
2380                 status = ironlake_dp_detect(intel_dp);
2381         else
2382                 status = g4x_dp_detect(intel_dp);
2383
2384         if (status != connector_status_connected)
2385                 return status;
2386
2387         intel_dp_probe_oui(intel_dp);
2388
2389         if (intel_dp->force_audio != HDMI_AUDIO_AUTO) {
2390                 intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON);
2391         } else {
2392                 edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2393                 if (edid) {
2394                         intel_dp->has_audio = drm_detect_monitor_audio(edid);
2395                         kfree(edid);
2396                 }
2397         }
2398
2399         if (intel_encoder->type != INTEL_OUTPUT_EDP)
2400                 intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2401         return connector_status_connected;
2402 }
2403
2404 static int intel_dp_get_modes(struct drm_connector *connector)
2405 {
2406         struct intel_dp *intel_dp = intel_attached_dp(connector);
2407         struct intel_connector *intel_connector = to_intel_connector(connector);
2408         struct drm_device *dev = connector->dev;
2409         int ret;
2410
2411         /* We should parse the EDID data and find out if it has an audio sink
2412          */
2413
2414         ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter);
2415         if (ret)
2416                 return ret;
2417
2418         /* if eDP has no EDID, fall back to fixed mode */
2419         if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) {
2420                 struct drm_display_mode *mode;
2421                 mode = drm_mode_duplicate(dev,
2422                                           intel_connector->panel.fixed_mode);
2423                 if (mode) {
2424                         drm_mode_probed_add(connector, mode);
2425                         return 1;
2426                 }
2427         }
2428         return 0;
2429 }
2430
2431 static bool
2432 intel_dp_detect_audio(struct drm_connector *connector)
2433 {
2434         struct intel_dp *intel_dp = intel_attached_dp(connector);
2435         struct edid *edid;
2436         bool has_audio = false;
2437
2438         edid = intel_dp_get_edid(connector, &intel_dp->adapter);
2439         if (edid) {
2440                 has_audio = drm_detect_monitor_audio(edid);
2441                 kfree(edid);
2442         }
2443
2444         return has_audio;
2445 }
2446
2447 static int
2448 intel_dp_set_property(struct drm_connector *connector,
2449                       struct drm_property *property,
2450                       uint64_t val)
2451 {
2452         struct drm_i915_private *dev_priv = connector->dev->dev_private;
2453         struct intel_connector *intel_connector = to_intel_connector(connector);
2454         struct intel_encoder *intel_encoder = intel_attached_encoder(connector);
2455         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2456         int ret;
2457
2458         ret = drm_object_property_set_value(&connector->base, property, val);
2459         if (ret)
2460                 return ret;
2461
2462         if (property == dev_priv->force_audio_property) {
2463                 int i = val;
2464                 bool has_audio;
2465
2466                 if (i == intel_dp->force_audio)
2467                         return 0;
2468
2469                 intel_dp->force_audio = i;
2470
2471                 if (i == HDMI_AUDIO_AUTO)
2472                         has_audio = intel_dp_detect_audio(connector);
2473                 else
2474                         has_audio = (i == HDMI_AUDIO_ON);
2475
2476                 if (has_audio == intel_dp->has_audio)
2477                         return 0;
2478
2479                 intel_dp->has_audio = has_audio;
2480                 goto done;
2481         }
2482
2483         if (property == dev_priv->broadcast_rgb_property) {
2484                 switch (val) {
2485                 case INTEL_BROADCAST_RGB_AUTO:
2486                         intel_dp->color_range_auto = true;
2487                         break;
2488                 case INTEL_BROADCAST_RGB_FULL:
2489                         intel_dp->color_range_auto = false;
2490                         intel_dp->color_range = 0;
2491                         break;
2492                 case INTEL_BROADCAST_RGB_LIMITED:
2493                         intel_dp->color_range_auto = false;
2494                         intel_dp->color_range = DP_COLOR_RANGE_16_235;
2495                         break;
2496                 default:
2497                         return -EINVAL;
2498                 }
2499                 goto done;
2500         }
2501
2502         if (is_edp(intel_dp) &&
2503             property == connector->dev->mode_config.scaling_mode_property) {
2504                 if (val == DRM_MODE_SCALE_NONE) {
2505                         DRM_DEBUG_KMS("no scaling not supported\n");
2506                         return -EINVAL;
2507                 }
2508
2509                 if (intel_connector->panel.fitting_mode == val) {
2510                         /* the eDP scaling property is not changed */
2511                         return 0;
2512                 }
2513                 intel_connector->panel.fitting_mode = val;
2514
2515                 goto done;
2516         }
2517
2518         return -EINVAL;
2519
2520 done:
2521         if (intel_encoder->base.crtc)
2522                 intel_crtc_restore_mode(intel_encoder->base.crtc);
2523
2524         return 0;
2525 }
2526
2527 static void
2528 intel_dp_destroy(struct drm_connector *connector)
2529 {
2530         struct drm_device *dev = connector->dev;
2531         struct intel_dp *intel_dp = intel_attached_dp(connector);
2532         struct intel_connector *intel_connector = to_intel_connector(connector);
2533
2534         if (!IS_ERR_OR_NULL(intel_connector->edid))
2535                 kfree(intel_connector->edid);
2536
2537         if (is_edp(intel_dp)) {
2538                 intel_panel_destroy_backlight(dev);
2539                 intel_panel_fini(&intel_connector->panel);
2540         }
2541
2542         drm_sysfs_connector_remove(connector);
2543         drm_connector_cleanup(connector);
2544         kfree(connector);
2545 }
2546
2547 void intel_dp_encoder_destroy(struct drm_encoder *encoder)
2548 {
2549         struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
2550         struct intel_dp *intel_dp = &intel_dig_port->dp;
2551
2552         i2c_del_adapter(&intel_dp->adapter);
2553         drm_encoder_cleanup(encoder);
2554         if (is_edp(intel_dp)) {
2555                 cancel_delayed_work_sync(&intel_dp->panel_vdd_work);
2556                 ironlake_panel_vdd_off_sync(intel_dp);
2557         }
2558         kfree(intel_dig_port);
2559 }
2560
2561 static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = {
2562         .mode_fixup = intel_dp_mode_fixup,
2563         .mode_set = intel_dp_mode_set,
2564         .disable = intel_encoder_noop,
2565 };
2566
2567 static const struct drm_connector_funcs intel_dp_connector_funcs = {
2568         .dpms = intel_connector_dpms,
2569         .detect = intel_dp_detect,
2570         .fill_modes = drm_helper_probe_single_connector_modes,
2571         .set_property = intel_dp_set_property,
2572         .destroy = intel_dp_destroy,
2573 };
2574
2575 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = {
2576         .get_modes = intel_dp_get_modes,
2577         .mode_valid = intel_dp_mode_valid,
2578         .best_encoder = intel_best_encoder,
2579 };
2580
2581 static const struct drm_encoder_funcs intel_dp_enc_funcs = {
2582         .destroy = intel_dp_encoder_destroy,
2583 };
2584
2585 static void
2586 intel_dp_hot_plug(struct intel_encoder *intel_encoder)
2587 {
2588         struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base);
2589
2590         intel_dp_check_link_status(intel_dp);
2591 }
2592
2593 /* Return which DP Port should be selected for Transcoder DP control */
2594 int
2595 intel_trans_dp_port_sel(struct drm_crtc *crtc)
2596 {
2597         struct drm_device *dev = crtc->dev;
2598         struct intel_encoder *intel_encoder;
2599         struct intel_dp *intel_dp;
2600
2601         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2602                 intel_dp = enc_to_intel_dp(&intel_encoder->base);
2603
2604                 if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT ||
2605                     intel_encoder->type == INTEL_OUTPUT_EDP)
2606                         return intel_dp->output_reg;
2607         }
2608
2609         return -1;
2610 }
2611
2612 /* check the VBT to see whether the eDP is on DP-D port */
2613 bool intel_dpd_is_edp(struct drm_device *dev)
2614 {
2615         struct drm_i915_private *dev_priv = dev->dev_private;
2616         struct child_device_config *p_child;
2617         int i;
2618
2619         if (!dev_priv->child_dev_num)
2620                 return false;
2621
2622         for (i = 0; i < dev_priv->child_dev_num; i++) {
2623                 p_child = dev_priv->child_dev + i;
2624
2625                 if (p_child->dvo_port == PORT_IDPD &&
2626                     p_child->device_type == DEVICE_TYPE_eDP)
2627                         return true;
2628         }
2629         return false;
2630 }
2631
2632 static void
2633 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector)
2634 {
2635         struct intel_connector *intel_connector = to_intel_connector(connector);
2636
2637         intel_attach_force_audio_property(connector);
2638         intel_attach_broadcast_rgb_property(connector);
2639         intel_dp->color_range_auto = true;
2640
2641         if (is_edp(intel_dp)) {
2642                 drm_mode_create_scaling_mode_property(connector->dev);
2643                 drm_object_attach_property(
2644                         &connector->base,
2645                         connector->dev->mode_config.scaling_mode_property,
2646                         DRM_MODE_SCALE_ASPECT);
2647                 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
2648         }
2649 }
2650
2651 static void
2652 intel_dp_init_panel_power_sequencer(struct drm_device *dev,
2653                                     struct intel_dp *intel_dp,
2654                                     struct edp_power_seq *out)
2655 {
2656         struct drm_i915_private *dev_priv = dev->dev_private;
2657         struct edp_power_seq cur, vbt, spec, final;
2658         u32 pp_on, pp_off, pp_div, pp;
2659
2660         /* Workaround: Need to write PP_CONTROL with the unlock key as
2661          * the very first thing. */
2662         pp = ironlake_get_pp_control(dev_priv);
2663         I915_WRITE(PCH_PP_CONTROL, pp);
2664
2665         pp_on = I915_READ(PCH_PP_ON_DELAYS);
2666         pp_off = I915_READ(PCH_PP_OFF_DELAYS);
2667         pp_div = I915_READ(PCH_PP_DIVISOR);
2668
2669         /* Pull timing values out of registers */
2670         cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >>
2671                 PANEL_POWER_UP_DELAY_SHIFT;
2672
2673         cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >>
2674                 PANEL_LIGHT_ON_DELAY_SHIFT;
2675
2676         cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >>
2677                 PANEL_LIGHT_OFF_DELAY_SHIFT;
2678
2679         cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >>
2680                 PANEL_POWER_DOWN_DELAY_SHIFT;
2681
2682         cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >>
2683                        PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
2684
2685         DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2686                       cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12);
2687
2688         vbt = dev_priv->edp.pps;
2689
2690         /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of
2691          * our hw here, which are all in 100usec. */
2692         spec.t1_t3 = 210 * 10;
2693         spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */
2694         spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */
2695         spec.t10 = 500 * 10;
2696         /* This one is special and actually in units of 100ms, but zero
2697          * based in the hw (so we need to add 100 ms). But the sw vbt
2698          * table multiplies it with 1000 to make it in units of 100usec,
2699          * too. */
2700         spec.t11_t12 = (510 + 100) * 10;
2701
2702         DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n",
2703                       vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12);
2704
2705         /* Use the max of the register settings and vbt. If both are
2706          * unset, fall back to the spec limits. */
2707 #define assign_final(field)     final.field = (max(cur.field, vbt.field) == 0 ? \
2708                                        spec.field : \
2709                                        max(cur.field, vbt.field))
2710         assign_final(t1_t3);
2711         assign_final(t8);
2712         assign_final(t9);
2713         assign_final(t10);
2714         assign_final(t11_t12);
2715 #undef assign_final
2716
2717 #define get_delay(field)        (DIV_ROUND_UP(final.field, 10))
2718         intel_dp->panel_power_up_delay = get_delay(t1_t3);
2719         intel_dp->backlight_on_delay = get_delay(t8);
2720         intel_dp->backlight_off_delay = get_delay(t9);
2721         intel_dp->panel_power_down_delay = get_delay(t10);
2722         intel_dp->panel_power_cycle_delay = get_delay(t11_t12);
2723 #undef get_delay
2724
2725         DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n",
2726                       intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay,
2727                       intel_dp->panel_power_cycle_delay);
2728
2729         DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n",
2730                       intel_dp->backlight_on_delay, intel_dp->backlight_off_delay);
2731
2732         if (out)
2733                 *out = final;
2734 }
2735
2736 static void
2737 intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev,
2738                                               struct intel_dp *intel_dp,
2739                                               struct edp_power_seq *seq)
2740 {
2741         struct drm_i915_private *dev_priv = dev->dev_private;
2742         u32 pp_on, pp_off, pp_div;
2743
2744         /* And finally store the new values in the power sequencer. */
2745         pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) |
2746                 (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
2747         pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) |
2748                  (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
2749         /* Compute the divisor for the pp clock, simply match the Bspec
2750          * formula. */
2751         pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1)
2752                         << PP_REFERENCE_DIVIDER_SHIFT;
2753         pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000)
2754                         << PANEL_POWER_CYCLE_DELAY_SHIFT);
2755
2756         /* Haswell doesn't have any port selection bits for the panel
2757          * power sequencer any more. */
2758         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
2759                 if (is_cpu_edp(intel_dp))
2760                         pp_on |= PANEL_POWER_PORT_DP_A;
2761                 else
2762                         pp_on |= PANEL_POWER_PORT_DP_D;
2763         }
2764
2765         I915_WRITE(PCH_PP_ON_DELAYS, pp_on);
2766         I915_WRITE(PCH_PP_OFF_DELAYS, pp_off);
2767         I915_WRITE(PCH_PP_DIVISOR, pp_div);
2768
2769         DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n",
2770                       I915_READ(PCH_PP_ON_DELAYS),
2771                       I915_READ(PCH_PP_OFF_DELAYS),
2772                       I915_READ(PCH_PP_DIVISOR));
2773 }
2774
2775 void
2776 intel_dp_init_connector(struct intel_digital_port *intel_dig_port,
2777                         struct intel_connector *intel_connector)
2778 {
2779         struct drm_connector *connector = &intel_connector->base;
2780         struct intel_dp *intel_dp = &intel_dig_port->dp;
2781         struct intel_encoder *intel_encoder = &intel_dig_port->base;
2782         struct drm_device *dev = intel_encoder->base.dev;
2783         struct drm_i915_private *dev_priv = dev->dev_private;
2784         struct drm_display_mode *fixed_mode = NULL;
2785         struct edp_power_seq power_seq = { 0 };
2786         enum port port = intel_dig_port->port;
2787         const char *name = NULL;
2788         int type;
2789
2790         /* Preserve the current hw state. */
2791         intel_dp->DP = I915_READ(intel_dp->output_reg);
2792         intel_dp->attached_connector = intel_connector;
2793
2794         if (HAS_PCH_SPLIT(dev) && port == PORT_D)
2795                 if (intel_dpd_is_edp(dev))
2796                         intel_dp->is_pch_edp = true;
2797
2798         /*
2799          * FIXME : We need to initialize built-in panels before external panels.
2800          * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup
2801          */
2802         if (IS_VALLEYVIEW(dev) && port == PORT_C) {
2803                 type = DRM_MODE_CONNECTOR_eDP;
2804                 intel_encoder->type = INTEL_OUTPUT_EDP;
2805         } else if (port == PORT_A || is_pch_edp(intel_dp)) {
2806                 type = DRM_MODE_CONNECTOR_eDP;
2807                 intel_encoder->type = INTEL_OUTPUT_EDP;
2808         } else {
2809                 /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for
2810                  * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't
2811                  * rewrite it.
2812                  */
2813                 type = DRM_MODE_CONNECTOR_DisplayPort;
2814         }
2815
2816         drm_connector_init(dev, connector, &intel_dp_connector_funcs, type);
2817         drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs);
2818
2819         connector->polled = DRM_CONNECTOR_POLL_HPD;
2820         connector->interlace_allowed = true;
2821         connector->doublescan_allowed = 0;
2822
2823         INIT_DELAYED_WORK(&intel_dp->panel_vdd_work,
2824                           ironlake_panel_vdd_work);
2825
2826         intel_connector_attach_encoder(intel_connector, intel_encoder);
2827         drm_sysfs_connector_add(connector);
2828
2829         if (HAS_DDI(dev))
2830                 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state;
2831         else
2832                 intel_connector->get_hw_state = intel_connector_get_hw_state;
2833
2834
2835         /* Set up the DDC bus. */
2836         switch (port) {
2837         case PORT_A:
2838                 name = "DPDDC-A";
2839                 break;
2840         case PORT_B:
2841                 dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS;
2842                 name = "DPDDC-B";
2843                 break;
2844         case PORT_C:
2845                 dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS;
2846                 name = "DPDDC-C";
2847                 break;
2848         case PORT_D:
2849                 dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS;
2850                 name = "DPDDC-D";
2851                 break;
2852         default:
2853                 WARN(1, "Invalid port %c\n", port_name(port));
2854                 break;
2855         }
2856
2857         if (is_edp(intel_dp))
2858                 intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq);
2859
2860         intel_dp_i2c_init(intel_dp, intel_connector, name);
2861
2862         /* Cache DPCD and EDID for edp. */
2863         if (is_edp(intel_dp)) {
2864                 bool ret;
2865                 struct drm_display_mode *scan;
2866                 struct edid *edid;
2867
2868                 ironlake_edp_panel_vdd_on(intel_dp);
2869                 ret = intel_dp_get_dpcd(intel_dp);
2870                 ironlake_edp_panel_vdd_off(intel_dp, false);
2871
2872                 if (ret) {
2873                         if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11)
2874                                 dev_priv->no_aux_handshake =
2875                                         intel_dp->dpcd[DP_MAX_DOWNSPREAD] &
2876                                         DP_NO_AUX_HANDSHAKE_LINK_TRAINING;
2877                 } else {
2878                         /* if this fails, presume the device is a ghost */
2879                         DRM_INFO("failed to retrieve link info, disabling eDP\n");
2880                         intel_dp_encoder_destroy(&intel_encoder->base);
2881                         intel_dp_destroy(connector);
2882                         return;
2883                 }
2884
2885                 /* We now know it's not a ghost, init power sequence regs. */
2886                 intel_dp_init_panel_power_sequencer_registers(dev, intel_dp,
2887                                                               &power_seq);
2888
2889                 ironlake_edp_panel_vdd_on(intel_dp);
2890                 edid = drm_get_edid(connector, &intel_dp->adapter);
2891                 if (edid) {
2892                         if (drm_add_edid_modes(connector, edid)) {
2893                                 drm_mode_connector_update_edid_property(connector, edid);
2894                                 drm_edid_to_eld(connector, edid);
2895                         } else {
2896                                 kfree(edid);
2897                                 edid = ERR_PTR(-EINVAL);
2898                         }
2899                 } else {
2900                         edid = ERR_PTR(-ENOENT);
2901                 }
2902                 intel_connector->edid = edid;
2903
2904                 /* prefer fixed mode from EDID if available */
2905                 list_for_each_entry(scan, &connector->probed_modes, head) {
2906                         if ((scan->type & DRM_MODE_TYPE_PREFERRED)) {
2907                                 fixed_mode = drm_mode_duplicate(dev, scan);
2908                                 break;
2909                         }
2910                 }
2911
2912                 /* fallback to VBT if available for eDP */
2913                 if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) {
2914                         fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
2915                         if (fixed_mode)
2916                                 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
2917                 }
2918
2919                 ironlake_edp_panel_vdd_off(intel_dp, false);
2920         }
2921
2922         if (is_edp(intel_dp)) {
2923                 intel_panel_init(&intel_connector->panel, fixed_mode);
2924                 intel_panel_setup_backlight(connector);
2925         }
2926
2927         intel_dp_add_properties(intel_dp, connector);
2928
2929         /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written
2930          * 0xd.  Failure to do so will result in spurious interrupts being
2931          * generated on the port when a cable is not attached.
2932          */
2933         if (IS_G4X(dev) && !IS_GM45(dev)) {
2934                 u32 temp = I915_READ(PEG_BAND_GAP_DATA);
2935                 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd);
2936         }
2937 }
2938
2939 void
2940 intel_dp_init(struct drm_device *dev, int output_reg, enum port port)
2941 {
2942         struct intel_digital_port *intel_dig_port;
2943         struct intel_encoder *intel_encoder;
2944         struct drm_encoder *encoder;
2945         struct intel_connector *intel_connector;
2946
2947         intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL);
2948         if (!intel_dig_port)
2949                 return;
2950
2951         intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
2952         if (!intel_connector) {
2953                 kfree(intel_dig_port);
2954                 return;
2955         }
2956
2957         intel_encoder = &intel_dig_port->base;
2958         encoder = &intel_encoder->base;
2959
2960         drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs,
2961                          DRM_MODE_ENCODER_TMDS);
2962         drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs);
2963
2964         intel_encoder->enable = intel_enable_dp;
2965         intel_encoder->pre_enable = intel_pre_enable_dp;
2966         intel_encoder->disable = intel_disable_dp;
2967         intel_encoder->post_disable = intel_post_disable_dp;
2968         intel_encoder->get_hw_state = intel_dp_get_hw_state;
2969
2970         intel_dig_port->port = port;
2971         intel_dig_port->dp.output_reg = output_reg;
2972
2973         intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT;
2974         intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
2975         intel_encoder->cloneable = false;
2976         intel_encoder->hot_plug = intel_dp_hot_plug;
2977
2978         intel_dp_init_connector(intel_dig_port, intel_connector);
2979 }