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44 * Configuration and status register (CSR) type definitions for
47 * This file is auto generated. Do not edit.
52 #ifndef __CVMX_USBNX_TYPEDEFS_H__
53 #define __CVMX_USBNX_TYPEDEFS_H__
55 #define CVMX_USBNX_BIST_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00011800680007F8ull) + ((block_id) & 1) * 0x10000000ull)
56 #define CVMX_USBNX_CLK_CTL(block_id) (CVMX_ADD_IO_SEG(0x0001180068000010ull) + ((block_id) & 1) * 0x10000000ull)
57 #define CVMX_USBNX_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000800ull) + ((block_id) & 1) * 0x100000000000ull)
58 #define CVMX_USBNX_DMA0_INB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000818ull) + ((block_id) & 1) * 0x100000000000ull)
59 #define CVMX_USBNX_DMA0_INB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000820ull) + ((block_id) & 1) * 0x100000000000ull)
60 #define CVMX_USBNX_DMA0_INB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000828ull) + ((block_id) & 1) * 0x100000000000ull)
61 #define CVMX_USBNX_DMA0_INB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000830ull) + ((block_id) & 1) * 0x100000000000ull)
62 #define CVMX_USBNX_DMA0_INB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000838ull) + ((block_id) & 1) * 0x100000000000ull)
63 #define CVMX_USBNX_DMA0_INB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000840ull) + ((block_id) & 1) * 0x100000000000ull)
64 #define CVMX_USBNX_DMA0_INB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000848ull) + ((block_id) & 1) * 0x100000000000ull)
65 #define CVMX_USBNX_DMA0_INB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000850ull) + ((block_id) & 1) * 0x100000000000ull)
66 #define CVMX_USBNX_DMA0_OUTB_CHN0(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000858ull) + ((block_id) & 1) * 0x100000000000ull)
67 #define CVMX_USBNX_DMA0_OUTB_CHN1(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000860ull) + ((block_id) & 1) * 0x100000000000ull)
68 #define CVMX_USBNX_DMA0_OUTB_CHN2(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000868ull) + ((block_id) & 1) * 0x100000000000ull)
69 #define CVMX_USBNX_DMA0_OUTB_CHN3(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000870ull) + ((block_id) & 1) * 0x100000000000ull)
70 #define CVMX_USBNX_DMA0_OUTB_CHN4(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000878ull) + ((block_id) & 1) * 0x100000000000ull)
71 #define CVMX_USBNX_DMA0_OUTB_CHN5(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000880ull) + ((block_id) & 1) * 0x100000000000ull)
72 #define CVMX_USBNX_DMA0_OUTB_CHN6(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000888ull) + ((block_id) & 1) * 0x100000000000ull)
73 #define CVMX_USBNX_DMA0_OUTB_CHN7(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000890ull) + ((block_id) & 1) * 0x100000000000ull)
74 #define CVMX_USBNX_DMA_TEST(block_id) (CVMX_ADD_IO_SEG(0x00016F0000000808ull) + ((block_id) & 1) * 0x100000000000ull)
75 #define CVMX_USBNX_INT_ENB(block_id) (CVMX_ADD_IO_SEG(0x0001180068000008ull) + ((block_id) & 1) * 0x10000000ull)
76 #define CVMX_USBNX_INT_SUM(block_id) (CVMX_ADD_IO_SEG(0x0001180068000000ull) + ((block_id) & 1) * 0x10000000ull)
77 #define CVMX_USBNX_USBP_CTL_STATUS(block_id) (CVMX_ADD_IO_SEG(0x0001180068000018ull) + ((block_id) & 1) * 0x10000000ull)
80 * cvmx_usbn#_bist_status
82 * USBN_BIST_STATUS = USBN's Control and Status
84 * Contain general control bits and status information for the USBN.
86 union cvmx_usbnx_bist_status
89 struct cvmx_usbnx_bist_status_s
91 uint64_t reserved_7_63 : 57;
92 uint64_t u2nc_bis : 1; /**< Bist status U2N CTL FIFO Memory. */
93 uint64_t u2nf_bis : 1; /**< Bist status U2N FIFO Memory. */
94 uint64_t e2hc_bis : 1; /**< Bist status E2H CTL FIFO Memory. */
95 uint64_t n2uf_bis : 1; /**< Bist status N2U FIFO Memory. */
96 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
97 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
98 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
100 struct cvmx_usbnx_bist_status_cn30xx
102 uint64_t reserved_3_63 : 61;
103 uint64_t usbc_bis : 1; /**< Bist status USBC FIFO Memory. */
104 uint64_t nif_bis : 1; /**< Bist status for Inbound Memory. */
105 uint64_t nof_bis : 1; /**< Bist status for Outbound Memory. */
107 struct cvmx_usbnx_bist_status_cn30xx cn31xx;
108 struct cvmx_usbnx_bist_status_s cn50xx;
109 struct cvmx_usbnx_bist_status_s cn52xx;
110 struct cvmx_usbnx_bist_status_s cn52xxp1;
111 struct cvmx_usbnx_bist_status_s cn56xx;
112 struct cvmx_usbnx_bist_status_s cn56xxp1;
114 typedef union cvmx_usbnx_bist_status cvmx_usbnx_bist_status_t;
119 * USBN_CLK_CTL = USBN's Clock Control
121 * This register is used to control the frequency of the hclk and the hreset and phy_rst signals.
123 union cvmx_usbnx_clk_ctl
126 struct cvmx_usbnx_clk_ctl_s
128 uint64_t reserved_20_63 : 44;
129 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
131 Also see the field DIVIDE. DIVIDE2<1> must currently
132 be zero because it is not implemented, so the maximum
133 ratio of eclk/hclk is currently 16.
134 The actual divide number for hclk is:
135 (DIVIDE2 + 1) * (DIVIDE + 1) */
136 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
137 generate the hclk in the USB Subsystem is held
138 in reset. This bit must be set to '0' before
139 changing the value os DIVIDE in this register.
140 The reset to the HCLK_DIVIDERis also asserted
141 when core reset is asserted. */
142 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
143 '1' USB-PHY XO block is powered-down during
145 '0' USB-PHY XO block is powered-up during
147 The value of this field must be set while POR is
149 uint64_t reserved_14_15 : 2;
150 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
151 remain powered in Suspend Mode.
152 '1' The USB-PHY XO Bias, Bandgap and PLL are
153 powered down in suspend mode.
154 The value of this field must be set while POR is
156 uint64_t p_c_sel : 2; /**< Phy clock speed select.
157 Selects the reference clock / crystal frequency.
159 '10': 48 MHz (reserved when a crystal is used)
160 '01': 24 MHz (reserved when a crystal is used)
162 The value of this field must be set while POR is
164 NOTE: if a crystal is used as a reference clock,
165 this field must be set to 12 MHz. */
166 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
167 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
168 in the USBC, for normal operation this must be '0'. */
169 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
170 to '1' transition. */
171 uint64_t por : 1; /**< Power On Reset for the PHY.
172 Resets all the PHYS registers and state machines. */
173 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
174 '0' the hclk will not be generated. SEE DIVIDE
175 field of this register. */
176 uint64_t prst : 1; /**< When this field is '0' the reset associated with
177 the phy_clk functionality in the USB Subsystem is
178 help in reset. This bit should not be set to '1'
179 until the time it takes 6 clocks (hclk or phy_clk,
180 whichever is slower) has passed. Under normal
181 operation once this bit is set to '1' it should not
183 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
184 the hclk functioanlity in the USB Subsystem is
185 held in reset.This bit should not be set to '1'
186 until 12ms after phy_clk is stable. Under normal
187 operation, once this bit is set to '1' it should
188 not be set to '0'. */
189 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
190 is the eclk frequency divided by the value of
191 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
192 DIVIDE2 of this register.
193 The hclk frequency should be less than 125Mhz.
194 After writing a value to this field the SW should
195 read the field for the value written.
196 The ENABLE field of this register should not be set
197 until AFTER this field is set and then read. */
199 struct cvmx_usbnx_clk_ctl_cn30xx
201 uint64_t reserved_18_63 : 46;
202 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
203 generate the hclk in the USB Subsystem is held
204 in reset. This bit must be set to '0' before
205 changing the value os DIVIDE in this register.
206 The reset to the HCLK_DIVIDERis also asserted
207 when core reset is asserted. */
208 uint64_t p_x_on : 1; /**< Force USB-PHY on during suspend.
209 '1' USB-PHY XO block is powered-down during
211 '0' USB-PHY XO block is powered-up during
213 The value of this field must be set while POR is
215 uint64_t p_rclk : 1; /**< Phy refrence clock enable.
216 '1' The PHY PLL uses the XO block output as a
219 uint64_t p_xenbn : 1; /**< Phy external clock enable.
220 '1' The XO block uses the clock from a crystal.
221 '0' The XO block uses an external clock supplied
222 on the XO pin. USB_XI should be tied to
223 ground for this usage. */
224 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
225 remain powered in Suspend Mode.
226 '1' The USB-PHY XO Bias, Bandgap and PLL are
227 powered down in suspend mode.
228 The value of this field must be set while POR is
230 uint64_t p_c_sel : 2; /**< Phy clock speed select.
231 Selects the reference clock / crystal frequency.
236 The value of this field must be set while POR is
238 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
239 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
240 in the USBC, for normal operation this must be '0'. */
241 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
242 to '1' transition. */
243 uint64_t por : 1; /**< Power On Reset for the PHY.
244 Resets all the PHYS registers and state machines. */
245 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
246 '0' the hclk will not be generated. */
247 uint64_t prst : 1; /**< When this field is '0' the reset associated with
248 the phy_clk functionality in the USB Subsystem is
249 help in reset. This bit should not be set to '1'
250 until the time it takes 6 clocks (hclk or phy_clk,
251 whichever is slower) has passed. Under normal
252 operation once this bit is set to '1' it should not
254 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
255 the hclk functioanlity in the USB Subsystem is
256 held in reset.This bit should not be set to '1'
257 until 12ms after phy_clk is stable. Under normal
258 operation, once this bit is set to '1' it should
259 not be set to '0'. */
260 uint64_t divide : 3; /**< The 'hclk' used by the USB subsystem is derived
261 from the eclk. The eclk will be divided by the
262 value of this field +1 to determine the hclk
263 frequency. (Also see HRST of this register).
264 The hclk frequency must be less than 125 MHz. */
266 struct cvmx_usbnx_clk_ctl_cn30xx cn31xx;
267 struct cvmx_usbnx_clk_ctl_cn50xx
269 uint64_t reserved_20_63 : 44;
270 uint64_t divide2 : 2; /**< The 'hclk' used by the USB subsystem is derived
272 Also see the field DIVIDE. DIVIDE2<1> must currently
273 be zero because it is not implemented, so the maximum
274 ratio of eclk/hclk is currently 16.
275 The actual divide number for hclk is:
276 (DIVIDE2 + 1) * (DIVIDE + 1) */
277 uint64_t hclk_rst : 1; /**< When this field is '0' the HCLK-DIVIDER used to
278 generate the hclk in the USB Subsystem is held
279 in reset. This bit must be set to '0' before
280 changing the value os DIVIDE in this register.
281 The reset to the HCLK_DIVIDERis also asserted
282 when core reset is asserted. */
283 uint64_t reserved_16_16 : 1;
284 uint64_t p_rtype : 2; /**< PHY reference clock type
285 '0' The USB-PHY uses a 12MHz crystal as a clock
286 source at the USB_XO and USB_XI pins
288 '2' The USB_PHY uses 12/24/48MHz 2.5V board clock
289 at the USB_XO pin. USB_XI should be tied to
292 (bit 14 was P_XENBN on 3xxx)
293 (bit 15 was P_RCLK on 3xxx) */
294 uint64_t p_com_on : 1; /**< '0' Force USB-PHY XO Bias, Bandgap and PLL to
295 remain powered in Suspend Mode.
296 '1' The USB-PHY XO Bias, Bandgap and PLL are
297 powered down in suspend mode.
298 The value of this field must be set while POR is
300 uint64_t p_c_sel : 2; /**< Phy clock speed select.
301 Selects the reference clock / crystal frequency.
303 '10': 48 MHz (reserved when a crystal is used)
304 '01': 24 MHz (reserved when a crystal is used)
306 The value of this field must be set while POR is
308 NOTE: if a crystal is used as a reference clock,
309 this field must be set to 12 MHz. */
310 uint64_t cdiv_byp : 1; /**< Used to enable the bypass input to the USB_CLK_DIV. */
311 uint64_t sd_mode : 2; /**< Scaledown mode for the USBC. Control timing events
312 in the USBC, for normal operation this must be '0'. */
313 uint64_t s_bist : 1; /**< Starts bist on the hclk memories, during the '0'
314 to '1' transition. */
315 uint64_t por : 1; /**< Power On Reset for the PHY.
316 Resets all the PHYS registers and state machines. */
317 uint64_t enable : 1; /**< When '1' allows the generation of the hclk. When
318 '0' the hclk will not be generated. SEE DIVIDE
319 field of this register. */
320 uint64_t prst : 1; /**< When this field is '0' the reset associated with
321 the phy_clk functionality in the USB Subsystem is
322 help in reset. This bit should not be set to '1'
323 until the time it takes 6 clocks (hclk or phy_clk,
324 whichever is slower) has passed. Under normal
325 operation once this bit is set to '1' it should not
327 uint64_t hrst : 1; /**< When this field is '0' the reset associated with
328 the hclk functioanlity in the USB Subsystem is
329 held in reset.This bit should not be set to '1'
330 until 12ms after phy_clk is stable. Under normal
331 operation, once this bit is set to '1' it should
332 not be set to '0'. */
333 uint64_t divide : 3; /**< The frequency of 'hclk' used by the USB subsystem
334 is the eclk frequency divided by the value of
335 (DIVIDE2 + 1) * (DIVIDE + 1), also see the field
336 DIVIDE2 of this register.
337 The hclk frequency should be less than 125Mhz.
338 After writing a value to this field the SW should
339 read the field for the value written.
340 The ENABLE field of this register should not be set
341 until AFTER this field is set and then read. */
343 struct cvmx_usbnx_clk_ctl_cn50xx cn52xx;
344 struct cvmx_usbnx_clk_ctl_cn50xx cn52xxp1;
345 struct cvmx_usbnx_clk_ctl_cn50xx cn56xx;
346 struct cvmx_usbnx_clk_ctl_cn50xx cn56xxp1;
348 typedef union cvmx_usbnx_clk_ctl cvmx_usbnx_clk_ctl_t;
351 * cvmx_usbn#_ctl_status
353 * USBN_CTL_STATUS = USBN's Control And Status Register
355 * Contains general control and status information for the USBN block.
357 union cvmx_usbnx_ctl_status
360 struct cvmx_usbnx_ctl_status_s
362 uint64_t reserved_6_63 : 58;
363 uint64_t dma_0pag : 1; /**< When '1' sets the DMA engine will set the zero-Page
364 bit in the L2C store operation to the IOB. */
365 uint64_t dma_stt : 1; /**< When '1' sets the DMA engine to use STT operations. */
366 uint64_t dma_test : 1; /**< When '1' sets the DMA engine into Test-Mode.
367 For normal operation this bit should be '0'. */
368 uint64_t inv_a2 : 1; /**< When '1' causes the address[2] driven on the AHB
369 for USB-CORE FIFO access to be inverted. Also data
370 writen to and read from the AHB will have it byte
371 order swapped. If the orginal order was A-B-C-D the
372 new byte order will be D-C-B-A. */
373 uint64_t l2c_emod : 2; /**< Endian format for data from/to the L2C.
375 OUT0: A-B-C-D-E-F-G-H
376 OUT1: H-G-F-E-D-C-B-A
377 OUT2: D-C-B-A-H-G-F-E
378 OUT3: E-F-G-H-A-B-C-D */
380 struct cvmx_usbnx_ctl_status_s cn30xx;
381 struct cvmx_usbnx_ctl_status_s cn31xx;
382 struct cvmx_usbnx_ctl_status_s cn50xx;
383 struct cvmx_usbnx_ctl_status_s cn52xx;
384 struct cvmx_usbnx_ctl_status_s cn52xxp1;
385 struct cvmx_usbnx_ctl_status_s cn56xx;
386 struct cvmx_usbnx_ctl_status_s cn56xxp1;
388 typedef union cvmx_usbnx_ctl_status cvmx_usbnx_ctl_status_t;
391 * cvmx_usbn#_dma0_inb_chn0
393 * USBN_DMA0_INB_CHN0 = USBN's Inbound DMA for USB0 Channel0
395 * Contains the starting address for use when USB0 writes to L2C via Channel0.
396 * Writing of this register sets the base address.
398 union cvmx_usbnx_dma0_inb_chn0
401 struct cvmx_usbnx_dma0_inb_chn0_s
403 uint64_t reserved_36_63 : 28;
404 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
406 struct cvmx_usbnx_dma0_inb_chn0_s cn30xx;
407 struct cvmx_usbnx_dma0_inb_chn0_s cn31xx;
408 struct cvmx_usbnx_dma0_inb_chn0_s cn50xx;
409 struct cvmx_usbnx_dma0_inb_chn0_s cn52xx;
410 struct cvmx_usbnx_dma0_inb_chn0_s cn52xxp1;
411 struct cvmx_usbnx_dma0_inb_chn0_s cn56xx;
412 struct cvmx_usbnx_dma0_inb_chn0_s cn56xxp1;
414 typedef union cvmx_usbnx_dma0_inb_chn0 cvmx_usbnx_dma0_inb_chn0_t;
417 * cvmx_usbn#_dma0_inb_chn1
419 * USBN_DMA0_INB_CHN1 = USBN's Inbound DMA for USB0 Channel1
421 * Contains the starting address for use when USB0 writes to L2C via Channel1.
422 * Writing of this register sets the base address.
424 union cvmx_usbnx_dma0_inb_chn1
427 struct cvmx_usbnx_dma0_inb_chn1_s
429 uint64_t reserved_36_63 : 28;
430 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
432 struct cvmx_usbnx_dma0_inb_chn1_s cn30xx;
433 struct cvmx_usbnx_dma0_inb_chn1_s cn31xx;
434 struct cvmx_usbnx_dma0_inb_chn1_s cn50xx;
435 struct cvmx_usbnx_dma0_inb_chn1_s cn52xx;
436 struct cvmx_usbnx_dma0_inb_chn1_s cn52xxp1;
437 struct cvmx_usbnx_dma0_inb_chn1_s cn56xx;
438 struct cvmx_usbnx_dma0_inb_chn1_s cn56xxp1;
440 typedef union cvmx_usbnx_dma0_inb_chn1 cvmx_usbnx_dma0_inb_chn1_t;
443 * cvmx_usbn#_dma0_inb_chn2
445 * USBN_DMA0_INB_CHN2 = USBN's Inbound DMA for USB0 Channel2
447 * Contains the starting address for use when USB0 writes to L2C via Channel2.
448 * Writing of this register sets the base address.
450 union cvmx_usbnx_dma0_inb_chn2
453 struct cvmx_usbnx_dma0_inb_chn2_s
455 uint64_t reserved_36_63 : 28;
456 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
458 struct cvmx_usbnx_dma0_inb_chn2_s cn30xx;
459 struct cvmx_usbnx_dma0_inb_chn2_s cn31xx;
460 struct cvmx_usbnx_dma0_inb_chn2_s cn50xx;
461 struct cvmx_usbnx_dma0_inb_chn2_s cn52xx;
462 struct cvmx_usbnx_dma0_inb_chn2_s cn52xxp1;
463 struct cvmx_usbnx_dma0_inb_chn2_s cn56xx;
464 struct cvmx_usbnx_dma0_inb_chn2_s cn56xxp1;
466 typedef union cvmx_usbnx_dma0_inb_chn2 cvmx_usbnx_dma0_inb_chn2_t;
469 * cvmx_usbn#_dma0_inb_chn3
471 * USBN_DMA0_INB_CHN3 = USBN's Inbound DMA for USB0 Channel3
473 * Contains the starting address for use when USB0 writes to L2C via Channel3.
474 * Writing of this register sets the base address.
476 union cvmx_usbnx_dma0_inb_chn3
479 struct cvmx_usbnx_dma0_inb_chn3_s
481 uint64_t reserved_36_63 : 28;
482 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
484 struct cvmx_usbnx_dma0_inb_chn3_s cn30xx;
485 struct cvmx_usbnx_dma0_inb_chn3_s cn31xx;
486 struct cvmx_usbnx_dma0_inb_chn3_s cn50xx;
487 struct cvmx_usbnx_dma0_inb_chn3_s cn52xx;
488 struct cvmx_usbnx_dma0_inb_chn3_s cn52xxp1;
489 struct cvmx_usbnx_dma0_inb_chn3_s cn56xx;
490 struct cvmx_usbnx_dma0_inb_chn3_s cn56xxp1;
492 typedef union cvmx_usbnx_dma0_inb_chn3 cvmx_usbnx_dma0_inb_chn3_t;
495 * cvmx_usbn#_dma0_inb_chn4
497 * USBN_DMA0_INB_CHN4 = USBN's Inbound DMA for USB0 Channel4
499 * Contains the starting address for use when USB0 writes to L2C via Channel4.
500 * Writing of this register sets the base address.
502 union cvmx_usbnx_dma0_inb_chn4
505 struct cvmx_usbnx_dma0_inb_chn4_s
507 uint64_t reserved_36_63 : 28;
508 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
510 struct cvmx_usbnx_dma0_inb_chn4_s cn30xx;
511 struct cvmx_usbnx_dma0_inb_chn4_s cn31xx;
512 struct cvmx_usbnx_dma0_inb_chn4_s cn50xx;
513 struct cvmx_usbnx_dma0_inb_chn4_s cn52xx;
514 struct cvmx_usbnx_dma0_inb_chn4_s cn52xxp1;
515 struct cvmx_usbnx_dma0_inb_chn4_s cn56xx;
516 struct cvmx_usbnx_dma0_inb_chn4_s cn56xxp1;
518 typedef union cvmx_usbnx_dma0_inb_chn4 cvmx_usbnx_dma0_inb_chn4_t;
521 * cvmx_usbn#_dma0_inb_chn5
523 * USBN_DMA0_INB_CHN5 = USBN's Inbound DMA for USB0 Channel5
525 * Contains the starting address for use when USB0 writes to L2C via Channel5.
526 * Writing of this register sets the base address.
528 union cvmx_usbnx_dma0_inb_chn5
531 struct cvmx_usbnx_dma0_inb_chn5_s
533 uint64_t reserved_36_63 : 28;
534 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
536 struct cvmx_usbnx_dma0_inb_chn5_s cn30xx;
537 struct cvmx_usbnx_dma0_inb_chn5_s cn31xx;
538 struct cvmx_usbnx_dma0_inb_chn5_s cn50xx;
539 struct cvmx_usbnx_dma0_inb_chn5_s cn52xx;
540 struct cvmx_usbnx_dma0_inb_chn5_s cn52xxp1;
541 struct cvmx_usbnx_dma0_inb_chn5_s cn56xx;
542 struct cvmx_usbnx_dma0_inb_chn5_s cn56xxp1;
544 typedef union cvmx_usbnx_dma0_inb_chn5 cvmx_usbnx_dma0_inb_chn5_t;
547 * cvmx_usbn#_dma0_inb_chn6
549 * USBN_DMA0_INB_CHN6 = USBN's Inbound DMA for USB0 Channel6
551 * Contains the starting address for use when USB0 writes to L2C via Channel6.
552 * Writing of this register sets the base address.
554 union cvmx_usbnx_dma0_inb_chn6
557 struct cvmx_usbnx_dma0_inb_chn6_s
559 uint64_t reserved_36_63 : 28;
560 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
562 struct cvmx_usbnx_dma0_inb_chn6_s cn30xx;
563 struct cvmx_usbnx_dma0_inb_chn6_s cn31xx;
564 struct cvmx_usbnx_dma0_inb_chn6_s cn50xx;
565 struct cvmx_usbnx_dma0_inb_chn6_s cn52xx;
566 struct cvmx_usbnx_dma0_inb_chn6_s cn52xxp1;
567 struct cvmx_usbnx_dma0_inb_chn6_s cn56xx;
568 struct cvmx_usbnx_dma0_inb_chn6_s cn56xxp1;
570 typedef union cvmx_usbnx_dma0_inb_chn6 cvmx_usbnx_dma0_inb_chn6_t;
573 * cvmx_usbn#_dma0_inb_chn7
575 * USBN_DMA0_INB_CHN7 = USBN's Inbound DMA for USB0 Channel7
577 * Contains the starting address for use when USB0 writes to L2C via Channel7.
578 * Writing of this register sets the base address.
580 union cvmx_usbnx_dma0_inb_chn7
583 struct cvmx_usbnx_dma0_inb_chn7_s
585 uint64_t reserved_36_63 : 28;
586 uint64_t addr : 36; /**< Base address for DMA Write to L2C. */
588 struct cvmx_usbnx_dma0_inb_chn7_s cn30xx;
589 struct cvmx_usbnx_dma0_inb_chn7_s cn31xx;
590 struct cvmx_usbnx_dma0_inb_chn7_s cn50xx;
591 struct cvmx_usbnx_dma0_inb_chn7_s cn52xx;
592 struct cvmx_usbnx_dma0_inb_chn7_s cn52xxp1;
593 struct cvmx_usbnx_dma0_inb_chn7_s cn56xx;
594 struct cvmx_usbnx_dma0_inb_chn7_s cn56xxp1;
596 typedef union cvmx_usbnx_dma0_inb_chn7 cvmx_usbnx_dma0_inb_chn7_t;
599 * cvmx_usbn#_dma0_outb_chn0
601 * USBN_DMA0_OUTB_CHN0 = USBN's Outbound DMA for USB0 Channel0
603 * Contains the starting address for use when USB0 reads from L2C via Channel0.
604 * Writing of this register sets the base address.
606 union cvmx_usbnx_dma0_outb_chn0
609 struct cvmx_usbnx_dma0_outb_chn0_s
611 uint64_t reserved_36_63 : 28;
612 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
614 struct cvmx_usbnx_dma0_outb_chn0_s cn30xx;
615 struct cvmx_usbnx_dma0_outb_chn0_s cn31xx;
616 struct cvmx_usbnx_dma0_outb_chn0_s cn50xx;
617 struct cvmx_usbnx_dma0_outb_chn0_s cn52xx;
618 struct cvmx_usbnx_dma0_outb_chn0_s cn52xxp1;
619 struct cvmx_usbnx_dma0_outb_chn0_s cn56xx;
620 struct cvmx_usbnx_dma0_outb_chn0_s cn56xxp1;
622 typedef union cvmx_usbnx_dma0_outb_chn0 cvmx_usbnx_dma0_outb_chn0_t;
625 * cvmx_usbn#_dma0_outb_chn1
627 * USBN_DMA0_OUTB_CHN1 = USBN's Outbound DMA for USB0 Channel1
629 * Contains the starting address for use when USB0 reads from L2C via Channel1.
630 * Writing of this register sets the base address.
632 union cvmx_usbnx_dma0_outb_chn1
635 struct cvmx_usbnx_dma0_outb_chn1_s
637 uint64_t reserved_36_63 : 28;
638 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
640 struct cvmx_usbnx_dma0_outb_chn1_s cn30xx;
641 struct cvmx_usbnx_dma0_outb_chn1_s cn31xx;
642 struct cvmx_usbnx_dma0_outb_chn1_s cn50xx;
643 struct cvmx_usbnx_dma0_outb_chn1_s cn52xx;
644 struct cvmx_usbnx_dma0_outb_chn1_s cn52xxp1;
645 struct cvmx_usbnx_dma0_outb_chn1_s cn56xx;
646 struct cvmx_usbnx_dma0_outb_chn1_s cn56xxp1;
648 typedef union cvmx_usbnx_dma0_outb_chn1 cvmx_usbnx_dma0_outb_chn1_t;
651 * cvmx_usbn#_dma0_outb_chn2
653 * USBN_DMA0_OUTB_CHN2 = USBN's Outbound DMA for USB0 Channel2
655 * Contains the starting address for use when USB0 reads from L2C via Channel2.
656 * Writing of this register sets the base address.
658 union cvmx_usbnx_dma0_outb_chn2
661 struct cvmx_usbnx_dma0_outb_chn2_s
663 uint64_t reserved_36_63 : 28;
664 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
666 struct cvmx_usbnx_dma0_outb_chn2_s cn30xx;
667 struct cvmx_usbnx_dma0_outb_chn2_s cn31xx;
668 struct cvmx_usbnx_dma0_outb_chn2_s cn50xx;
669 struct cvmx_usbnx_dma0_outb_chn2_s cn52xx;
670 struct cvmx_usbnx_dma0_outb_chn2_s cn52xxp1;
671 struct cvmx_usbnx_dma0_outb_chn2_s cn56xx;
672 struct cvmx_usbnx_dma0_outb_chn2_s cn56xxp1;
674 typedef union cvmx_usbnx_dma0_outb_chn2 cvmx_usbnx_dma0_outb_chn2_t;
677 * cvmx_usbn#_dma0_outb_chn3
679 * USBN_DMA0_OUTB_CHN3 = USBN's Outbound DMA for USB0 Channel3
681 * Contains the starting address for use when USB0 reads from L2C via Channel3.
682 * Writing of this register sets the base address.
684 union cvmx_usbnx_dma0_outb_chn3
687 struct cvmx_usbnx_dma0_outb_chn3_s
689 uint64_t reserved_36_63 : 28;
690 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
692 struct cvmx_usbnx_dma0_outb_chn3_s cn30xx;
693 struct cvmx_usbnx_dma0_outb_chn3_s cn31xx;
694 struct cvmx_usbnx_dma0_outb_chn3_s cn50xx;
695 struct cvmx_usbnx_dma0_outb_chn3_s cn52xx;
696 struct cvmx_usbnx_dma0_outb_chn3_s cn52xxp1;
697 struct cvmx_usbnx_dma0_outb_chn3_s cn56xx;
698 struct cvmx_usbnx_dma0_outb_chn3_s cn56xxp1;
700 typedef union cvmx_usbnx_dma0_outb_chn3 cvmx_usbnx_dma0_outb_chn3_t;
703 * cvmx_usbn#_dma0_outb_chn4
705 * USBN_DMA0_OUTB_CHN4 = USBN's Outbound DMA for USB0 Channel4
707 * Contains the starting address for use when USB0 reads from L2C via Channel4.
708 * Writing of this register sets the base address.
710 union cvmx_usbnx_dma0_outb_chn4
713 struct cvmx_usbnx_dma0_outb_chn4_s
715 uint64_t reserved_36_63 : 28;
716 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
718 struct cvmx_usbnx_dma0_outb_chn4_s cn30xx;
719 struct cvmx_usbnx_dma0_outb_chn4_s cn31xx;
720 struct cvmx_usbnx_dma0_outb_chn4_s cn50xx;
721 struct cvmx_usbnx_dma0_outb_chn4_s cn52xx;
722 struct cvmx_usbnx_dma0_outb_chn4_s cn52xxp1;
723 struct cvmx_usbnx_dma0_outb_chn4_s cn56xx;
724 struct cvmx_usbnx_dma0_outb_chn4_s cn56xxp1;
726 typedef union cvmx_usbnx_dma0_outb_chn4 cvmx_usbnx_dma0_outb_chn4_t;
729 * cvmx_usbn#_dma0_outb_chn5
731 * USBN_DMA0_OUTB_CHN5 = USBN's Outbound DMA for USB0 Channel5
733 * Contains the starting address for use when USB0 reads from L2C via Channel5.
734 * Writing of this register sets the base address.
736 union cvmx_usbnx_dma0_outb_chn5
739 struct cvmx_usbnx_dma0_outb_chn5_s
741 uint64_t reserved_36_63 : 28;
742 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
744 struct cvmx_usbnx_dma0_outb_chn5_s cn30xx;
745 struct cvmx_usbnx_dma0_outb_chn5_s cn31xx;
746 struct cvmx_usbnx_dma0_outb_chn5_s cn50xx;
747 struct cvmx_usbnx_dma0_outb_chn5_s cn52xx;
748 struct cvmx_usbnx_dma0_outb_chn5_s cn52xxp1;
749 struct cvmx_usbnx_dma0_outb_chn5_s cn56xx;
750 struct cvmx_usbnx_dma0_outb_chn5_s cn56xxp1;
752 typedef union cvmx_usbnx_dma0_outb_chn5 cvmx_usbnx_dma0_outb_chn5_t;
755 * cvmx_usbn#_dma0_outb_chn6
757 * USBN_DMA0_OUTB_CHN6 = USBN's Outbound DMA for USB0 Channel6
759 * Contains the starting address for use when USB0 reads from L2C via Channel6.
760 * Writing of this register sets the base address.
762 union cvmx_usbnx_dma0_outb_chn6
765 struct cvmx_usbnx_dma0_outb_chn6_s
767 uint64_t reserved_36_63 : 28;
768 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
770 struct cvmx_usbnx_dma0_outb_chn6_s cn30xx;
771 struct cvmx_usbnx_dma0_outb_chn6_s cn31xx;
772 struct cvmx_usbnx_dma0_outb_chn6_s cn50xx;
773 struct cvmx_usbnx_dma0_outb_chn6_s cn52xx;
774 struct cvmx_usbnx_dma0_outb_chn6_s cn52xxp1;
775 struct cvmx_usbnx_dma0_outb_chn6_s cn56xx;
776 struct cvmx_usbnx_dma0_outb_chn6_s cn56xxp1;
778 typedef union cvmx_usbnx_dma0_outb_chn6 cvmx_usbnx_dma0_outb_chn6_t;
781 * cvmx_usbn#_dma0_outb_chn7
783 * USBN_DMA0_OUTB_CHN7 = USBN's Outbound DMA for USB0 Channel7
785 * Contains the starting address for use when USB0 reads from L2C via Channel7.
786 * Writing of this register sets the base address.
788 union cvmx_usbnx_dma0_outb_chn7
791 struct cvmx_usbnx_dma0_outb_chn7_s
793 uint64_t reserved_36_63 : 28;
794 uint64_t addr : 36; /**< Base address for DMA Read from L2C. */
796 struct cvmx_usbnx_dma0_outb_chn7_s cn30xx;
797 struct cvmx_usbnx_dma0_outb_chn7_s cn31xx;
798 struct cvmx_usbnx_dma0_outb_chn7_s cn50xx;
799 struct cvmx_usbnx_dma0_outb_chn7_s cn52xx;
800 struct cvmx_usbnx_dma0_outb_chn7_s cn52xxp1;
801 struct cvmx_usbnx_dma0_outb_chn7_s cn56xx;
802 struct cvmx_usbnx_dma0_outb_chn7_s cn56xxp1;
804 typedef union cvmx_usbnx_dma0_outb_chn7 cvmx_usbnx_dma0_outb_chn7_t;
807 * cvmx_usbn#_dma_test
809 * USBN_DMA_TEST = USBN's DMA TestRegister
811 * This register can cause the external DMA engine to the USB-Core to make transfers from/to L2C/USB-FIFOs
813 union cvmx_usbnx_dma_test
816 struct cvmx_usbnx_dma_test_s
818 uint64_t reserved_40_63 : 24;
819 uint64_t done : 1; /**< This field is set when a DMA completes. Writing a
820 '1' to this field clears this bit. */
821 uint64_t req : 1; /**< DMA Request. Writing a 1 to this register
822 will cause a DMA request as specified in the other
823 fields of this register to take place. This field
824 will always read as '0'. */
825 uint64_t f_addr : 18; /**< The address to read from in the Data-Fifo. */
826 uint64_t count : 11; /**< DMA Request Count. */
827 uint64_t channel : 5; /**< DMA Channel/Enpoint. */
828 uint64_t burst : 4; /**< DMA Burst Size. */
830 struct cvmx_usbnx_dma_test_s cn30xx;
831 struct cvmx_usbnx_dma_test_s cn31xx;
832 struct cvmx_usbnx_dma_test_s cn50xx;
833 struct cvmx_usbnx_dma_test_s cn52xx;
834 struct cvmx_usbnx_dma_test_s cn52xxp1;
835 struct cvmx_usbnx_dma_test_s cn56xx;
836 struct cvmx_usbnx_dma_test_s cn56xxp1;
838 typedef union cvmx_usbnx_dma_test cvmx_usbnx_dma_test_t;
843 * USBN_INT_ENB = USBN's Interrupt Enable
845 * The USBN's interrupt enable register.
847 union cvmx_usbnx_int_enb
850 struct cvmx_usbnx_int_enb_s
852 uint64_t reserved_38_63 : 26;
853 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
854 register is asserted the USBN will assert an
856 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
857 register is asserted the USBN will assert an
859 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
860 register is asserted the USBN will assert an
862 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
863 register is asserted the USBN will assert an
865 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
866 register is asserted the USBN will assert an
868 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
869 register is asserted the USBN will assert an
871 uint64_t u2n_c_pe : 1; /**< When set (1) and bit 31 of the USBN_INT_SUM
872 register is asserted the USBN will assert an
874 uint64_t u2n_c_pf : 1; /**< When set (1) and bit 30 of the USBN_INT_SUM
875 register is asserted the USBN will assert an
877 uint64_t u2n_d_pf : 1; /**< When set (1) and bit 29 of the USBN_INT_SUM
878 register is asserted the USBN will assert an
880 uint64_t u2n_d_pe : 1; /**< When set (1) and bit 28 of the USBN_INT_SUM
881 register is asserted the USBN will assert an
883 uint64_t n2u_pe : 1; /**< When set (1) and bit 27 of the USBN_INT_SUM
884 register is asserted the USBN will assert an
886 uint64_t n2u_pf : 1; /**< When set (1) and bit 26 of the USBN_INT_SUM
887 register is asserted the USBN will assert an
889 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
890 register is asserted the USBN will assert an
892 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
893 register is asserted the USBN will assert an
895 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
896 register is asserted the USBN will assert an
898 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
899 register is asserted the USBN will assert an
901 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
902 register is asserted the USBN will assert an
904 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
905 register is asserted the USBN will assert an
907 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
908 register is asserted the USBN will assert an
910 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
911 register is asserted the USBN will assert an
913 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
914 register is asserted the USBN will assert an
916 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
917 register is asserted the USBN will assert an
919 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
920 register is asserted the USBN will assert an
922 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
923 register is asserted the USBN will assert an
925 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
926 register is asserted the USBN will assert an
928 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
929 register is asserted the USBN will assert an
931 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
932 register is asserted the USBN will assert an
934 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
935 register is asserted the USBN will assert an
937 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
938 register is asserted the USBN will assert an
940 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
941 register is asserted the USBN will assert an
943 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
944 register is asserted the USBN will assert an
946 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
947 register is asserted the USBN will assert an
949 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
950 register is asserted the USBN will assert an
952 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
953 register is asserted the USBN will assert an
955 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
956 register is asserted the USBN will assert an
958 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
959 register is asserted the USBN will assert an
961 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
962 register is asserted the USBN will assert an
964 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
965 register is asserted the USBN will assert an
968 struct cvmx_usbnx_int_enb_s cn30xx;
969 struct cvmx_usbnx_int_enb_s cn31xx;
970 struct cvmx_usbnx_int_enb_cn50xx
972 uint64_t reserved_38_63 : 26;
973 uint64_t nd4o_dpf : 1; /**< When set (1) and bit 37 of the USBN_INT_SUM
974 register is asserted the USBN will assert an
976 uint64_t nd4o_dpe : 1; /**< When set (1) and bit 36 of the USBN_INT_SUM
977 register is asserted the USBN will assert an
979 uint64_t nd4o_rpf : 1; /**< When set (1) and bit 35 of the USBN_INT_SUM
980 register is asserted the USBN will assert an
982 uint64_t nd4o_rpe : 1; /**< When set (1) and bit 34 of the USBN_INT_SUM
983 register is asserted the USBN will assert an
985 uint64_t ltl_f_pf : 1; /**< When set (1) and bit 33 of the USBN_INT_SUM
986 register is asserted the USBN will assert an
988 uint64_t ltl_f_pe : 1; /**< When set (1) and bit 32 of the USBN_INT_SUM
989 register is asserted the USBN will assert an
991 uint64_t reserved_26_31 : 6;
992 uint64_t uod_pf : 1; /**< When set (1) and bit 25 of the USBN_INT_SUM
993 register is asserted the USBN will assert an
995 uint64_t uod_pe : 1; /**< When set (1) and bit 24 of the USBN_INT_SUM
996 register is asserted the USBN will assert an
998 uint64_t rq_q3_e : 1; /**< When set (1) and bit 23 of the USBN_INT_SUM
999 register is asserted the USBN will assert an
1001 uint64_t rq_q3_f : 1; /**< When set (1) and bit 22 of the USBN_INT_SUM
1002 register is asserted the USBN will assert an
1004 uint64_t rq_q2_e : 1; /**< When set (1) and bit 21 of the USBN_INT_SUM
1005 register is asserted the USBN will assert an
1007 uint64_t rq_q2_f : 1; /**< When set (1) and bit 20 of the USBN_INT_SUM
1008 register is asserted the USBN will assert an
1010 uint64_t rg_fi_f : 1; /**< When set (1) and bit 19 of the USBN_INT_SUM
1011 register is asserted the USBN will assert an
1013 uint64_t rg_fi_e : 1; /**< When set (1) and bit 18 of the USBN_INT_SUM
1014 register is asserted the USBN will assert an
1016 uint64_t l2_fi_f : 1; /**< When set (1) and bit 17 of the USBN_INT_SUM
1017 register is asserted the USBN will assert an
1019 uint64_t l2_fi_e : 1; /**< When set (1) and bit 16 of the USBN_INT_SUM
1020 register is asserted the USBN will assert an
1022 uint64_t l2c_a_f : 1; /**< When set (1) and bit 15 of the USBN_INT_SUM
1023 register is asserted the USBN will assert an
1025 uint64_t l2c_s_e : 1; /**< When set (1) and bit 14 of the USBN_INT_SUM
1026 register is asserted the USBN will assert an
1028 uint64_t dcred_f : 1; /**< When set (1) and bit 13 of the USBN_INT_SUM
1029 register is asserted the USBN will assert an
1031 uint64_t dcred_e : 1; /**< When set (1) and bit 12 of the USBN_INT_SUM
1032 register is asserted the USBN will assert an
1034 uint64_t lt_pu_f : 1; /**< When set (1) and bit 11 of the USBN_INT_SUM
1035 register is asserted the USBN will assert an
1037 uint64_t lt_po_e : 1; /**< When set (1) and bit 10 of the USBN_INT_SUM
1038 register is asserted the USBN will assert an
1040 uint64_t nt_pu_f : 1; /**< When set (1) and bit 9 of the USBN_INT_SUM
1041 register is asserted the USBN will assert an
1043 uint64_t nt_po_e : 1; /**< When set (1) and bit 8 of the USBN_INT_SUM
1044 register is asserted the USBN will assert an
1046 uint64_t pt_pu_f : 1; /**< When set (1) and bit 7 of the USBN_INT_SUM
1047 register is asserted the USBN will assert an
1049 uint64_t pt_po_e : 1; /**< When set (1) and bit 6 of the USBN_INT_SUM
1050 register is asserted the USBN will assert an
1052 uint64_t lr_pu_f : 1; /**< When set (1) and bit 5 of the USBN_INT_SUM
1053 register is asserted the USBN will assert an
1055 uint64_t lr_po_e : 1; /**< When set (1) and bit 4 of the USBN_INT_SUM
1056 register is asserted the USBN will assert an
1058 uint64_t nr_pu_f : 1; /**< When set (1) and bit 3 of the USBN_INT_SUM
1059 register is asserted the USBN will assert an
1061 uint64_t nr_po_e : 1; /**< When set (1) and bit 2 of the USBN_INT_SUM
1062 register is asserted the USBN will assert an
1064 uint64_t pr_pu_f : 1; /**< When set (1) and bit 1 of the USBN_INT_SUM
1065 register is asserted the USBN will assert an
1067 uint64_t pr_po_e : 1; /**< When set (1) and bit 0 of the USBN_INT_SUM
1068 register is asserted the USBN will assert an
1071 struct cvmx_usbnx_int_enb_cn50xx cn52xx;
1072 struct cvmx_usbnx_int_enb_cn50xx cn52xxp1;
1073 struct cvmx_usbnx_int_enb_cn50xx cn56xx;
1074 struct cvmx_usbnx_int_enb_cn50xx cn56xxp1;
1076 typedef union cvmx_usbnx_int_enb cvmx_usbnx_int_enb_t;
1079 * cvmx_usbn#_int_sum
1081 * USBN_INT_SUM = USBN's Interrupt Summary Register
1083 * Contains the diffrent interrupt summary bits of the USBN.
1085 union cvmx_usbnx_int_sum
1088 struct cvmx_usbnx_int_sum_s
1090 uint64_t reserved_38_63 : 26;
1091 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1092 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1093 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1094 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1095 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1096 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1097 uint64_t u2n_c_pe : 1; /**< U2N Control Fifo Pop Empty. */
1098 uint64_t u2n_c_pf : 1; /**< U2N Control Fifo Push Full. */
1099 uint64_t u2n_d_pf : 1; /**< U2N Data Fifo Push Full. */
1100 uint64_t u2n_d_pe : 1; /**< U2N Data Fifo Pop Empty. */
1101 uint64_t n2u_pe : 1; /**< N2U Fifo Pop Empty. */
1102 uint64_t n2u_pf : 1; /**< N2U Fifo Push Full. */
1103 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1104 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1105 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1106 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1107 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1108 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1109 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1110 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1111 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1112 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1113 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1114 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1115 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1116 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1117 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1118 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1119 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1120 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1121 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1122 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1123 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1124 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1125 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1126 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1127 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1128 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1130 struct cvmx_usbnx_int_sum_s cn30xx;
1131 struct cvmx_usbnx_int_sum_s cn31xx;
1132 struct cvmx_usbnx_int_sum_cn50xx
1134 uint64_t reserved_38_63 : 26;
1135 uint64_t nd4o_dpf : 1; /**< NCB DMA Out Data Fifo Push Full. */
1136 uint64_t nd4o_dpe : 1; /**< NCB DMA Out Data Fifo Pop Empty. */
1137 uint64_t nd4o_rpf : 1; /**< NCB DMA Out Request Fifo Push Full. */
1138 uint64_t nd4o_rpe : 1; /**< NCB DMA Out Request Fifo Pop Empty. */
1139 uint64_t ltl_f_pf : 1; /**< L2C Transfer Length Fifo Push Full. */
1140 uint64_t ltl_f_pe : 1; /**< L2C Transfer Length Fifo Pop Empty. */
1141 uint64_t reserved_26_31 : 6;
1142 uint64_t uod_pf : 1; /**< UOD Fifo Push Full. */
1143 uint64_t uod_pe : 1; /**< UOD Fifo Pop Empty. */
1144 uint64_t rq_q3_e : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1145 uint64_t rq_q3_f : 1; /**< Request Queue-3 Fifo Pushed When Full. */
1146 uint64_t rq_q2_e : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1147 uint64_t rq_q2_f : 1; /**< Request Queue-2 Fifo Pushed When Full. */
1148 uint64_t rg_fi_f : 1; /**< Register Request Fifo Pushed When Full. */
1149 uint64_t rg_fi_e : 1; /**< Register Request Fifo Pushed When Full. */
1150 uint64_t lt_fi_f : 1; /**< L2C Request Fifo Pushed When Full. */
1151 uint64_t lt_fi_e : 1; /**< L2C Request Fifo Pushed When Full. */
1152 uint64_t l2c_a_f : 1; /**< L2C Credit Count Added When Full. */
1153 uint64_t l2c_s_e : 1; /**< L2C Credit Count Subtracted When Empty. */
1154 uint64_t dcred_f : 1; /**< Data CreditFifo Pushed When Full. */
1155 uint64_t dcred_e : 1; /**< Data Credit Fifo Pushed When Full. */
1156 uint64_t lt_pu_f : 1; /**< L2C Trasaction Fifo Pushed When Full. */
1157 uint64_t lt_po_e : 1; /**< L2C Trasaction Fifo Popped When Full. */
1158 uint64_t nt_pu_f : 1; /**< NPI Trasaction Fifo Pushed When Full. */
1159 uint64_t nt_po_e : 1; /**< NPI Trasaction Fifo Popped When Full. */
1160 uint64_t pt_pu_f : 1; /**< PP Trasaction Fifo Pushed When Full. */
1161 uint64_t pt_po_e : 1; /**< PP Trasaction Fifo Popped When Full. */
1162 uint64_t lr_pu_f : 1; /**< L2C Request Fifo Pushed When Full. */
1163 uint64_t lr_po_e : 1; /**< L2C Request Fifo Popped When Empty. */
1164 uint64_t nr_pu_f : 1; /**< NPI Request Fifo Pushed When Full. */
1165 uint64_t nr_po_e : 1; /**< NPI Request Fifo Popped When Empty. */
1166 uint64_t pr_pu_f : 1; /**< PP Request Fifo Pushed When Full. */
1167 uint64_t pr_po_e : 1; /**< PP Request Fifo Popped When Empty. */
1169 struct cvmx_usbnx_int_sum_cn50xx cn52xx;
1170 struct cvmx_usbnx_int_sum_cn50xx cn52xxp1;
1171 struct cvmx_usbnx_int_sum_cn50xx cn56xx;
1172 struct cvmx_usbnx_int_sum_cn50xx cn56xxp1;
1174 typedef union cvmx_usbnx_int_sum cvmx_usbnx_int_sum_t;
1177 * cvmx_usbn#_usbp_ctl_status
1179 * USBN_USBP_CTL_STATUS = USBP Control And Status Register
1181 * Contains general control and status information for the USBN block.
1183 union cvmx_usbnx_usbp_ctl_status
1186 struct cvmx_usbnx_usbp_ctl_status_s
1188 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
1189 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
1190 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
1191 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
1192 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
1193 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
1194 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
1195 uint64_t otgdisable : 1; /**< OTG Block Disable */
1196 uint64_t portreset : 1; /**< Per_Port Reset */
1197 uint64_t drvvbus : 1; /**< Drive VBUS */
1198 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
1199 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
1200 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
1201 uint64_t bist_done : 1; /**< PHY Bist Done.
1202 Asserted at the end of the PHY BIST sequence. */
1203 uint64_t bist_err : 1; /**< PHY Bist Error.
1204 Indicates an internal error was detected during
1205 the BIST sequence. */
1206 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1207 Presents either internaly generated signals or
1208 test register contents, based upon the value of
1209 test_data_out_sel. */
1210 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
1211 Normally should be set to zero.
1212 When customers have no intent to use USB PHY
1213 interface, they should:
1214 - still provide 3.3V to USB_VDD33, and
1215 - tie USB_REXT to 3.3V supply, and
1216 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
1217 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
1218 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1219 with byte-counts between packets. When set to 0
1220 the L2C DMA address is incremented to the next
1221 4-byte aligned address after adding byte-count. */
1222 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1223 set to '0' for operation. */
1224 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1225 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1226 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1227 This signal enables the pull-down resistance on
1228 the D+ line. '1' pull down-resistance is connected
1229 to D+/ '0' pull down resistance is not connected
1230 to D+. When an A/B device is acting as a host
1231 (downstream-facing port), dp_pulldown and
1232 dm_pulldown are enabled. This must not toggle
1233 during normal opeartion. */
1234 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1235 This signal enables the pull-down resistance on
1236 the D- line. '1' pull down-resistance is connected
1237 to D-. '0' pull down resistance is not connected
1238 to D-. When an A/B device is acting as a host
1239 (downstream-facing port), dp_pulldown and
1240 dm_pulldown are enabled. This must not toggle
1241 during normal opeartion. */
1242 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1243 USB is acting as device. This field needs to be
1244 set while the USB is in reset. */
1245 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
1246 Tunes the current supply and rise/fall output
1247 times for high-speed operation.
1248 [20:19] == 11: Current supply increased
1250 [20:19] == 10: Current supply increased
1252 [20:19] == 01: Design default.
1253 [20:19] == 00: Current supply decreased
1255 [22:21] == 11: Rise and fall times are increased.
1256 [22:21] == 10: Design default.
1257 [22:21] == 01: Rise and fall times are decreased.
1258 [22:21] == 00: Rise and fall times are decreased
1259 further as compared to the 01 setting. */
1260 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1261 Enables or disables bit stuffing on data[15:8]
1262 when bit-stuffing is enabled. */
1263 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1264 Enables or disables bit stuffing on data[7:0]
1265 when bit-stuffing is enabled. */
1266 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1267 '1': During data transmission the receive is
1269 '0': During data transmission the receive is
1271 Must be '0' for normal operation. */
1272 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1273 '1' The PHY's analog_test pin is enabled for the
1274 input and output of applicable analog test signals.
1275 '0' THe analog_test pin is disabled. */
1276 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1277 Used to activate BIST in the PHY. */
1278 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1279 '1' test_data_out[3:0] (PHY) register contents
1280 are output. '0' internaly generated signals are
1282 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1283 Specifies the register address for writing to or
1284 reading from the PHY test interface register. */
1285 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1286 This is a test bus. Data is present on [3:0],
1287 and its corresponding select (enable) is present
1289 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1290 This is a test signal. When the USB Core is
1291 powered up (not in Susned Mode), an automatic
1292 tester can use this to disable phy_clock and
1293 free_clk, then re-eanable them with an aligned
1295 '1': The phy_clk and free_clk outputs are
1296 disabled. "0": The phy_clock and free_clk outputs
1297 are available within a specific period after the
1300 struct cvmx_usbnx_usbp_ctl_status_cn30xx
1302 uint64_t reserved_38_63 : 26;
1303 uint64_t bist_done : 1; /**< PHY Bist Done.
1304 Asserted at the end of the PHY BIST sequence. */
1305 uint64_t bist_err : 1; /**< PHY Bist Error.
1306 Indicates an internal error was detected during
1307 the BIST sequence. */
1308 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1309 Presents either internaly generated signals or
1310 test register contents, based upon the value of
1311 test_data_out_sel. */
1312 uint64_t reserved_30_31 : 2;
1313 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1314 with byte-counts between packets. When set to 0
1315 the L2C DMA address is incremented to the next
1316 4-byte aligned address after adding byte-count. */
1317 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1318 set to '0' for operation. */
1319 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1320 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1321 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1322 This signal enables the pull-down resistance on
1323 the D+ line. '1' pull down-resistance is connected
1324 to D+/ '0' pull down resistance is not connected
1325 to D+. When an A/B device is acting as a host
1326 (downstream-facing port), dp_pulldown and
1327 dm_pulldown are enabled. This must not toggle
1328 during normal opeartion. */
1329 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1330 This signal enables the pull-down resistance on
1331 the D- line. '1' pull down-resistance is connected
1332 to D-. '0' pull down resistance is not connected
1333 to D-. When an A/B device is acting as a host
1334 (downstream-facing port), dp_pulldown and
1335 dm_pulldown are enabled. This must not toggle
1336 during normal opeartion. */
1337 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1338 USB is acting as device. This field needs to be
1339 set while the USB is in reset. */
1340 uint64_t tuning : 4; /**< Transmitter Tuning for High-Speed Operation.
1341 Tunes the current supply and rise/fall output
1342 times for high-speed operation.
1343 [20:19] == 11: Current supply increased
1345 [20:19] == 10: Current supply increased
1347 [20:19] == 01: Design default.
1348 [20:19] == 00: Current supply decreased
1350 [22:21] == 11: Rise and fall times are increased.
1351 [22:21] == 10: Design default.
1352 [22:21] == 01: Rise and fall times are decreased.
1353 [22:21] == 00: Rise and fall times are decreased
1354 further as compared to the 01 setting. */
1355 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1356 Enables or disables bit stuffing on data[15:8]
1357 when bit-stuffing is enabled. */
1358 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1359 Enables or disables bit stuffing on data[7:0]
1360 when bit-stuffing is enabled. */
1361 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1362 '1': During data transmission the receive is
1364 '0': During data transmission the receive is
1366 Must be '0' for normal operation. */
1367 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1368 '1' The PHY's analog_test pin is enabled for the
1369 input and output of applicable analog test signals.
1370 '0' THe analog_test pin is disabled. */
1371 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1372 Used to activate BIST in the PHY. */
1373 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1374 '1' test_data_out[3:0] (PHY) register contents
1375 are output. '0' internaly generated signals are
1377 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1378 Specifies the register address for writing to or
1379 reading from the PHY test interface register. */
1380 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1381 This is a test bus. Data is present on [3:0],
1382 and its corresponding select (enable) is present
1384 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1385 This is a test signal. When the USB Core is
1386 powered up (not in Susned Mode), an automatic
1387 tester can use this to disable phy_clock and
1388 free_clk, then re-eanable them with an aligned
1390 '1': The phy_clk and free_clk outputs are
1391 disabled. "0": The phy_clock and free_clk outputs
1392 are available within a specific period after the
1395 struct cvmx_usbnx_usbp_ctl_status_cn30xx cn31xx;
1396 struct cvmx_usbnx_usbp_ctl_status_cn50xx
1398 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
1399 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
1400 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
1401 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
1402 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
1403 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
1404 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
1405 uint64_t otgdisable : 1; /**< OTG Block Disable */
1406 uint64_t portreset : 1; /**< Per_Port Reset */
1407 uint64_t drvvbus : 1; /**< Drive VBUS */
1408 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
1409 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
1410 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
1411 uint64_t bist_done : 1; /**< PHY Bist Done.
1412 Asserted at the end of the PHY BIST sequence. */
1413 uint64_t bist_err : 1; /**< PHY Bist Error.
1414 Indicates an internal error was detected during
1415 the BIST sequence. */
1416 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1417 Presents either internaly generated signals or
1418 test register contents, based upon the value of
1419 test_data_out_sel. */
1420 uint64_t reserved_31_31 : 1;
1421 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
1422 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1423 with byte-counts between packets. When set to 0
1424 the L2C DMA address is incremented to the next
1425 4-byte aligned address after adding byte-count. */
1426 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1427 set to '0' for operation. */
1428 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1429 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1430 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1431 This signal enables the pull-down resistance on
1432 the D+ line. '1' pull down-resistance is connected
1433 to D+/ '0' pull down resistance is not connected
1434 to D+. When an A/B device is acting as a host
1435 (downstream-facing port), dp_pulldown and
1436 dm_pulldown are enabled. This must not toggle
1437 during normal opeartion. */
1438 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1439 This signal enables the pull-down resistance on
1440 the D- line. '1' pull down-resistance is connected
1441 to D-. '0' pull down resistance is not connected
1442 to D-. When an A/B device is acting as a host
1443 (downstream-facing port), dp_pulldown and
1444 dm_pulldown are enabled. This must not toggle
1445 during normal opeartion. */
1446 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1447 USB is acting as device. This field needs to be
1448 set while the USB is in reset. */
1449 uint64_t reserved_19_22 : 4;
1450 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1451 Enables or disables bit stuffing on data[15:8]
1452 when bit-stuffing is enabled. */
1453 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1454 Enables or disables bit stuffing on data[7:0]
1455 when bit-stuffing is enabled. */
1456 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1457 '1': During data transmission the receive is
1459 '0': During data transmission the receive is
1461 Must be '0' for normal operation. */
1462 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1463 '1' The PHY's analog_test pin is enabled for the
1464 input and output of applicable analog test signals.
1465 '0' THe analog_test pin is disabled. */
1466 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1467 Used to activate BIST in the PHY. */
1468 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1469 '1' test_data_out[3:0] (PHY) register contents
1470 are output. '0' internaly generated signals are
1472 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1473 Specifies the register address for writing to or
1474 reading from the PHY test interface register. */
1475 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1476 This is a test bus. Data is present on [3:0],
1477 and its corresponding select (enable) is present
1479 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1480 This is a test signal. When the USB Core is
1481 powered up (not in Susned Mode), an automatic
1482 tester can use this to disable phy_clock and
1483 free_clk, then re-eanable them with an aligned
1485 '1': The phy_clk and free_clk outputs are
1486 disabled. "0": The phy_clock and free_clk outputs
1487 are available within a specific period after the
1490 struct cvmx_usbnx_usbp_ctl_status_cn52xx
1492 uint64_t txrisetune : 1; /**< HS Transmitter Rise/Fall Time Adjustment */
1493 uint64_t txvreftune : 4; /**< HS DC Voltage Level Adjustment */
1494 uint64_t txfslstune : 4; /**< FS/LS Source Impedence Adjustment */
1495 uint64_t txhsxvtune : 2; /**< Transmitter High-Speed Crossover Adjustment */
1496 uint64_t sqrxtune : 3; /**< Squelch Threshold Adjustment */
1497 uint64_t compdistune : 3; /**< Disconnect Threshold Adjustment */
1498 uint64_t otgtune : 3; /**< VBUS Valid Threshold Adjustment */
1499 uint64_t otgdisable : 1; /**< OTG Block Disable */
1500 uint64_t portreset : 1; /**< Per_Port Reset */
1501 uint64_t drvvbus : 1; /**< Drive VBUS */
1502 uint64_t lsbist : 1; /**< Low-Speed BIST Enable. */
1503 uint64_t fsbist : 1; /**< Full-Speed BIST Enable. */
1504 uint64_t hsbist : 1; /**< High-Speed BIST Enable. */
1505 uint64_t bist_done : 1; /**< PHY Bist Done.
1506 Asserted at the end of the PHY BIST sequence. */
1507 uint64_t bist_err : 1; /**< PHY Bist Error.
1508 Indicates an internal error was detected during
1509 the BIST sequence. */
1510 uint64_t tdata_out : 4; /**< PHY Test Data Out.
1511 Presents either internaly generated signals or
1512 test register contents, based upon the value of
1513 test_data_out_sel. */
1514 uint64_t siddq : 1; /**< Drives the USBP (USB-PHY) SIDDQ input.
1515 Normally should be set to zero.
1516 When customers have no intent to use USB PHY
1517 interface, they should:
1518 - still provide 3.3V to USB_VDD33, and
1519 - tie USB_REXT to 3.3V supply, and
1520 - set USBN*_USBP_CTL_STATUS[SIDDQ]=1 */
1521 uint64_t txpreemphasistune : 1; /**< HS Transmitter Pre-Emphasis Enable */
1522 uint64_t dma_bmode : 1; /**< When set to 1 the L2C DMA address will be updated
1523 with byte-counts between packets. When set to 0
1524 the L2C DMA address is incremented to the next
1525 4-byte aligned address after adding byte-count. */
1526 uint64_t usbc_end : 1; /**< Bigendian input to the USB Core. This should be
1527 set to '0' for operation. */
1528 uint64_t usbp_bist : 1; /**< PHY, This is cleared '0' to run BIST on the USBP. */
1529 uint64_t tclk : 1; /**< PHY Test Clock, used to load TDATA_IN to the USBP. */
1530 uint64_t dp_pulld : 1; /**< PHY DP_PULLDOWN input to the USB-PHY.
1531 This signal enables the pull-down resistance on
1532 the D+ line. '1' pull down-resistance is connected
1533 to D+/ '0' pull down resistance is not connected
1534 to D+. When an A/B device is acting as a host
1535 (downstream-facing port), dp_pulldown and
1536 dm_pulldown are enabled. This must not toggle
1537 during normal opeartion. */
1538 uint64_t dm_pulld : 1; /**< PHY DM_PULLDOWN input to the USB-PHY.
1539 This signal enables the pull-down resistance on
1540 the D- line. '1' pull down-resistance is connected
1541 to D-. '0' pull down resistance is not connected
1542 to D-. When an A/B device is acting as a host
1543 (downstream-facing port), dp_pulldown and
1544 dm_pulldown are enabled. This must not toggle
1545 during normal opeartion. */
1546 uint64_t hst_mode : 1; /**< When '0' the USB is acting as HOST, when '1'
1547 USB is acting as device. This field needs to be
1548 set while the USB is in reset. */
1549 uint64_t reserved_19_22 : 4;
1550 uint64_t tx_bs_enh : 1; /**< Transmit Bit Stuffing on [15:8].
1551 Enables or disables bit stuffing on data[15:8]
1552 when bit-stuffing is enabled. */
1553 uint64_t tx_bs_en : 1; /**< Transmit Bit Stuffing on [7:0].
1554 Enables or disables bit stuffing on data[7:0]
1555 when bit-stuffing is enabled. */
1556 uint64_t loop_enb : 1; /**< PHY Loopback Test Enable.
1557 '1': During data transmission the receive is
1559 '0': During data transmission the receive is
1561 Must be '0' for normal operation. */
1562 uint64_t vtest_enb : 1; /**< Analog Test Pin Enable.
1563 '1' The PHY's analog_test pin is enabled for the
1564 input and output of applicable analog test signals.
1565 '0' THe analog_test pin is disabled. */
1566 uint64_t bist_enb : 1; /**< Built-In Self Test Enable.
1567 Used to activate BIST in the PHY. */
1568 uint64_t tdata_sel : 1; /**< Test Data Out Select.
1569 '1' test_data_out[3:0] (PHY) register contents
1570 are output. '0' internaly generated signals are
1572 uint64_t taddr_in : 4; /**< Mode Address for Test Interface.
1573 Specifies the register address for writing to or
1574 reading from the PHY test interface register. */
1575 uint64_t tdata_in : 8; /**< Internal Testing Register Input Data and Select
1576 This is a test bus. Data is present on [3:0],
1577 and its corresponding select (enable) is present
1579 uint64_t ate_reset : 1; /**< Reset input from automatic test equipment.
1580 This is a test signal. When the USB Core is
1581 powered up (not in Susned Mode), an automatic
1582 tester can use this to disable phy_clock and
1583 free_clk, then re-eanable them with an aligned
1585 '1': The phy_clk and free_clk outputs are
1586 disabled. "0": The phy_clock and free_clk outputs
1587 are available within a specific period after the
1590 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn52xxp1;
1591 struct cvmx_usbnx_usbp_ctl_status_cn52xx cn56xx;
1592 struct cvmx_usbnx_usbp_ctl_status_cn50xx cn56xxp1;
1594 typedef union cvmx_usbnx_usbp_ctl_status cvmx_usbnx_usbp_ctl_status_t;
projects / linux-imx.git / blob