drivers/gpu/drm/radeon/si_dpm.c

   1 /*
   2  * Copyright 2013 Advanced Micro Devices, Inc.
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice shall be included in
  12  * all copies or substantial portions of the Software.
  13  *
  14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20  * OTHER DEALINGS IN THE SOFTWARE.
  21  *
  22  */
  23
  24 #include "drmP.h"
  25 #include "radeon.h"
  26 #include "sid.h"
  27 #include "r600_dpm.h"
  28 #include "si_dpm.h"
  29 #include "atom.h"
  30 #include <linux/math64.h>
  31 #include <linux/seq_file.h>
  32
  33 #define MC_CG_ARB_FREQ_F0           0x0a
  34 #define MC_CG_ARB_FREQ_F1           0x0b
  35 #define MC_CG_ARB_FREQ_F2           0x0c
  36 #define MC_CG_ARB_FREQ_F3           0x0d
  37
  38 #define SMC_RAM_END                 0x20000
  39
  40 #define DDR3_DRAM_ROWS              0x2000
  41
  42 #define SCLK_MIN_DEEPSLEEP_FREQ     1350
  43
  44 static const struct si_cac_config_reg cac_weights_tahiti[] =
  45 {
  46         { 0x0, 0x0000ffff, 0, 0xc, SISLANDS_CACCONFIG_CGIND },
  47         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  48         { 0x1, 0x0000ffff, 0, 0x101, SISLANDS_CACCONFIG_CGIND },
  49         { 0x1, 0xffff0000, 16, 0xc, SISLANDS_CACCONFIG_CGIND },
  50         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  51         { 0x3, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  52         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  53         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  54         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  55         { 0x5, 0x0000ffff, 0, 0x8fc, SISLANDS_CACCONFIG_CGIND },
  56         { 0x5, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  57         { 0x6, 0x0000ffff, 0, 0x95, SISLANDS_CACCONFIG_CGIND },
  58         { 0x6, 0xffff0000, 16, 0x34e, SISLANDS_CACCONFIG_CGIND },
  59         { 0x18f, 0x0000ffff, 0, 0x1a1, SISLANDS_CACCONFIG_CGIND },
  60         { 0x7, 0x0000ffff, 0, 0xda, SISLANDS_CACCONFIG_CGIND },
  61         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  62         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  63         { 0x8, 0xffff0000, 16, 0x46, SISLANDS_CACCONFIG_CGIND },
  64         { 0x9, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  65         { 0xa, 0x0000ffff, 0, 0x208, SISLANDS_CACCONFIG_CGIND },
  66         { 0xb, 0x0000ffff, 0, 0xe7, SISLANDS_CACCONFIG_CGIND },
  67         { 0xb, 0xffff0000, 16, 0x948, SISLANDS_CACCONFIG_CGIND },
  68         { 0xc, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  69         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  70         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  71         { 0xe, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  72         { 0xf, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  73         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  74         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  75         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  76         { 0x11, 0x0000ffff, 0, 0x167, SISLANDS_CACCONFIG_CGIND },
  77         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  78         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  79         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  80         { 0x13, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
  81         { 0x14, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  82         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  83         { 0x15, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
  84         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  85         { 0x16, 0x0000ffff, 0, 0x31, SISLANDS_CACCONFIG_CGIND },
  86         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  87         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  88         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  89         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  90         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  91         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  92         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  93         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  94         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  95         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  96         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  97         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
  98         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
  99         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 100         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 101         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 102         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 103         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 104         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 105         { 0x6d, 0x0000ffff, 0, 0x18e, SISLANDS_CACCONFIG_CGIND },
 106         { 0xFFFFFFFF }
 107 };
 108
 109 static const struct si_cac_config_reg lcac_tahiti[] =
 110 {
 111         { 0x143, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 112         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 113         { 0x146, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 114         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 115         { 0x149, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 116         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 117         { 0x14c, 0x0001fffe, 1, 0x3, SISLANDS_CACCONFIG_CGIND },
 118         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 119         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 120         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 121         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 122         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 123         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 124         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 125         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 126         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 127         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 128         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 129         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 130         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 131         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 132         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 133         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 134         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 135         { 0x8c, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 136         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 137         { 0x8f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 138         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 139         { 0x92, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 140         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 141         { 0x95, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 142         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 143         { 0x14f, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 144         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 145         { 0x152, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 146         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 147         { 0x155, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 148         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 149         { 0x158, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 150         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 151         { 0x110, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 152         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 153         { 0x113, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 154         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 155         { 0x116, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 156         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 157         { 0x119, 0x0001fffe, 1, 0x8, SISLANDS_CACCONFIG_CGIND },
 158         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 159         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 160         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 161         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 162         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 163         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 164         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 165         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 166         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 167         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 168         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 169         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 170         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 171         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 172         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 173         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 174         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 175         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 176         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 177         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 178         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 179         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 180         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 181         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 182         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 183         { 0x16d, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
 184         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 185         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 186         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 187         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 188         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 189         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 190         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 191         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 192         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 193         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 194         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 195         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 196         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 197         { 0xFFFFFFFF }
 198
 199 };
 200
 201 static const struct si_cac_config_reg cac_override_tahiti[] =
 202 {
 203         { 0xFFFFFFFF }
 204 };
 205
 206 static const struct si_powertune_data powertune_data_tahiti =
 207 {
 208         ((1 << 16) | 27027),
 209         6,
 210         0,
 211         4,
 212         95,
 213         {
 214                 0UL,
 215                 0UL,
 216                 4521550UL,
 217                 309631529UL,
 218                 -1270850L,
 219                 4513710L,
 220                 40
 221         },
 222         595000000UL,
 223         12,
 224         {
 225                 0,
 226                 0,
 227                 0,
 228                 0,
 229                 0,
 230                 0,
 231                 0,
 232                 0
 233         },
 234         true
 235 };
 236
 237 static const struct si_dte_data dte_data_tahiti =
 238 {
 239         { 1159409, 0, 0, 0, 0 },
 240         { 777, 0, 0, 0, 0 },
 241         2,
 242         54000,
 243         127000,
 244         25,
 245         2,
 246         10,
 247         13,
 248         { 27, 31, 35, 39, 43, 47, 54, 61, 67, 74, 81, 88, 95, 0, 0, 0 },
 249         { 240888759, 221057860, 235370597, 162287531, 158510299, 131423027, 116673180, 103067515, 87941937, 76209048, 68209175, 64090048, 58301890, 0, 0, 0 },
 250         { 12024, 11189, 11451, 8411, 7939, 6666, 5681, 4905, 4241, 3720, 3354, 3122, 2890, 0, 0, 0 },
 251         85,
 252         false
 253 };
 254
 255 static const struct si_dte_data dte_data_tahiti_le =
 256 {
 257         { 0x1E8480, 0x7A1200, 0x2160EC0, 0x3938700, 0 },
 258         { 0x7D, 0x7D, 0x4E4, 0xB00, 0 },
 259         0x5,
 260         0xAFC8,
 261         0x64,
 262         0x32,
 263         1,
 264         0,
 265         0x10,
 266         { 0x78, 0x7C, 0x82, 0x88, 0x8E, 0x94, 0x9A, 0xA0, 0xA6, 0xAC, 0xB0, 0xB4, 0xB8, 0xBC, 0xC0, 0xC4 },
 267         { 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700, 0x3938700 },
 268         { 0x2AF8, 0x2AF8, 0x29BB, 0x27F9, 0x2637, 0x2475, 0x22B3, 0x20F1, 0x1F2F, 0x1D6D, 0x1734, 0x1414, 0x10F4, 0xDD4, 0xAB4, 0x794 },
 269         85,
 270         true
 271 };
 272
 273 static const struct si_dte_data dte_data_tahiti_pro =
 274 {
 275         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 276         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 277         5,
 278         45000,
 279         100,
 280         0xA,
 281         1,
 282         0,
 283         0x10,
 284         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 285         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 286         { 0x7D0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 287         90,
 288         true
 289 };
 290
 291 static const struct si_dte_data dte_data_new_zealand =
 292 {
 293         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0 },
 294         { 0x29B, 0x3E9, 0x537, 0x7D2, 0 },
 295         0x5,
 296         0xAFC8,
 297         0x69,
 298         0x32,
 299         1,
 300         0,
 301         0x10,
 302         { 0x82, 0xA0, 0xB4, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE, 0xFE },
 303         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 304         { 0xDAC, 0x1388, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685, 0x685 },
 305         85,
 306         true
 307 };
 308
 309 static const struct si_dte_data dte_data_aruba_pro =
 310 {
 311         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 312         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 313         5,
 314         45000,
 315         100,
 316         0xA,
 317         1,
 318         0,
 319         0x10,
 320         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 321         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 322         { 0x1000, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 323         90,
 324         true
 325 };
 326
 327 static const struct si_dte_data dte_data_malta =
 328 {
 329         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 330         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 331         5,
 332         45000,
 333         100,
 334         0xA,
 335         1,
 336         0,
 337         0x10,
 338         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 339         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 340         { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 341         90,
 342         true
 343 };
 344
 345 struct si_cac_config_reg cac_weights_pitcairn[] =
 346 {
 347         { 0x0, 0x0000ffff, 0, 0x8a, SISLANDS_CACCONFIG_CGIND },
 348         { 0x0, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 349         { 0x1, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 350         { 0x1, 0xffff0000, 16, 0x24d, SISLANDS_CACCONFIG_CGIND },
 351         { 0x2, 0x0000ffff, 0, 0x19, SISLANDS_CACCONFIG_CGIND },
 352         { 0x3, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 353         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 354         { 0x4, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
 355         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 356         { 0x5, 0x0000ffff, 0, 0xc11, SISLANDS_CACCONFIG_CGIND },
 357         { 0x5, 0xffff0000, 16, 0x7f3, SISLANDS_CACCONFIG_CGIND },
 358         { 0x6, 0x0000ffff, 0, 0x403, SISLANDS_CACCONFIG_CGIND },
 359         { 0x6, 0xffff0000, 16, 0x367, SISLANDS_CACCONFIG_CGIND },
 360         { 0x18f, 0x0000ffff, 0, 0x4c9, SISLANDS_CACCONFIG_CGIND },
 361         { 0x7, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 362         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 363         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 364         { 0x8, 0xffff0000, 16, 0x45d, SISLANDS_CACCONFIG_CGIND },
 365         { 0x9, 0x0000ffff, 0, 0x36d, SISLANDS_CACCONFIG_CGIND },
 366         { 0xa, 0x0000ffff, 0, 0x534, SISLANDS_CACCONFIG_CGIND },
 367         { 0xb, 0x0000ffff, 0, 0x5da, SISLANDS_CACCONFIG_CGIND },
 368         { 0xb, 0xffff0000, 16, 0x880, SISLANDS_CACCONFIG_CGIND },
 369         { 0xc, 0x0000ffff, 0, 0x201, SISLANDS_CACCONFIG_CGIND },
 370         { 0xd, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 371         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 372         { 0xe, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
 373         { 0xf, 0x0000ffff, 0, 0x1f, SISLANDS_CACCONFIG_CGIND },
 374         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 375         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 376         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 377         { 0x11, 0x0000ffff, 0, 0x5de, SISLANDS_CACCONFIG_CGIND },
 378         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 379         { 0x12, 0x0000ffff, 0, 0x7b, SISLANDS_CACCONFIG_CGIND },
 380         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 381         { 0x13, 0xffff0000, 16, 0x13, SISLANDS_CACCONFIG_CGIND },
 382         { 0x14, 0x0000ffff, 0, 0xf9, SISLANDS_CACCONFIG_CGIND },
 383         { 0x15, 0x0000ffff, 0, 0x66, SISLANDS_CACCONFIG_CGIND },
 384         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 385         { 0x4e, 0x0000ffff, 0, 0x13, SISLANDS_CACCONFIG_CGIND },
 386         { 0x16, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 387         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 388         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 389         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 390         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 391         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 392         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 393         { 0x1a, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 394         { 0x1a, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 395         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 396         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 397         { 0x1c, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 398         { 0x1c, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 399         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 400         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 401         { 0x1e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 402         { 0x1e, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 403         { 0x1f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 404         { 0x1f, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 405         { 0x20, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 406         { 0x6d, 0x0000ffff, 0, 0x186, SISLANDS_CACCONFIG_CGIND },
 407         { 0xFFFFFFFF }
 408 };
 409
 410 static const struct si_cac_config_reg lcac_pitcairn[] =
 411 {
 412         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 413         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 414         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 415         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 416         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 417         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 418         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 419         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 420         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 421         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 422         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 423         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 424         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 425         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 426         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 427         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 428         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 429         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 430         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 431         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 432         { 0x8f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 433         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 434         { 0x146, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 435         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 436         { 0x9e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 437         { 0x9e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 438         { 0x10a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 439         { 0x10a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 440         { 0x116, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 441         { 0x116, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 442         { 0x155, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 443         { 0x155, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 444         { 0x92, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 445         { 0x92, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 446         { 0x149, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 447         { 0x149, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 448         { 0x101, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 449         { 0x101, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 450         { 0x10d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 451         { 0x10d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 452         { 0x119, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 453         { 0x119, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 454         { 0x158, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 455         { 0x158, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 456         { 0x95, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 457         { 0x95, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 458         { 0x14c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 459         { 0x14c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 460         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 461         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 462         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 463         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 464         { 0x122, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 465         { 0x122, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 466         { 0x125, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 467         { 0x125, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 468         { 0x128, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 469         { 0x128, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 470         { 0x12b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 471         { 0x12b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 472         { 0x164, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 473         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 474         { 0x167, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 475         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 476         { 0x16a, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 477         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 478         { 0x15e, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 479         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 480         { 0x161, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 481         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 482         { 0x15b, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 483         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 484         { 0x16d, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
 485         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 486         { 0x170, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 487         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 488         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 489         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 490         { 0x176, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 491         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 492         { 0x179, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 493         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 494         { 0x17c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 495         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 496         { 0x17f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 497         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 498         { 0xFFFFFFFF }
 499 };
 500
 501 static const struct si_cac_config_reg cac_override_pitcairn[] =
 502 {
 503     { 0xFFFFFFFF }
 504 };
 505
 506 static const struct si_powertune_data powertune_data_pitcairn =
 507 {
 508         ((1 << 16) | 27027),
 509         5,
 510         0,
 511         6,
 512         100,
 513         {
 514                 51600000UL,
 515                 1800000UL,
 516                 7194395UL,
 517                 309631529UL,
 518                 -1270850L,
 519                 4513710L,
 520                 100
 521         },
 522         117830498UL,
 523         12,
 524         {
 525                 0,
 526                 0,
 527                 0,
 528                 0,
 529                 0,
 530                 0,
 531                 0,
 532                 0
 533         },
 534         true
 535 };
 536
 537 static const struct si_dte_data dte_data_pitcairn =
 538 {
 539         { 0, 0, 0, 0, 0 },
 540         { 0, 0, 0, 0, 0 },
 541         0,
 542         0,
 543         0,
 544         0,
 545         0,
 546         0,
 547         0,
 548         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 549         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 550         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
 551         0,
 552         false
 553 };
 554
 555 static const struct si_dte_data dte_data_curacao_xt =
 556 {
 557         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 558         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 559         5,
 560         45000,
 561         100,
 562         0xA,
 563         1,
 564         0,
 565         0x10,
 566         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 567         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 568         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 569         90,
 570         true
 571 };
 572
 573 static const struct si_dte_data dte_data_curacao_pro =
 574 {
 575         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 576         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 577         5,
 578         45000,
 579         100,
 580         0xA,
 581         1,
 582         0,
 583         0x10,
 584         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 585         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 586         { 0x1D17, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 587         90,
 588         true
 589 };
 590
 591 static const struct si_dte_data dte_data_neptune_xt =
 592 {
 593         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
 594         { 0x0, 0x0, 0x0, 0x0, 0x0 },
 595         5,
 596         45000,
 597         100,
 598         0xA,
 599         1,
 600         0,
 601         0x10,
 602         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
 603         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
 604         { 0x3A2F, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
 605         90,
 606         true
 607 };
 608
 609 static const struct si_cac_config_reg cac_weights_chelsea_pro[] =
 610 {
 611         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 612         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 613         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 614         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 615         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 616         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 617         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 618         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 619         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 620         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 621         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 622         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 623         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 624         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 625         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 626         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 627         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 628         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 629         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 630         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 631         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 632         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 633         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 634         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 635         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 636         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 637         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 638         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 639         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 640         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 641         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 642         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 643         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 644         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 645         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 646         { 0x14, 0x0000ffff, 0, 0x2BD, SISLANDS_CACCONFIG_CGIND },
 647         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 648         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 649         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 650         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 651         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 652         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 653         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 654         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 655         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 656         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 657         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 658         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 659         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 660         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 661         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 662         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 663         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 664         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 665         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 666         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 667         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 668         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 669         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 670         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 671         { 0xFFFFFFFF }
 672 };
 673
 674 static const struct si_cac_config_reg cac_weights_chelsea_xt[] =
 675 {
 676         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 677         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 678         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 679         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 680         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 681         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 682         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 683         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 684         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 685         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 686         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 687         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 688         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 689         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 690         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 691         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 692         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 693         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 694         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 695         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 696         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 697         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 698         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 699         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 700         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 701         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 702         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 703         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 704         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 705         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 706         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 707         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 708         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 709         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 710         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 711         { 0x14, 0x0000ffff, 0, 0x30A, SISLANDS_CACCONFIG_CGIND },
 712         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 713         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 714         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 715         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 716         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 717         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 718         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 719         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 720         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 721         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 722         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 723         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 724         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 725         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 726         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 727         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 728         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 729         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 730         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 731         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 732         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 733         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 734         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 735         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 736         { 0xFFFFFFFF }
 737 };
 738
 739 static const struct si_cac_config_reg cac_weights_heathrow[] =
 740 {
 741         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 742         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 743         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 744         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 745         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 746         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 747         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 748         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 749         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 750         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 751         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 752         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 753         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 754         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 755         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 756         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 757         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 758         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 759         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 760         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 761         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 762         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 763         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 764         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 765         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 766         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 767         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 768         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 769         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 770         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 771         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 772         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 773         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 774         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 775         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 776         { 0x14, 0x0000ffff, 0, 0x362, SISLANDS_CACCONFIG_CGIND },
 777         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 778         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 779         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 780         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 781         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 782         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 783         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 784         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 785         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 786         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 787         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 788         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 789         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 790         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 791         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 792         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 793         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 794         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 795         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 796         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 797         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 798         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 799         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 800         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 801         { 0xFFFFFFFF }
 802 };
 803
 804 static const struct si_cac_config_reg cac_weights_cape_verde_pro[] =
 805 {
 806         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 807         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 808         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 809         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 810         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 811         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 812         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 813         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 814         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 815         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 816         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 817         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 818         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 819         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 820         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 821         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 822         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 823         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 824         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 825         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 826         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 827         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 828         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 829         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 830         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 831         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 832         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 833         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 834         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 835         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 836         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 837         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 838         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 839         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 840         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 841         { 0x14, 0x0000ffff, 0, 0x315, SISLANDS_CACCONFIG_CGIND },
 842         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 843         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 844         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 845         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 846         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 847         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 848         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 849         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 850         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 851         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 852         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 853         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 854         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 855         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 856         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 857         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 858         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 859         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 860         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 861         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 862         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 863         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 864         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 865         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 866         { 0xFFFFFFFF }
 867 };
 868
 869 static const struct si_cac_config_reg cac_weights_cape_verde[] =
 870 {
 871         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
 872         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 873         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
 874         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
 875         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 876         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 877         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
 878         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
 879         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
 880         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
 881         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
 882         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
 883         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
 884         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 885         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
 886         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
 887         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
 888         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
 889         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
 890         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
 891         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
 892         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
 893         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
 894         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
 895         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
 896         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 897         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
 898         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 899         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 900         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
 901         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
 902         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
 903         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
 904         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
 905         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
 906         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
 907         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 908         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
 909         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 910         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
 911         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
 912         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 913         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 914         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 915         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
 916         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
 917         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 918         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 919         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 920         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 921         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 922         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 923         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 924         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 925         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 926         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 927         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 928         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
 929         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
 930         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
 931         { 0xFFFFFFFF }
 932 };
 933
 934 static const struct si_cac_config_reg lcac_cape_verde[] =
 935 {
 936         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 937         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 938         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 939         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 940         { 0x110, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 941         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 942         { 0x14f, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 943         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 944         { 0x8c, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 945         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 946         { 0x143, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 947         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 948         { 0x9b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 949         { 0x9b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 950         { 0x107, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 951         { 0x107, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 952         { 0x113, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 953         { 0x113, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 954         { 0x152, 0x0001fffe, 1, 0x5, SISLANDS_CACCONFIG_CGIND },
 955         { 0x152, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 956         { 0x8f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 957         { 0x8f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 958         { 0x146, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 959         { 0x146, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 960         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 961         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 962         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 963         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 964         { 0x164, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 965         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 966         { 0x167, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 967         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 968         { 0x16a, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 969         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 970         { 0x15e, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 971         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 972         { 0x161, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 973         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 974         { 0x15b, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 975         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 976         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 977         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 978         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 979         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 980         { 0x173, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
 981         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 982         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 983         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 984         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 985         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 986         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 987         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 988         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
 989         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
 990         { 0xFFFFFFFF }
 991 };
 992
 993 static const struct si_cac_config_reg cac_override_cape_verde[] =
 994 {
 995     { 0xFFFFFFFF }
 996 };
 997
 998 static const struct si_powertune_data powertune_data_cape_verde =
 999 {
1000         ((1 << 16) | 0x6993),
1001         5,
1002         0,
1003         7,
1004         105,
1005         {
1006                 0UL,
1007                 0UL,
1008                 7194395UL,
1009                 309631529UL,
1010                 -1270850L,
1011                 4513710L,
1012                 100
1013         },
1014         117830498UL,
1015         12,
1016         {
1017                 0,
1018                 0,
1019                 0,
1020                 0,
1021                 0,
1022                 0,
1023                 0,
1024                 0
1025         },
1026         true
1027 };
1028
1029 static const struct si_dte_data dte_data_cape_verde =
1030 {
1031         { 0, 0, 0, 0, 0 },
1032         { 0, 0, 0, 0, 0 },
1033         0,
1034         0,
1035         0,
1036         0,
1037         0,
1038         0,
1039         0,
1040         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1041         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1042         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1043         0,
1044         false
1045 };
1046
1047 static const struct si_dte_data dte_data_venus_xtx =
1048 {
1049         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1050         { 0x71C, 0xAAB, 0xE39, 0x11C7, 0x0 },
1051         5,
1052         55000,
1053         0x69,
1054         0xA,
1055         1,
1056         0,
1057         0x3,
1058         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1059         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1060         { 0xD6D8, 0x88B8, 0x1555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1061         90,
1062         true
1063 };
1064
1065 static const struct si_dte_data dte_data_venus_xt =
1066 {
1067         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1068         { 0xBDA, 0x11C7, 0x17B4, 0x1DA1, 0x0 },
1069         5,
1070         55000,
1071         0x69,
1072         0xA,
1073         1,
1074         0,
1075         0x3,
1076         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1077         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1078         { 0xAFC8, 0x88B8, 0x238E, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1079         90,
1080         true
1081 };
1082
1083 static const struct si_dte_data dte_data_venus_pro =
1084 {
1085         {  0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1086         { 0x11C7, 0x1AAB, 0x238E, 0x2C72, 0x0 },
1087         5,
1088         55000,
1089         0x69,
1090         0xA,
1091         1,
1092         0,
1093         0x3,
1094         { 0x96, 0xB4, 0xFF, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1095         { 0x895440, 0x3D0900, 0x989680, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1096         { 0x88B8, 0x88B8, 0x3555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1097         90,
1098         true
1099 };
1100
1101 struct si_cac_config_reg cac_weights_oland[] =
1102 {
1103         { 0x0, 0x0000ffff, 0, 0x82, SISLANDS_CACCONFIG_CGIND },
1104         { 0x0, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1105         { 0x1, 0x0000ffff, 0, 0x153, SISLANDS_CACCONFIG_CGIND },
1106         { 0x1, 0xffff0000, 16, 0x52, SISLANDS_CACCONFIG_CGIND },
1107         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1108         { 0x3, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1109         { 0x3, 0xffff0000, 16, 0x4F, SISLANDS_CACCONFIG_CGIND },
1110         { 0x4, 0x0000ffff, 0, 0x135, SISLANDS_CACCONFIG_CGIND },
1111         { 0x4, 0xffff0000, 16, 0xAC, SISLANDS_CACCONFIG_CGIND },
1112         { 0x5, 0x0000ffff, 0, 0x118, SISLANDS_CACCONFIG_CGIND },
1113         { 0x5, 0xffff0000, 16, 0xBE, SISLANDS_CACCONFIG_CGIND },
1114         { 0x6, 0x0000ffff, 0, 0x110, SISLANDS_CACCONFIG_CGIND },
1115         { 0x6, 0xffff0000, 16, 0x4CD, SISLANDS_CACCONFIG_CGIND },
1116         { 0x18f, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1117         { 0x7, 0x0000ffff, 0, 0x37, SISLANDS_CACCONFIG_CGIND },
1118         { 0x7, 0xffff0000, 16, 0x27, SISLANDS_CACCONFIG_CGIND },
1119         { 0x8, 0x0000ffff, 0, 0xC3, SISLANDS_CACCONFIG_CGIND },
1120         { 0x8, 0xffff0000, 16, 0x35, SISLANDS_CACCONFIG_CGIND },
1121         { 0x9, 0x0000ffff, 0, 0x28, SISLANDS_CACCONFIG_CGIND },
1122         { 0xa, 0x0000ffff, 0, 0x26C, SISLANDS_CACCONFIG_CGIND },
1123         { 0xb, 0x0000ffff, 0, 0x3B2, SISLANDS_CACCONFIG_CGIND },
1124         { 0xb, 0xffff0000, 16, 0x99D, SISLANDS_CACCONFIG_CGIND },
1125         { 0xc, 0x0000ffff, 0, 0xA3F, SISLANDS_CACCONFIG_CGIND },
1126         { 0xd, 0x0000ffff, 0, 0xA, SISLANDS_CACCONFIG_CGIND },
1127         { 0xd, 0xffff0000, 16, 0xA, SISLANDS_CACCONFIG_CGIND },
1128         { 0xe, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1129         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1130         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1131         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1132         { 0x10, 0xffff0000, 16, 0x1, SISLANDS_CACCONFIG_CGIND },
1133         { 0x11, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1134         { 0x11, 0xffff0000, 16, 0x15, SISLANDS_CACCONFIG_CGIND },
1135         { 0x12, 0x0000ffff, 0, 0x34, SISLANDS_CACCONFIG_CGIND },
1136         { 0x13, 0x0000ffff, 0, 0x4, SISLANDS_CACCONFIG_CGIND },
1137         { 0x13, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1138         { 0x14, 0x0000ffff, 0, 0x3BA, SISLANDS_CACCONFIG_CGIND },
1139         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1140         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1141         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1142         { 0x16, 0x0000ffff, 0, 0x30, SISLANDS_CACCONFIG_CGIND },
1143         { 0x16, 0xffff0000, 16, 0x7A, SISLANDS_CACCONFIG_CGIND },
1144         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1145         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1146         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1147         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1148         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1149         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1150         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1151         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1152         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1153         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1154         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1155         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1156         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1157         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1158         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1159         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1160         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1161         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1162         { 0x6d, 0x0000ffff, 0, 0x100, SISLANDS_CACCONFIG_CGIND },
1163         { 0xFFFFFFFF }
1164 };
1165
1166 static const struct si_cac_config_reg cac_weights_mars_pro[] =
1167 {
1168         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1169         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1170         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1171         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1172         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1173         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1174         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1175         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1176         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1177         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1178         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1179         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1180         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1181         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1182         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1183         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1184         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1185         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1186         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1187         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1188         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1189         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1190         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1191         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1192         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1193         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1194         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1195         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1196         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1197         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1198         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1199         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1200         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1201         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1202         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1203         { 0x14, 0x0000ffff, 0, 0x2, SISLANDS_CACCONFIG_CGIND },
1204         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1205         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1206         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1207         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1208         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1209         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1210         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1211         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1212         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1213         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1214         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1215         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1216         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1217         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1218         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1219         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1220         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1221         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1222         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1223         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1224         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1225         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1226         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1227         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1228         { 0xFFFFFFFF }
1229 };
1230
1231 static const struct si_cac_config_reg cac_weights_mars_xt[] =
1232 {
1233         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1234         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1235         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1236         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1237         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1238         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1239         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1240         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1241         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1242         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1243         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1244         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1245         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1246         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1247         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1248         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1249         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1250         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1251         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1252         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1253         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1254         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1255         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1256         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1257         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1258         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1259         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1260         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1261         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1262         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1263         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1264         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1265         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1266         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1267         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1268         { 0x14, 0x0000ffff, 0, 0x60, SISLANDS_CACCONFIG_CGIND },
1269         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1270         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1271         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1272         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1273         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1274         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1275         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1276         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1277         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1278         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1279         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1280         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1281         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1282         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1283         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1284         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1285         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1286         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1287         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1288         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1289         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1290         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1291         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1292         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1293         { 0xFFFFFFFF }
1294 };
1295
1296 static const struct si_cac_config_reg cac_weights_oland_pro[] =
1297 {
1298         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1299         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1300         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1301         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1302         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1303         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1304         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1305         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1306         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1307         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1308         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1309         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1310         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1311         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1312         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1313         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1314         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1315         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1316         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1317         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1318         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1319         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1320         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1321         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1322         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1323         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1324         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1325         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1326         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1327         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1328         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1329         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1330         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1331         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1332         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1333         { 0x14, 0x0000ffff, 0, 0x90, SISLANDS_CACCONFIG_CGIND },
1334         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1335         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1336         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1337         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1338         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1339         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1340         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1341         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1342         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1343         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1344         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1345         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1346         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1347         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1348         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1349         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1350         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1351         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1352         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1353         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1354         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1355         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1356         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1357         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1358         { 0xFFFFFFFF }
1359 };
1360
1361 static const struct si_cac_config_reg cac_weights_oland_xt[] =
1362 {
1363         { 0x0, 0x0000ffff, 0, 0x43, SISLANDS_CACCONFIG_CGIND },
1364         { 0x0, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1365         { 0x1, 0x0000ffff, 0, 0xAF, SISLANDS_CACCONFIG_CGIND },
1366         { 0x1, 0xffff0000, 16, 0x2A, SISLANDS_CACCONFIG_CGIND },
1367         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1368         { 0x3, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1369         { 0x3, 0xffff0000, 16, 0x29, SISLANDS_CACCONFIG_CGIND },
1370         { 0x4, 0x0000ffff, 0, 0xA0, SISLANDS_CACCONFIG_CGIND },
1371         { 0x4, 0xffff0000, 16, 0x59, SISLANDS_CACCONFIG_CGIND },
1372         { 0x5, 0x0000ffff, 0, 0x1A5, SISLANDS_CACCONFIG_CGIND },
1373         { 0x5, 0xffff0000, 16, 0x1D6, SISLANDS_CACCONFIG_CGIND },
1374         { 0x6, 0x0000ffff, 0, 0x2A3, SISLANDS_CACCONFIG_CGIND },
1375         { 0x6, 0xffff0000, 16, 0x8FD, SISLANDS_CACCONFIG_CGIND },
1376         { 0x18f, 0x0000ffff, 0, 0x76, SISLANDS_CACCONFIG_CGIND },
1377         { 0x7, 0x0000ffff, 0, 0x8A, SISLANDS_CACCONFIG_CGIND },
1378         { 0x7, 0xffff0000, 16, 0xA3, SISLANDS_CACCONFIG_CGIND },
1379         { 0x8, 0x0000ffff, 0, 0x71, SISLANDS_CACCONFIG_CGIND },
1380         { 0x8, 0xffff0000, 16, 0x36, SISLANDS_CACCONFIG_CGIND },
1381         { 0x9, 0x0000ffff, 0, 0xA6, SISLANDS_CACCONFIG_CGIND },
1382         { 0xa, 0x0000ffff, 0, 0x81, SISLANDS_CACCONFIG_CGIND },
1383         { 0xb, 0x0000ffff, 0, 0x3D2, SISLANDS_CACCONFIG_CGIND },
1384         { 0xb, 0xffff0000, 16, 0x27C, SISLANDS_CACCONFIG_CGIND },
1385         { 0xc, 0x0000ffff, 0, 0xA96, SISLANDS_CACCONFIG_CGIND },
1386         { 0xd, 0x0000ffff, 0, 0x5, SISLANDS_CACCONFIG_CGIND },
1387         { 0xd, 0xffff0000, 16, 0x5, SISLANDS_CACCONFIG_CGIND },
1388         { 0xe, 0x0000ffff, 0, 0xB, SISLANDS_CACCONFIG_CGIND },
1389         { 0xf, 0x0000ffff, 0, 0x3, SISLANDS_CACCONFIG_CGIND },
1390         { 0xf, 0xffff0000, 16, 0x2, SISLANDS_CACCONFIG_CGIND },
1391         { 0x10, 0x0000ffff, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1392         { 0x10, 0xffff0000, 16, 0x4, SISLANDS_CACCONFIG_CGIND },
1393         { 0x11, 0x0000ffff, 0, 0x15, SISLANDS_CACCONFIG_CGIND },
1394         { 0x11, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1395         { 0x12, 0x0000ffff, 0, 0x36, SISLANDS_CACCONFIG_CGIND },
1396         { 0x13, 0x0000ffff, 0, 0x10, SISLANDS_CACCONFIG_CGIND },
1397         { 0x13, 0xffff0000, 16, 0x10, SISLANDS_CACCONFIG_CGIND },
1398         { 0x14, 0x0000ffff, 0, 0x120, SISLANDS_CACCONFIG_CGIND },
1399         { 0x15, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1400         { 0x15, 0xffff0000, 16, 0x6, SISLANDS_CACCONFIG_CGIND },
1401         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1402         { 0x16, 0x0000ffff, 0, 0x32, SISLANDS_CACCONFIG_CGIND },
1403         { 0x16, 0xffff0000, 16, 0x7E, SISLANDS_CACCONFIG_CGIND },
1404         { 0x17, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1405         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1406         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1407         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1408         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1409         { 0x1a, 0x0000ffff, 0, 0x280, SISLANDS_CACCONFIG_CGIND },
1410         { 0x1a, 0xffff0000, 16, 0x7, SISLANDS_CACCONFIG_CGIND },
1411         { 0x1b, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1412         { 0x1b, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1413         { 0x1c, 0x0000ffff, 0, 0x3C, SISLANDS_CACCONFIG_CGIND },
1414         { 0x1c, 0xffff0000, 16, 0x203, SISLANDS_CACCONFIG_CGIND },
1415         { 0x1d, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1416         { 0x1d, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1417         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1418         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1419         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1420         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1421         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1422         { 0x6d, 0x0000ffff, 0, 0xB4, SISLANDS_CACCONFIG_CGIND },
1423         { 0xFFFFFFFF }
1424 };
1425
1426 static const struct si_cac_config_reg lcac_oland[] =
1427 {
1428         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1429         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1430         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1431         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1432         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1433         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1434         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1435         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1436         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1437         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1438         { 0x143, 0x0001fffe, 1, 0x4, SISLANDS_CACCONFIG_CGIND },
1439         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1440         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1441         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1442         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1443         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1444         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1445         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1446         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1447         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1448         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1449         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1450         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1451         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1452         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1453         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1454         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1455         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1456         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1457         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1458         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1459         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1460         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1461         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1462         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1463         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1464         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1465         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1466         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1467         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1468         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1469         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1470         { 0xFFFFFFFF }
1471 };
1472
1473 static const struct si_cac_config_reg lcac_mars_pro[] =
1474 {
1475         { 0x98, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1476         { 0x98, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1477         { 0x104, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1478         { 0x104, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1479         { 0x110, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1480         { 0x110, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1481         { 0x14f, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1482         { 0x14f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1483         { 0x8c, 0x0001fffe, 1, 0x6, SISLANDS_CACCONFIG_CGIND },
1484         { 0x8c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1485         { 0x143, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1486         { 0x143, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1487         { 0x11c, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1488         { 0x11c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1489         { 0x11f, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1490         { 0x11f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1491         { 0x164, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1492         { 0x164, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1493         { 0x167, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1494         { 0x167, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1495         { 0x16a, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1496         { 0x16a, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1497         { 0x15e, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1498         { 0x15e, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1499         { 0x161, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1500         { 0x161, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1501         { 0x15b, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1502         { 0x15b, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1503         { 0x16d, 0x0001fffe, 1, 0x2, SISLANDS_CACCONFIG_CGIND },
1504         { 0x16d, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1505         { 0x170, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1506         { 0x170, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1507         { 0x173, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1508         { 0x173, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1509         { 0x176, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1510         { 0x176, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1511         { 0x179, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1512         { 0x179, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1513         { 0x17c, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1514         { 0x17c, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1515         { 0x17f, 0x0001fffe, 1, 0x1, SISLANDS_CACCONFIG_CGIND },
1516         { 0x17f, 0x00000001, 0, 0x1, SISLANDS_CACCONFIG_CGIND },
1517         { 0xFFFFFFFF }
1518 };
1519
1520 static const struct si_cac_config_reg cac_override_oland[] =
1521 {
1522         { 0xFFFFFFFF }
1523 };
1524
1525 static const struct si_powertune_data powertune_data_oland =
1526 {
1527         ((1 << 16) | 0x6993),
1528         5,
1529         0,
1530         7,
1531         105,
1532         {
1533                 0UL,
1534                 0UL,
1535                 7194395UL,
1536                 309631529UL,
1537                 -1270850L,
1538                 4513710L,
1539                 100
1540         },
1541         117830498UL,
1542         12,
1543         {
1544                 0,
1545                 0,
1546                 0,
1547                 0,
1548                 0,
1549                 0,
1550                 0,
1551                 0
1552         },
1553         true
1554 };
1555
1556 static const struct si_powertune_data powertune_data_mars_pro =
1557 {
1558         ((1 << 16) | 0x6993),
1559         5,
1560         0,
1561         7,
1562         105,
1563         {
1564                 0UL,
1565                 0UL,
1566                 7194395UL,
1567                 309631529UL,
1568                 -1270850L,
1569                 4513710L,
1570                 100
1571         },
1572         117830498UL,
1573         12,
1574         {
1575                 0,
1576                 0,
1577                 0,
1578                 0,
1579                 0,
1580                 0,
1581                 0,
1582                 0
1583         },
1584         true
1585 };
1586
1587 static const struct si_dte_data dte_data_oland =
1588 {
1589         { 0, 0, 0, 0, 0 },
1590         { 0, 0, 0, 0, 0 },
1591         0,
1592         0,
1593         0,
1594         0,
1595         0,
1596         0,
1597         0,
1598         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1599         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1600         { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 },
1601         0,
1602         false
1603 };
1604
1605 static const struct si_dte_data dte_data_mars_pro =
1606 {
1607         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1608         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1609         5,
1610         55000,
1611         105,
1612         0xA,
1613         1,
1614         0,
1615         0x10,
1616         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1617         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1618         { 0xF627, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1619         90,
1620         true
1621 };
1622
1623 static const struct si_dte_data dte_data_sun_xt =
1624 {
1625         { 0x1E8480, 0x3D0900, 0x989680, 0x2625A00, 0x0 },
1626         { 0x0, 0x0, 0x0, 0x0, 0x0 },
1627         5,
1628         55000,
1629         105,
1630         0xA,
1631         1,
1632         0,
1633         0x10,
1634         { 0x96, 0xB4, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF },
1635         { 0x895440, 0x3D0900, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680, 0x989680 },
1636         { 0xD555, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 },
1637         90,
1638         true
1639 };
1640
1641
1642 static const struct si_cac_config_reg cac_weights_hainan[] =
1643 {
1644         { 0x0, 0x0000ffff, 0, 0x2d9, SISLANDS_CACCONFIG_CGIND },
1645         { 0x0, 0xffff0000, 16, 0x22b, SISLANDS_CACCONFIG_CGIND },
1646         { 0x1, 0x0000ffff, 0, 0x21c, SISLANDS_CACCONFIG_CGIND },
1647         { 0x1, 0xffff0000, 16, 0x1dc, SISLANDS_CACCONFIG_CGIND },
1648         { 0x2, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1649         { 0x3, 0x0000ffff, 0, 0x24e, SISLANDS_CACCONFIG_CGIND },
1650         { 0x3, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1651         { 0x4, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1652         { 0x4, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1653         { 0x5, 0x0000ffff, 0, 0x35e, SISLANDS_CACCONFIG_CGIND },
1654         { 0x5, 0xffff0000, 16, 0x1143, SISLANDS_CACCONFIG_CGIND },
1655         { 0x6, 0x0000ffff, 0, 0xe17, SISLANDS_CACCONFIG_CGIND },
1656         { 0x6, 0xffff0000, 16, 0x441, SISLANDS_CACCONFIG_CGIND },
1657         { 0x18f, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1658         { 0x7, 0x0000ffff, 0, 0x28b, SISLANDS_CACCONFIG_CGIND },
1659         { 0x7, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1660         { 0x8, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1661         { 0x8, 0xffff0000, 16, 0xabe, SISLANDS_CACCONFIG_CGIND },
1662         { 0x9, 0x0000ffff, 0, 0xf11, SISLANDS_CACCONFIG_CGIND },
1663         { 0xa, 0x0000ffff, 0, 0x907, SISLANDS_CACCONFIG_CGIND },
1664         { 0xb, 0x0000ffff, 0, 0xb45, SISLANDS_CACCONFIG_CGIND },
1665         { 0xb, 0xffff0000, 16, 0xd1e, SISLANDS_CACCONFIG_CGIND },
1666         { 0xc, 0x0000ffff, 0, 0xa2c, SISLANDS_CACCONFIG_CGIND },
1667         { 0xd, 0x0000ffff, 0, 0x62, SISLANDS_CACCONFIG_CGIND },
1668         { 0xd, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1669         { 0xe, 0x0000ffff, 0, 0x1f3, SISLANDS_CACCONFIG_CGIND },
1670         { 0xf, 0x0000ffff, 0, 0x42, SISLANDS_CACCONFIG_CGIND },
1671         { 0xf, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1672         { 0x10, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1673         { 0x10, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1674         { 0x11, 0x0000ffff, 0, 0x709, SISLANDS_CACCONFIG_CGIND },
1675         { 0x11, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1676         { 0x12, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1677         { 0x13, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1678         { 0x13, 0xffff0000, 16, 0x3a, SISLANDS_CACCONFIG_CGIND },
1679         { 0x14, 0x0000ffff, 0, 0x357, SISLANDS_CACCONFIG_CGIND },
1680         { 0x15, 0x0000ffff, 0, 0x9f, SISLANDS_CACCONFIG_CGIND },
1681         { 0x15, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1682         { 0x4e, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1683         { 0x16, 0x0000ffff, 0, 0x314, SISLANDS_CACCONFIG_CGIND },
1684         { 0x16, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1685         { 0x17, 0x0000ffff, 0, 0x6d, SISLANDS_CACCONFIG_CGIND },
1686         { 0x18, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1687         { 0x18, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1688         { 0x19, 0x0000ffff, 0, 0x0, SISLANDS_CACCONFIG_CGIND },
1689         { 0x19, 0xffff0000, 16, 0x0, SISLANDS_CACCONFIG_CGIND },
1690         { 0x1a, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1691         { 0x1a, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1692         { 0x1b, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1693         { 0x1b, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1694         { 0x1c, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1695         { 0x1c, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1696         { 0x1d, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1697         { 0x1d, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1698         { 0x1e, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1699         { 0x1e, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1700         { 0x1f, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1701         { 0x1f, 0xffff0000, 16, 0, SISLANDS_CACCONFIG_CGIND },
1702         { 0x20, 0x0000ffff, 0, 0, SISLANDS_CACCONFIG_CGIND },
1703         { 0x6d, 0x0000ffff, 0, 0x1b9, SISLANDS_CACCONFIG_CGIND },
1704         { 0xFFFFFFFF }
1705 };
1706
1707 static const struct si_powertune_data powertune_data_hainan =
1708 {
1709         ((1 << 16) | 0x6993),
1710         5,
1711         0,
1712         9,
1713         105,
1714         {
1715                 0UL,
1716                 0UL,
1717                 7194395UL,
1718                 309631529UL,
1719                 -1270850L,
1720                 4513710L,
1721                 100
1722         },
1723         117830498UL,
1724         12,
1725         {
1726                 0,
1727                 0,
1728                 0,
1729                 0,
1730                 0,
1731                 0,
1732                 0,
1733                 0
1734         },
1735         true
1736 };
1737
1738 struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev);
1739 struct evergreen_power_info *evergreen_get_pi(struct radeon_device *rdev);
1740 struct ni_power_info *ni_get_pi(struct radeon_device *rdev);
1741 struct ni_ps *ni_get_ps(struct radeon_ps *rps);
1742
1743 static int si_populate_voltage_value(struct radeon_device *rdev,
1744                                      const struct atom_voltage_table *table,
1745                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage);
1746 static int si_get_std_voltage_value(struct radeon_device *rdev,
1747                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
1748                                     u16 *std_voltage);
1749 static int si_write_smc_soft_register(struct radeon_device *rdev,
1750                                       u16 reg_offset, u32 value);
1751 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
1752                                          struct rv7xx_pl *pl,
1753                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level);
1754 static int si_calculate_sclk_params(struct radeon_device *rdev,
1755                                     u32 engine_clock,
1756                                     SISLANDS_SMC_SCLK_VALUE *sclk);
1757
1758 static struct si_power_info *si_get_pi(struct radeon_device *rdev)
1759 {
1760         struct si_power_info *pi = rdev->pm.dpm.priv;
1761
1762         return pi;
1763 }
1764
1765 static void si_calculate_leakage_for_v_and_t_formula(const struct ni_leakage_coeffients *coeff,
1766                                                      u16 v, s32 t, u32 ileakage, u32 *leakage)
1767 {
1768         s64 kt, kv, leakage_w, i_leakage, vddc;
1769         s64 temperature, t_slope, t_intercept, av, bv, t_ref;
1770
1771         i_leakage = drm_int2fixp(ileakage / 100);
1772         vddc = div64_s64(drm_int2fixp(v), 1000);
1773         temperature = div64_s64(drm_int2fixp(t), 1000);
1774
1775         t_slope = div64_s64(drm_int2fixp(coeff->t_slope), 100000000);
1776         t_intercept = div64_s64(drm_int2fixp(coeff->t_intercept), 100000000);
1777         av = div64_s64(drm_int2fixp(coeff->av), 100000000);
1778         bv = div64_s64(drm_int2fixp(coeff->bv), 100000000);
1779         t_ref = drm_int2fixp(coeff->t_ref);
1780
1781         kt = drm_fixp_div(drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, temperature)),
1782                           drm_fixp_exp(drm_fixp_mul(drm_fixp_mul(t_slope, vddc) + t_intercept, t_ref)));
1783         kv = drm_fixp_mul(av, drm_fixp_exp(drm_fixp_mul(bv, vddc)));
1784
1785         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1786
1787         *leakage = drm_fixp2int(leakage_w * 1000);
1788 }
1789
1790 static void si_calculate_leakage_for_v_and_t(struct radeon_device *rdev,
1791                                              const struct ni_leakage_coeffients *coeff,
1792                                              u16 v,
1793                                              s32 t,
1794                                              u32 i_leakage,
1795                                              u32 *leakage)
1796 {
1797         si_calculate_leakage_for_v_and_t_formula(coeff, v, t, i_leakage, leakage);
1798 }
1799
1800 static void si_calculate_leakage_for_v_formula(const struct ni_leakage_coeffients *coeff,
1801                                                const u32 fixed_kt, u16 v,
1802                                                u32 ileakage, u32 *leakage)
1803 {
1804         s64 kt, kv, leakage_w, i_leakage, vddc;
1805
1806         i_leakage = div64_s64(drm_int2fixp(ileakage), 100);
1807         vddc = div64_s64(drm_int2fixp(v), 1000);
1808
1809         kt = div64_s64(drm_int2fixp(fixed_kt), 100000000);
1810         kv = drm_fixp_mul(div64_s64(drm_int2fixp(coeff->av), 100000000),
1811                           drm_fixp_exp(drm_fixp_mul(div64_s64(drm_int2fixp(coeff->bv), 100000000), vddc)));
1812
1813         leakage_w = drm_fixp_mul(drm_fixp_mul(drm_fixp_mul(i_leakage, kt), kv), vddc);
1814
1815         *leakage = drm_fixp2int(leakage_w * 1000);
1816 }
1817
1818 static void si_calculate_leakage_for_v(struct radeon_device *rdev,
1819                                        const struct ni_leakage_coeffients *coeff,
1820                                        const u32 fixed_kt,
1821                                        u16 v,
1822                                        u32 i_leakage,
1823                                        u32 *leakage)
1824 {
1825         si_calculate_leakage_for_v_formula(coeff, fixed_kt, v, i_leakage, leakage);
1826 }
1827
1828
1829 static void si_update_dte_from_pl2(struct radeon_device *rdev,
1830                                    struct si_dte_data *dte_data)
1831 {
1832         u32 p_limit1 = rdev->pm.dpm.tdp_limit;
1833         u32 p_limit2 = rdev->pm.dpm.near_tdp_limit;
1834         u32 k = dte_data->k;
1835         u32 t_max = dte_data->max_t;
1836         u32 t_split[5] = { 10, 15, 20, 25, 30 };
1837         u32 t_0 = dte_data->t0;
1838         u32 i;
1839
1840         if (p_limit2 != 0 && p_limit2 <= p_limit1) {
1841                 dte_data->tdep_count = 3;
1842
1843                 for (i = 0; i < k; i++) {
1844                         dte_data->r[i] =
1845                                 (t_split[i] * (t_max - t_0/(u32)1000) * (1 << 14)) /
1846                                 (p_limit2  * (u32)100);
1847                 }
1848
1849                 dte_data->tdep_r[1] = dte_data->r[4] * 2;
1850
1851                 for (i = 2; i < SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE; i++) {
1852                         dte_data->tdep_r[i] = dte_data->r[4];
1853                 }
1854         } else {
1855                 DRM_ERROR("Invalid PL2! DTE will not be updated.\n");
1856         }
1857 }
1858
1859 static void si_initialize_powertune_defaults(struct radeon_device *rdev)
1860 {
1861         struct ni_power_info *ni_pi = ni_get_pi(rdev);
1862         struct si_power_info *si_pi = si_get_pi(rdev);
1863         bool update_dte_from_pl2 = false;
1864
1865         if (rdev->family == CHIP_TAHITI) {
1866                 si_pi->cac_weights = cac_weights_tahiti;
1867                 si_pi->lcac_config = lcac_tahiti;
1868                 si_pi->cac_override = cac_override_tahiti;
1869                 si_pi->powertune_data = &powertune_data_tahiti;
1870                 si_pi->dte_data = dte_data_tahiti;
1871
1872                 switch (rdev->pdev->device) {
1873                 case 0x6798:
1874                         si_pi->dte_data.enable_dte_by_default = true;
1875                         break;
1876                 case 0x6799:
1877                         si_pi->dte_data = dte_data_new_zealand;
1878                         break;
1879                 case 0x6790:
1880                 case 0x6791:
1881                 case 0x6792:
1882                 case 0x679E:
1883                         si_pi->dte_data = dte_data_aruba_pro;
1884                         update_dte_from_pl2 = true;
1885                         break;
1886                 case 0x679B:
1887                         si_pi->dte_data = dte_data_malta;
1888                         update_dte_from_pl2 = true;
1889                         break;
1890                 case 0x679A:
1891                         si_pi->dte_data = dte_data_tahiti_pro;
1892                         update_dte_from_pl2 = true;
1893                         break;
1894                 default:
1895                         if (si_pi->dte_data.enable_dte_by_default == true)
1896                                 DRM_ERROR("DTE is not enabled!\n");
1897                         break;
1898                 }
1899         } else if (rdev->family == CHIP_PITCAIRN) {
1900                 switch (rdev->pdev->device) {
1901                 case 0x6810:
1902                 case 0x6818:
1903                         si_pi->cac_weights = cac_weights_pitcairn;
1904                         si_pi->lcac_config = lcac_pitcairn;
1905                         si_pi->cac_override = cac_override_pitcairn;
1906                         si_pi->powertune_data = &powertune_data_pitcairn;
1907                         si_pi->dte_data = dte_data_curacao_xt;
1908                         update_dte_from_pl2 = true;
1909                         break;
1910                 case 0x6819:
1911                 case 0x6811:
1912                         si_pi->cac_weights = cac_weights_pitcairn;
1913                         si_pi->lcac_config = lcac_pitcairn;
1914                         si_pi->cac_override = cac_override_pitcairn;
1915                         si_pi->powertune_data = &powertune_data_pitcairn;
1916                         si_pi->dte_data = dte_data_curacao_pro;
1917                         update_dte_from_pl2 = true;
1918                         break;
1919                 case 0x6800:
1920                 case 0x6806:
1921                         si_pi->cac_weights = cac_weights_pitcairn;
1922                         si_pi->lcac_config = lcac_pitcairn;
1923                         si_pi->cac_override = cac_override_pitcairn;
1924                         si_pi->powertune_data = &powertune_data_pitcairn;
1925                         si_pi->dte_data = dte_data_neptune_xt;
1926                         update_dte_from_pl2 = true;
1927                         break;
1928                 default:
1929                         si_pi->cac_weights = cac_weights_pitcairn;
1930                         si_pi->lcac_config = lcac_pitcairn;
1931                         si_pi->cac_override = cac_override_pitcairn;
1932                         si_pi->powertune_data = &powertune_data_pitcairn;
1933                         si_pi->dte_data = dte_data_pitcairn;
1934                 }
1935         } else if (rdev->family == CHIP_VERDE) {
1936                 si_pi->lcac_config = lcac_cape_verde;
1937                 si_pi->cac_override = cac_override_cape_verde;
1938                 si_pi->powertune_data = &powertune_data_cape_verde;
1939
1940                 switch (rdev->pdev->device) {
1941                 case 0x683B:
1942                 case 0x683F:
1943                 case 0x6829:
1944                         si_pi->cac_weights = cac_weights_cape_verde_pro;
1945                         si_pi->dte_data = dte_data_cape_verde;
1946                         break;
1947                 case 0x6825:
1948                 case 0x6827:
1949                         si_pi->cac_weights = cac_weights_heathrow;
1950                         si_pi->dte_data = dte_data_cape_verde;
1951                         break;
1952                 case 0x6824:
1953                 case 0x682D:
1954                         si_pi->cac_weights = cac_weights_chelsea_xt;
1955                         si_pi->dte_data = dte_data_cape_verde;
1956                         break;
1957                 case 0x682F:
1958                         si_pi->cac_weights = cac_weights_chelsea_pro;
1959                         si_pi->dte_data = dte_data_cape_verde;
1960                         break;
1961                 case 0x6820:
1962                         si_pi->cac_weights = cac_weights_heathrow;
1963                         si_pi->dte_data = dte_data_venus_xtx;
1964                         break;
1965                 case 0x6821:
1966                         si_pi->cac_weights = cac_weights_heathrow;
1967                         si_pi->dte_data = dte_data_venus_xt;
1968                         break;
1969                 case 0x6823:
1970                         si_pi->cac_weights = cac_weights_chelsea_pro;
1971                         si_pi->dte_data = dte_data_venus_pro;
1972                         break;
1973                 case 0x682B:
1974                         si_pi->cac_weights = cac_weights_chelsea_pro;
1975                         si_pi->dte_data = dte_data_venus_pro;
1976                         break;
1977                 default:
1978                         si_pi->cac_weights = cac_weights_cape_verde;
1979                         si_pi->dte_data = dte_data_cape_verde;
1980                         break;
1981                 }
1982         } else if (rdev->family == CHIP_OLAND) {
1983                 switch (rdev->pdev->device) {
1984                 case 0x6601:
1985                 case 0x6621:
1986                 case 0x6603:
1987                         si_pi->cac_weights = cac_weights_mars_pro;
1988                         si_pi->lcac_config = lcac_mars_pro;
1989                         si_pi->cac_override = cac_override_oland;
1990                         si_pi->powertune_data = &powertune_data_mars_pro;
1991                         si_pi->dte_data = dte_data_mars_pro;
1992                         update_dte_from_pl2 = true;
1993                         break;
1994                 case 0x6600:
1995                 case 0x6606:
1996                 case 0x6620:
1997                         si_pi->cac_weights = cac_weights_mars_xt;
1998                         si_pi->lcac_config = lcac_mars_pro;
1999                         si_pi->cac_override = cac_override_oland;
2000                         si_pi->powertune_data = &powertune_data_mars_pro;
2001                         si_pi->dte_data = dte_data_mars_pro;
2002                         update_dte_from_pl2 = true;
2003                         break;
2004                 case 0x6611:
2005                         si_pi->cac_weights = cac_weights_oland_pro;
2006                         si_pi->lcac_config = lcac_mars_pro;
2007                         si_pi->cac_override = cac_override_oland;
2008                         si_pi->powertune_data = &powertune_data_mars_pro;
2009                         si_pi->dte_data = dte_data_mars_pro;
2010                         update_dte_from_pl2 = true;
2011                         break;
2012                 case 0x6610:
2013                         si_pi->cac_weights = cac_weights_oland_xt;
2014                         si_pi->lcac_config = lcac_mars_pro;
2015                         si_pi->cac_override = cac_override_oland;
2016                         si_pi->powertune_data = &powertune_data_mars_pro;
2017                         si_pi->dte_data = dte_data_mars_pro;
2018                         update_dte_from_pl2 = true;
2019                         break;
2020                 default:
2021                         si_pi->cac_weights = cac_weights_oland;
2022                         si_pi->lcac_config = lcac_oland;
2023                         si_pi->cac_override = cac_override_oland;
2024                         si_pi->powertune_data = &powertune_data_oland;
2025                         si_pi->dte_data = dte_data_oland;
2026                         break;
2027                 }
2028         } else if (rdev->family == CHIP_HAINAN) {
2029                 si_pi->cac_weights = cac_weights_hainan;
2030                 si_pi->lcac_config = lcac_oland;
2031                 si_pi->cac_override = cac_override_oland;
2032                 si_pi->powertune_data = &powertune_data_hainan;
2033                 si_pi->dte_data = dte_data_sun_xt;
2034                 update_dte_from_pl2 = true;
2035         } else {
2036                 DRM_ERROR("Unknown SI asic revision, failed to initialize PowerTune!\n");
2037                 return;
2038         }
2039
2040         ni_pi->enable_power_containment = false;
2041         ni_pi->enable_cac = false;
2042         ni_pi->enable_sq_ramping = false;
2043         si_pi->enable_dte = false;
2044
2045         if (si_pi->powertune_data->enable_powertune_by_default) {
2046                 ni_pi->enable_power_containment= true;
2047                 ni_pi->enable_cac = true;
2048                 if (si_pi->dte_data.enable_dte_by_default) {
2049                         si_pi->enable_dte = true;
2050                         if (update_dte_from_pl2)
2051                                 si_update_dte_from_pl2(rdev, &si_pi->dte_data);
2052
2053                 }
2054                 ni_pi->enable_sq_ramping = true;
2055         }
2056
2057         ni_pi->driver_calculate_cac_leakage = true;
2058         ni_pi->cac_configuration_required = true;
2059
2060         if (ni_pi->cac_configuration_required) {
2061                 ni_pi->support_cac_long_term_average = true;
2062                 si_pi->dyn_powertune_data.l2_lta_window_size =
2063                         si_pi->powertune_data->l2_lta_window_size_default;
2064                 si_pi->dyn_powertune_data.lts_truncate =
2065                         si_pi->powertune_data->lts_truncate_default;
2066         } else {
2067                 ni_pi->support_cac_long_term_average = false;
2068                 si_pi->dyn_powertune_data.l2_lta_window_size = 0;
2069                 si_pi->dyn_powertune_data.lts_truncate = 0;
2070         }
2071
2072         si_pi->dyn_powertune_data.disable_uvd_powertune = false;
2073 }
2074
2075 static u32 si_get_smc_power_scaling_factor(struct radeon_device *rdev)
2076 {
2077         return 1;
2078 }
2079
2080 static u32 si_calculate_cac_wintime(struct radeon_device *rdev)
2081 {
2082         u32 xclk;
2083         u32 wintime;
2084         u32 cac_window;
2085         u32 cac_window_size;
2086
2087         xclk = radeon_get_xclk(rdev);
2088
2089         if (xclk == 0)
2090                 return 0;
2091
2092         cac_window = RREG32(CG_CAC_CTRL) & CAC_WINDOW_MASK;
2093         cac_window_size = ((cac_window & 0xFFFF0000) >> 16) * (cac_window & 0x0000FFFF);
2094
2095         wintime = (cac_window_size * 100) / xclk;
2096
2097         return wintime;
2098 }
2099
2100 static u32 si_scale_power_for_smc(u32 power_in_watts, u32 scaling_factor)
2101 {
2102         return power_in_watts;
2103 }
2104
2105 static int si_calculate_adjusted_tdp_limits(struct radeon_device *rdev,
2106                                             bool adjust_polarity,
2107                                             u32 tdp_adjustment,
2108                                             u32 *tdp_limit,
2109                                             u32 *near_tdp_limit)
2110 {
2111         u32 adjustment_delta, max_tdp_limit;
2112
2113         if (tdp_adjustment > (u32)rdev->pm.dpm.tdp_od_limit)
2114                 return -EINVAL;
2115
2116         max_tdp_limit = ((100 + 100) * rdev->pm.dpm.tdp_limit) / 100;
2117
2118         if (adjust_polarity) {
2119                 *tdp_limit = ((100 + tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2120                 *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted + (*tdp_limit - rdev->pm.dpm.tdp_limit);
2121         } else {
2122                 *tdp_limit = ((100 - tdp_adjustment) * rdev->pm.dpm.tdp_limit) / 100;
2123                 adjustment_delta  = rdev->pm.dpm.tdp_limit - *tdp_limit;
2124                 if (adjustment_delta < rdev->pm.dpm.near_tdp_limit_adjusted)
2125                         *near_tdp_limit = rdev->pm.dpm.near_tdp_limit_adjusted - adjustment_delta;
2126                 else
2127                         *near_tdp_limit = 0;
2128         }
2129
2130         if ((*tdp_limit <= 0) || (*tdp_limit > max_tdp_limit))
2131                 return -EINVAL;
2132         if ((*near_tdp_limit <= 0) || (*near_tdp_limit > *tdp_limit))
2133                 return -EINVAL;
2134
2135         return 0;
2136 }
2137
2138 static int si_populate_smc_tdp_limits(struct radeon_device *rdev,
2139                                       struct radeon_ps *radeon_state)
2140 {
2141         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2142         struct si_power_info *si_pi = si_get_pi(rdev);
2143
2144         if (ni_pi->enable_power_containment) {
2145                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2146                 PP_SIslands_PAPMParameters *papm_parm;
2147                 struct radeon_ppm_table *ppm = rdev->pm.dpm.dyn_state.ppm_table;
2148                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2149                 u32 tdp_limit;
2150                 u32 near_tdp_limit;
2151                 int ret;
2152
2153                 if (scaling_factor == 0)
2154                         return -EINVAL;
2155
2156                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2157
2158                 ret = si_calculate_adjusted_tdp_limits(rdev,
2159                                                        false, /* ??? */
2160                                                        rdev->pm.dpm.tdp_adjustment,
2161                                                        &tdp_limit,
2162                                                        &near_tdp_limit);
2163                 if (ret)
2164                         return ret;
2165
2166                 smc_table->dpm2Params.TDPLimit =
2167                         cpu_to_be32(si_scale_power_for_smc(tdp_limit, scaling_factor) * 1000);
2168                 smc_table->dpm2Params.NearTDPLimit =
2169                         cpu_to_be32(si_scale_power_for_smc(near_tdp_limit, scaling_factor) * 1000);
2170                 smc_table->dpm2Params.SafePowerLimit =
2171                         cpu_to_be32(si_scale_power_for_smc((near_tdp_limit * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2172
2173                 ret = si_copy_bytes_to_smc(rdev,
2174                                            (si_pi->state_table_start + offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2175                                                  offsetof(PP_SIslands_DPM2Parameters, TDPLimit)),
2176                                            (u8 *)(&(smc_table->dpm2Params.TDPLimit)),
2177                                            sizeof(u32) * 3,
2178                                            si_pi->sram_end);
2179                 if (ret)
2180                         return ret;
2181
2182                 if (si_pi->enable_ppm) {
2183                         papm_parm = &si_pi->papm_parm;
2184                         memset(papm_parm, 0, sizeof(PP_SIslands_PAPMParameters));
2185                         papm_parm->NearTDPLimitTherm = cpu_to_be32(ppm->dgpu_tdp);
2186                         papm_parm->dGPU_T_Limit = cpu_to_be32(ppm->tj_max);
2187                         papm_parm->dGPU_T_Warning = cpu_to_be32(95);
2188                         papm_parm->dGPU_T_Hysteresis = cpu_to_be32(5);
2189                         papm_parm->PlatformPowerLimit = 0xffffffff;
2190                         papm_parm->NearTDPLimitPAPM = 0xffffffff;
2191
2192                         ret = si_copy_bytes_to_smc(rdev, si_pi->papm_cfg_table_start,
2193                                                    (u8 *)papm_parm,
2194                                                    sizeof(PP_SIslands_PAPMParameters),
2195                                                    si_pi->sram_end);
2196                         if (ret)
2197                                 return ret;
2198                 }
2199         }
2200         return 0;
2201 }
2202
2203 static int si_populate_smc_tdp_limits_2(struct radeon_device *rdev,
2204                                         struct radeon_ps *radeon_state)
2205 {
2206         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2207         struct si_power_info *si_pi = si_get_pi(rdev);
2208
2209         if (ni_pi->enable_power_containment) {
2210                 SISLANDS_SMC_STATETABLE *smc_table = &si_pi->smc_statetable;
2211                 u32 scaling_factor = si_get_smc_power_scaling_factor(rdev);
2212                 int ret;
2213
2214                 memset(smc_table, 0, sizeof(SISLANDS_SMC_STATETABLE));
2215
2216                 smc_table->dpm2Params.NearTDPLimit =
2217                         cpu_to_be32(si_scale_power_for_smc(rdev->pm.dpm.near_tdp_limit_adjusted, scaling_factor) * 1000);
2218                 smc_table->dpm2Params.SafePowerLimit =
2219                         cpu_to_be32(si_scale_power_for_smc((rdev->pm.dpm.near_tdp_limit_adjusted * SISLANDS_DPM2_TDP_SAFE_LIMIT_PERCENT) / 100, scaling_factor) * 1000);
2220
2221                 ret = si_copy_bytes_to_smc(rdev,
2222                                            (si_pi->state_table_start +
2223                                             offsetof(SISLANDS_SMC_STATETABLE, dpm2Params) +
2224                                             offsetof(PP_SIslands_DPM2Parameters, NearTDPLimit)),
2225                                            (u8 *)(&(smc_table->dpm2Params.NearTDPLimit)),
2226                                            sizeof(u32) * 2,
2227                                            si_pi->sram_end);
2228                 if (ret)
2229                         return ret;
2230         }
2231
2232         return 0;
2233 }
2234
2235 static u16 si_calculate_power_efficiency_ratio(struct radeon_device *rdev,
2236                                                const u16 prev_std_vddc,
2237                                                const u16 curr_std_vddc)
2238 {
2239         u64 margin = (u64)SISLANDS_DPM2_PWREFFICIENCYRATIO_MARGIN;
2240         u64 prev_vddc = (u64)prev_std_vddc;
2241         u64 curr_vddc = (u64)curr_std_vddc;
2242         u64 pwr_efficiency_ratio, n, d;
2243
2244         if ((prev_vddc == 0) || (curr_vddc == 0))
2245                 return 0;
2246
2247         n = div64_u64((u64)1024 * curr_vddc * curr_vddc * ((u64)1000 + margin), (u64)1000);
2248         d = prev_vddc * prev_vddc;
2249         pwr_efficiency_ratio = div64_u64(n, d);
2250
2251         if (pwr_efficiency_ratio > (u64)0xFFFF)
2252                 return 0;
2253
2254         return (u16)pwr_efficiency_ratio;
2255 }
2256
2257 static bool si_should_disable_uvd_powertune(struct radeon_device *rdev,
2258                                             struct radeon_ps *radeon_state)
2259 {
2260         struct si_power_info *si_pi = si_get_pi(rdev);
2261
2262         if (si_pi->dyn_powertune_data.disable_uvd_powertune &&
2263             radeon_state->vclk && radeon_state->dclk)
2264                 return true;
2265
2266         return false;
2267 }
2268
2269 static int si_populate_power_containment_values(struct radeon_device *rdev,
2270                                                 struct radeon_ps *radeon_state,
2271                                                 SISLANDS_SMC_SWSTATE *smc_state)
2272 {
2273         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
2274         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2275         struct ni_ps *state = ni_get_ps(radeon_state);
2276         SISLANDS_SMC_VOLTAGE_VALUE vddc;
2277         u32 prev_sclk;
2278         u32 max_sclk;
2279         u32 min_sclk;
2280         u16 prev_std_vddc;
2281         u16 curr_std_vddc;
2282         int i;
2283         u16 pwr_efficiency_ratio;
2284         u8 max_ps_percent;
2285         bool disable_uvd_power_tune;
2286         int ret;
2287
2288         if (ni_pi->enable_power_containment == false)
2289                 return 0;
2290
2291         if (state->performance_level_count == 0)
2292                 return -EINVAL;
2293
2294         if (smc_state->levelCount != state->performance_level_count)
2295                 return -EINVAL;
2296
2297         disable_uvd_power_tune = si_should_disable_uvd_powertune(rdev, radeon_state);
2298
2299         smc_state->levels[0].dpm2.MaxPS = 0;
2300         smc_state->levels[0].dpm2.NearTDPDec = 0;
2301         smc_state->levels[0].dpm2.AboveSafeInc = 0;
2302         smc_state->levels[0].dpm2.BelowSafeInc = 0;
2303         smc_state->levels[0].dpm2.PwrEfficiencyRatio = 0;
2304
2305         for (i = 1; i < state->performance_level_count; i++) {
2306                 prev_sclk = state->performance_levels[i-1].sclk;
2307                 max_sclk  = state->performance_levels[i].sclk;
2308                 if (i == 1)
2309                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_M;
2310                 else
2311                         max_ps_percent = SISLANDS_DPM2_MAXPS_PERCENT_H;
2312
2313                 if (prev_sclk > max_sclk)
2314                         return -EINVAL;
2315
2316                 if ((max_ps_percent == 0) ||
2317                     (prev_sclk == max_sclk) ||
2318                     disable_uvd_power_tune) {
2319                         min_sclk = max_sclk;
2320                 } else if (i == 1) {
2321                         min_sclk = prev_sclk;
2322                 } else {
2323                         min_sclk = (prev_sclk * (u32)max_ps_percent) / 100;
2324                 }
2325
2326                 if (min_sclk < state->performance_levels[0].sclk)
2327                         min_sclk = state->performance_levels[0].sclk;
2328
2329                 if (min_sclk == 0)
2330                         return -EINVAL;
2331
2332                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2333                                                 state->performance_levels[i-1].vddc, &vddc);
2334                 if (ret)
2335                         return ret;
2336
2337                 ret = si_get_std_voltage_value(rdev, &vddc, &prev_std_vddc);
2338                 if (ret)
2339                         return ret;
2340
2341                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
2342                                                 state->performance_levels[i].vddc, &vddc);
2343                 if (ret)
2344                         return ret;
2345
2346                 ret = si_get_std_voltage_value(rdev, &vddc, &curr_std_vddc);
2347                 if (ret)
2348                         return ret;
2349
2350                 pwr_efficiency_ratio = si_calculate_power_efficiency_ratio(rdev,
2351                                                                            prev_std_vddc, curr_std_vddc);
2352
2353                 smc_state->levels[i].dpm2.MaxPS = (u8)((SISLANDS_DPM2_MAX_PULSE_SKIP * (max_sclk - min_sclk)) / max_sclk);
2354                 smc_state->levels[i].dpm2.NearTDPDec = SISLANDS_DPM2_NEAR_TDP_DEC;
2355                 smc_state->levels[i].dpm2.AboveSafeInc = SISLANDS_DPM2_ABOVE_SAFE_INC;
2356                 smc_state->levels[i].dpm2.BelowSafeInc = SISLANDS_DPM2_BELOW_SAFE_INC;
2357                 smc_state->levels[i].dpm2.PwrEfficiencyRatio = cpu_to_be16(pwr_efficiency_ratio);
2358         }
2359
2360         return 0;
2361 }
2362
2363 static int si_populate_sq_ramping_values(struct radeon_device *rdev,
2364                                          struct radeon_ps *radeon_state,
2365                                          SISLANDS_SMC_SWSTATE *smc_state)
2366 {
2367         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2368         struct ni_ps *state = ni_get_ps(radeon_state);
2369         u32 sq_power_throttle, sq_power_throttle2;
2370         bool enable_sq_ramping = ni_pi->enable_sq_ramping;
2371         int i;
2372
2373         if (state->performance_level_count == 0)
2374                 return -EINVAL;
2375
2376         if (smc_state->levelCount != state->performance_level_count)
2377                 return -EINVAL;
2378
2379         if (rdev->pm.dpm.sq_ramping_threshold == 0)
2380                 return -EINVAL;
2381
2382         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER > (MAX_POWER_MASK >> MAX_POWER_SHIFT))
2383                 enable_sq_ramping = false;
2384
2385         if (SISLANDS_DPM2_SQ_RAMP_MIN_POWER > (MIN_POWER_MASK >> MIN_POWER_SHIFT))
2386                 enable_sq_ramping = false;
2387
2388         if (SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA > (MAX_POWER_DELTA_MASK >> MAX_POWER_DELTA_SHIFT))
2389                 enable_sq_ramping = false;
2390
2391         if (SISLANDS_DPM2_SQ_RAMP_STI_SIZE > (STI_SIZE_MASK >> STI_SIZE_SHIFT))
2392                 enable_sq_ramping = false;
2393
2394         if (NISLANDS_DPM2_SQ_RAMP_LTI_RATIO <= (LTI_RATIO_MASK >> LTI_RATIO_SHIFT))
2395                 enable_sq_ramping = false;
2396
2397         for (i = 0; i < state->performance_level_count; i++) {
2398                 sq_power_throttle = 0;
2399                 sq_power_throttle2 = 0;
2400
2401                 if ((state->performance_levels[i].sclk >= rdev->pm.dpm.sq_ramping_threshold) &&
2402                     enable_sq_ramping) {
2403                         sq_power_throttle |= MAX_POWER(SISLANDS_DPM2_SQ_RAMP_MAX_POWER);
2404                         sq_power_throttle |= MIN_POWER(SISLANDS_DPM2_SQ_RAMP_MIN_POWER);
2405                         sq_power_throttle2 |= MAX_POWER_DELTA(SISLANDS_DPM2_SQ_RAMP_MAX_POWER_DELTA);
2406                         sq_power_throttle2 |= STI_SIZE(SISLANDS_DPM2_SQ_RAMP_STI_SIZE);
2407                         sq_power_throttle2 |= LTI_RATIO(SISLANDS_DPM2_SQ_RAMP_LTI_RATIO);
2408                 } else {
2409                         sq_power_throttle |= MAX_POWER_MASK | MIN_POWER_MASK;
2410                         sq_power_throttle2 |= MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
2411                 }
2412
2413                 smc_state->levels[i].SQPowerThrottle = cpu_to_be32(sq_power_throttle);
2414                 smc_state->levels[i].SQPowerThrottle_2 = cpu_to_be32(sq_power_throttle2);
2415         }
2416
2417         return 0;
2418 }
2419
2420 static int si_enable_power_containment(struct radeon_device *rdev,
2421                                        struct radeon_ps *radeon_new_state,
2422                                        bool enable)
2423 {
2424         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2425         PPSMC_Result smc_result;
2426         int ret = 0;
2427
2428         if (ni_pi->enable_power_containment) {
2429                 if (enable) {
2430                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2431                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingActive);
2432                                 if (smc_result != PPSMC_Result_OK) {
2433                                         ret = -EINVAL;
2434                                         ni_pi->pc_enabled = false;
2435                                 } else {
2436                                         ni_pi->pc_enabled = true;
2437                                 }
2438                         }
2439                 } else {
2440                         smc_result = si_send_msg_to_smc(rdev, PPSMC_TDPClampingInactive);
2441                         if (smc_result != PPSMC_Result_OK)
2442                                 ret = -EINVAL;
2443                         ni_pi->pc_enabled = false;
2444                 }
2445         }
2446
2447         return ret;
2448 }
2449
2450 static int si_initialize_smc_dte_tables(struct radeon_device *rdev)
2451 {
2452         struct si_power_info *si_pi = si_get_pi(rdev);
2453         int ret = 0;
2454         struct si_dte_data *dte_data = &si_pi->dte_data;
2455         Smc_SIslands_DTE_Configuration *dte_tables = NULL;
2456         u32 table_size;
2457         u8 tdep_count;
2458         u32 i;
2459
2460         if (dte_data == NULL)
2461                 si_pi->enable_dte = false;
2462
2463         if (si_pi->enable_dte == false)
2464                 return 0;
2465
2466         if (dte_data->k <= 0)
2467                 return -EINVAL;
2468
2469         dte_tables = kzalloc(sizeof(Smc_SIslands_DTE_Configuration), GFP_KERNEL);
2470         if (dte_tables == NULL) {
2471                 si_pi->enable_dte = false;
2472                 return -ENOMEM;
2473         }
2474
2475         table_size = dte_data->k;
2476
2477         if (table_size > SMC_SISLANDS_DTE_MAX_FILTER_STAGES)
2478                 table_size = SMC_SISLANDS_DTE_MAX_FILTER_STAGES;
2479
2480         tdep_count = dte_data->tdep_count;
2481         if (tdep_count > SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE)
2482                 tdep_count = SMC_SISLANDS_DTE_MAX_TEMPERATURE_DEPENDENT_ARRAY_SIZE;
2483
2484         dte_tables->K = cpu_to_be32(table_size);
2485         dte_tables->T0 = cpu_to_be32(dte_data->t0);
2486         dte_tables->MaxT = cpu_to_be32(dte_data->max_t);
2487         dte_tables->WindowSize = dte_data->window_size;
2488         dte_tables->temp_select = dte_data->temp_select;
2489         dte_tables->DTE_mode = dte_data->dte_mode;
2490         dte_tables->Tthreshold = cpu_to_be32(dte_data->t_threshold);
2491
2492         if (tdep_count > 0)
2493                 table_size--;
2494
2495         for (i = 0; i < table_size; i++) {
2496                 dte_tables->tau[i] = cpu_to_be32(dte_data->tau[i]);
2497                 dte_tables->R[i]   = cpu_to_be32(dte_data->r[i]);
2498         }
2499
2500         dte_tables->Tdep_count = tdep_count;
2501
2502         for (i = 0; i < (u32)tdep_count; i++) {
2503                 dte_tables->T_limits[i] = dte_data->t_limits[i];
2504                 dte_tables->Tdep_tau[i] = cpu_to_be32(dte_data->tdep_tau[i]);
2505                 dte_tables->Tdep_R[i] = cpu_to_be32(dte_data->tdep_r[i]);
2506         }
2507
2508         ret = si_copy_bytes_to_smc(rdev, si_pi->dte_table_start, (u8 *)dte_tables,
2509                                    sizeof(Smc_SIslands_DTE_Configuration), si_pi->sram_end);
2510         kfree(dte_tables);
2511
2512         return ret;
2513 }
2514
2515 static int si_get_cac_std_voltage_max_min(struct radeon_device *rdev,
2516                                           u16 *max, u16 *min)
2517 {
2518         struct si_power_info *si_pi = si_get_pi(rdev);
2519         struct radeon_cac_leakage_table *table =
2520                 &rdev->pm.dpm.dyn_state.cac_leakage_table;
2521         u32 i;
2522         u32 v0_loadline;
2523
2524
2525         if (table == NULL)
2526                 return -EINVAL;
2527
2528         *max = 0;
2529         *min = 0xFFFF;
2530
2531         for (i = 0; i < table->count; i++) {
2532                 if (table->entries[i].vddc > *max)
2533                         *max = table->entries[i].vddc;
2534                 if (table->entries[i].vddc < *min)
2535                         *min = table->entries[i].vddc;
2536         }
2537
2538         if (si_pi->powertune_data->lkge_lut_v0_percent > 100)
2539                 return -EINVAL;
2540
2541         v0_loadline = (*min) * (100 - si_pi->powertune_data->lkge_lut_v0_percent) / 100;
2542
2543         if (v0_loadline > 0xFFFFUL)
2544                 return -EINVAL;
2545
2546         *min = (u16)v0_loadline;
2547
2548         if ((*min > *max) || (*max == 0) || (*min == 0))
2549                 return -EINVAL;
2550
2551         return 0;
2552 }
2553
2554 static u16 si_get_cac_std_voltage_step(u16 max, u16 min)
2555 {
2556         return ((max - min) + (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1)) /
2557                 SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES;
2558 }
2559
2560 static int si_init_dte_leakage_table(struct radeon_device *rdev,
2561                                      PP_SIslands_CacConfig *cac_tables,
2562                                      u16 vddc_max, u16 vddc_min, u16 vddc_step,
2563                                      u16 t0, u16 t_step)
2564 {
2565         struct si_power_info *si_pi = si_get_pi(rdev);
2566         u32 leakage;
2567         unsigned int i, j;
2568         s32 t;
2569         u32 smc_leakage;
2570         u32 scaling_factor;
2571         u16 voltage;
2572
2573         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2574
2575         for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++) {
2576                 t = (1000 * (i * t_step + t0));
2577
2578                 for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2579                         voltage = vddc_max - (vddc_step * j);
2580
2581                         si_calculate_leakage_for_v_and_t(rdev,
2582                                                          &si_pi->powertune_data->leakage_coefficients,
2583                                                          voltage,
2584                                                          t,
2585                                                          si_pi->dyn_powertune_data.cac_leakage,
2586                                                          &leakage);
2587
2588                         smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2589
2590                         if (smc_leakage > 0xFFFF)
2591                                 smc_leakage = 0xFFFF;
2592
2593                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2594                                 cpu_to_be16((u16)smc_leakage);
2595                 }
2596         }
2597         return 0;
2598 }
2599
2600 static int si_init_simplified_leakage_table(struct radeon_device *rdev,
2601                                             PP_SIslands_CacConfig *cac_tables,
2602                                             u16 vddc_max, u16 vddc_min, u16 vddc_step)
2603 {
2604         struct si_power_info *si_pi = si_get_pi(rdev);
2605         u32 leakage;
2606         unsigned int i, j;
2607         u32 smc_leakage;
2608         u32 scaling_factor;
2609         u16 voltage;
2610
2611         scaling_factor = si_get_smc_power_scaling_factor(rdev);
2612
2613         for (j = 0; j < SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES; j++) {
2614                 voltage = vddc_max - (vddc_step * j);
2615
2616                 si_calculate_leakage_for_v(rdev,
2617                                            &si_pi->powertune_data->leakage_coefficients,
2618                                            si_pi->powertune_data->fixed_kt,
2619                                            voltage,
2620                                            si_pi->dyn_powertune_data.cac_leakage,
2621                                            &leakage);
2622
2623                 smc_leakage = si_scale_power_for_smc(leakage, scaling_factor) / 4;
2624
2625                 if (smc_leakage > 0xFFFF)
2626                         smc_leakage = 0xFFFF;
2627
2628                 for (i = 0; i < SMC_SISLANDS_LKGE_LUT_NUM_OF_TEMP_ENTRIES ; i++)
2629                         cac_tables->cac_lkge_lut[i][SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES-1-j] =
2630                                 cpu_to_be16((u16)smc_leakage);
2631         }
2632         return 0;
2633 }
2634
2635 static int si_initialize_smc_cac_tables(struct radeon_device *rdev)
2636 {
2637         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2638         struct si_power_info *si_pi = si_get_pi(rdev);
2639         PP_SIslands_CacConfig *cac_tables = NULL;
2640         u16 vddc_max, vddc_min, vddc_step;
2641         u16 t0, t_step;
2642         u32 load_line_slope, reg;
2643         int ret = 0;
2644         u32 ticks_per_us = radeon_get_xclk(rdev) / 100;
2645
2646         if (ni_pi->enable_cac == false)
2647                 return 0;
2648
2649         cac_tables = kzalloc(sizeof(PP_SIslands_CacConfig), GFP_KERNEL);
2650         if (!cac_tables)
2651                 return -ENOMEM;
2652
2653         reg = RREG32(CG_CAC_CTRL) & ~CAC_WINDOW_MASK;
2654         reg |= CAC_WINDOW(si_pi->powertune_data->cac_window);
2655         WREG32(CG_CAC_CTRL, reg);
2656
2657         si_pi->dyn_powertune_data.cac_leakage = rdev->pm.dpm.cac_leakage;
2658         si_pi->dyn_powertune_data.dc_pwr_value =
2659                 si_pi->powertune_data->dc_cac[NISLANDS_DCCAC_LEVEL_0];
2660         si_pi->dyn_powertune_data.wintime = si_calculate_cac_wintime(rdev);
2661         si_pi->dyn_powertune_data.shift_n = si_pi->powertune_data->shift_n_default;
2662
2663         si_pi->dyn_powertune_data.leakage_minimum_temperature = 80 * 1000;
2664
2665         ret = si_get_cac_std_voltage_max_min(rdev, &vddc_max, &vddc_min);
2666         if (ret)
2667                 goto done_free;
2668
2669         vddc_step = si_get_cac_std_voltage_step(vddc_max, vddc_min);
2670         vddc_min = vddc_max - (vddc_step * (SMC_SISLANDS_LKGE_LUT_NUM_OF_VOLT_ENTRIES - 1));
2671         t_step = 4;
2672         t0 = 60;
2673
2674         if (si_pi->enable_dte || ni_pi->driver_calculate_cac_leakage)
2675                 ret = si_init_dte_leakage_table(rdev, cac_tables,
2676                                                 vddc_max, vddc_min, vddc_step,
2677                                                 t0, t_step);
2678         else
2679                 ret = si_init_simplified_leakage_table(rdev, cac_tables,
2680                                                        vddc_max, vddc_min, vddc_step);
2681         if (ret)
2682                 goto done_free;
2683
2684         load_line_slope = ((u32)rdev->pm.dpm.load_line_slope << SMC_SISLANDS_SCALE_R) / 100;
2685
2686         cac_tables->l2numWin_TDP = cpu_to_be32(si_pi->dyn_powertune_data.l2_lta_window_size);
2687         cac_tables->lts_truncate_n = si_pi->dyn_powertune_data.lts_truncate;
2688         cac_tables->SHIFT_N = si_pi->dyn_powertune_data.shift_n;
2689         cac_tables->lkge_lut_V0 = cpu_to_be32((u32)vddc_min);
2690         cac_tables->lkge_lut_Vstep = cpu_to_be32((u32)vddc_step);
2691         cac_tables->R_LL = cpu_to_be32(load_line_slope);
2692         cac_tables->WinTime = cpu_to_be32(si_pi->dyn_powertune_data.wintime);
2693         cac_tables->calculation_repeats = cpu_to_be32(2);
2694         cac_tables->dc_cac = cpu_to_be32(0);
2695         cac_tables->log2_PG_LKG_SCALE = 12;
2696         cac_tables->cac_temp = si_pi->powertune_data->operating_temp;
2697         cac_tables->lkge_lut_T0 = cpu_to_be32((u32)t0);
2698         cac_tables->lkge_lut_Tstep = cpu_to_be32((u32)t_step);
2699
2700         ret = si_copy_bytes_to_smc(rdev, si_pi->cac_table_start, (u8 *)cac_tables,
2701                                    sizeof(PP_SIslands_CacConfig), si_pi->sram_end);
2702
2703         if (ret)
2704                 goto done_free;
2705
2706         ret = si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ticks_per_us, ticks_per_us);
2707
2708 done_free:
2709         if (ret) {
2710                 ni_pi->enable_cac = false;
2711                 ni_pi->enable_power_containment = false;
2712         }
2713
2714         kfree(cac_tables);
2715
2716         return 0;
2717 }
2718
2719 static int si_program_cac_config_registers(struct radeon_device *rdev,
2720                                            const struct si_cac_config_reg *cac_config_regs)
2721 {
2722         const struct si_cac_config_reg *config_regs = cac_config_regs;
2723         u32 data = 0, offset;
2724
2725         if (!config_regs)
2726                 return -EINVAL;
2727
2728         while (config_regs->offset != 0xFFFFFFFF) {
2729                 switch (config_regs->type) {
2730                 case SISLANDS_CACCONFIG_CGIND:
2731                         offset = SMC_CG_IND_START + config_regs->offset;
2732                         if (offset < SMC_CG_IND_END)
2733                                 data = RREG32_SMC(offset);
2734                         break;
2735                 default:
2736                         data = RREG32(config_regs->offset << 2);
2737                         break;
2738                 }
2739
2740                 data &= ~config_regs->mask;
2741                 data |= ((config_regs->value << config_regs->shift) & config_regs->mask);
2742
2743                 switch (config_regs->type) {
2744                 case SISLANDS_CACCONFIG_CGIND:
2745                         offset = SMC_CG_IND_START + config_regs->offset;
2746                         if (offset < SMC_CG_IND_END)
2747                                 WREG32_SMC(offset, data);
2748                         break;
2749                 default:
2750                         WREG32(config_regs->offset << 2, data);
2751                         break;
2752                 }
2753                 config_regs++;
2754         }
2755         return 0;
2756 }
2757
2758 static int si_initialize_hardware_cac_manager(struct radeon_device *rdev)
2759 {
2760         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2761         struct si_power_info *si_pi = si_get_pi(rdev);
2762         int ret;
2763
2764         if ((ni_pi->enable_cac == false) ||
2765             (ni_pi->cac_configuration_required == false))
2766                 return 0;
2767
2768         ret = si_program_cac_config_registers(rdev, si_pi->lcac_config);
2769         if (ret)
2770                 return ret;
2771         ret = si_program_cac_config_registers(rdev, si_pi->cac_override);
2772         if (ret)
2773                 return ret;
2774         ret = si_program_cac_config_registers(rdev, si_pi->cac_weights);
2775         if (ret)
2776                 return ret;
2777
2778         return 0;
2779 }
2780
2781 static int si_enable_smc_cac(struct radeon_device *rdev,
2782                              struct radeon_ps *radeon_new_state,
2783                              bool enable)
2784 {
2785         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2786         struct si_power_info *si_pi = si_get_pi(rdev);
2787         PPSMC_Result smc_result;
2788         int ret = 0;
2789
2790         if (ni_pi->enable_cac) {
2791                 if (enable) {
2792                         if (!si_should_disable_uvd_powertune(rdev, radeon_new_state)) {
2793                                 if (ni_pi->support_cac_long_term_average) {
2794                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgEnable);
2795                                         if (smc_result != PPSMC_Result_OK)
2796                                                 ni_pi->support_cac_long_term_average = false;
2797                                 }
2798
2799                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableCac);
2800                                 if (smc_result != PPSMC_Result_OK) {
2801                                         ret = -EINVAL;
2802                                         ni_pi->cac_enabled = false;
2803                                 } else {
2804                                         ni_pi->cac_enabled = true;
2805                                 }
2806
2807                                 if (si_pi->enable_dte) {
2808                                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableDTE);
2809                                         if (smc_result != PPSMC_Result_OK)
2810                                                 ret = -EINVAL;
2811                                 }
2812                         }
2813                 } else if (ni_pi->cac_enabled) {
2814                         if (si_pi->enable_dte)
2815                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableDTE);
2816
2817                         smc_result = si_send_msg_to_smc(rdev, PPSMC_MSG_DisableCac);
2818
2819                         ni_pi->cac_enabled = false;
2820
2821                         if (ni_pi->support_cac_long_term_average)
2822                                 smc_result = si_send_msg_to_smc(rdev, PPSMC_CACLongTermAvgDisable);
2823                 }
2824         }
2825         return ret;
2826 }
2827
2828 static int si_init_smc_spll_table(struct radeon_device *rdev)
2829 {
2830         struct ni_power_info *ni_pi = ni_get_pi(rdev);
2831         struct si_power_info *si_pi = si_get_pi(rdev);
2832         SMC_SISLANDS_SPLL_DIV_TABLE *spll_table;
2833         SISLANDS_SMC_SCLK_VALUE sclk_params;
2834         u32 fb_div, p_div;
2835         u32 clk_s, clk_v;
2836         u32 sclk = 0;
2837         int ret = 0;
2838         u32 tmp;
2839         int i;
2840
2841         if (si_pi->spll_table_start == 0)
2842                 return -EINVAL;
2843
2844         spll_table = kzalloc(sizeof(SMC_SISLANDS_SPLL_DIV_TABLE), GFP_KERNEL);
2845         if (spll_table == NULL)
2846                 return -ENOMEM;
2847
2848         for (i = 0; i < 256; i++) {
2849                 ret = si_calculate_sclk_params(rdev, sclk, &sclk_params);
2850                 if (ret)
2851                         break;
2852
2853                 p_div = (sclk_params.vCG_SPLL_FUNC_CNTL & SPLL_PDIV_A_MASK) >> SPLL_PDIV_A_SHIFT;
2854                 fb_div = (sclk_params.vCG_SPLL_FUNC_CNTL_3 & SPLL_FB_DIV_MASK) >> SPLL_FB_DIV_SHIFT;
2855                 clk_s = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM & CLK_S_MASK) >> CLK_S_SHIFT;
2856                 clk_v = (sclk_params.vCG_SPLL_SPREAD_SPECTRUM_2 & CLK_V_MASK) >> CLK_V_SHIFT;
2857
2858                 fb_div &= ~0x00001FFF;
2859                 fb_div >>= 1;
2860                 clk_v >>= 6;
2861
2862                 if (p_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT))
2863                         ret = -EINVAL;
2864                 if (fb_div & ~(SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT))
2865                         ret = -EINVAL;
2866                 if (clk_s & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT))
2867                         ret = -EINVAL;
2868                 if (clk_v & ~(SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK >> SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT))
2869                         ret = -EINVAL;
2870
2871                 if (ret)
2872                         break;
2873
2874                 tmp = ((fb_div << SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_FBDIV_MASK) |
2875                         ((p_div << SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_PDIV_MASK);
2876                 spll_table->freq[i] = cpu_to_be32(tmp);
2877
2878                 tmp = ((clk_v << SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKV_MASK) |
2879                         ((clk_s << SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_SHIFT) & SMC_SISLANDS_SPLL_DIV_TABLE_CLKS_MASK);
2880                 spll_table->ss[i] = cpu_to_be32(tmp);
2881
2882                 sclk += 512;
2883         }
2884
2885
2886         if (!ret)
2887                 ret = si_copy_bytes_to_smc(rdev, si_pi->spll_table_start,
2888                                            (u8 *)spll_table, sizeof(SMC_SISLANDS_SPLL_DIV_TABLE),
2889                                            si_pi->sram_end);
2890
2891         if (ret)
2892                 ni_pi->enable_power_containment = false;
2893
2894         kfree(spll_table);
2895
2896         return ret;
2897 }
2898
2899 static void si_apply_state_adjust_rules(struct radeon_device *rdev,
2900                                         struct radeon_ps *rps)
2901 {
2902         struct ni_ps *ps = ni_get_ps(rps);
2903         struct radeon_clock_and_voltage_limits *max_limits;
2904         bool disable_mclk_switching;
2905         u32 mclk, sclk;
2906         u16 vddc, vddci;
2907         int i;
2908
2909         if ((rdev->pm.dpm.new_active_crtc_count > 1) ||
2910             ni_dpm_vblank_too_short(rdev))
2911                 disable_mclk_switching = true;
2912         else
2913                 disable_mclk_switching = false;
2914
2915         if (rdev->pm.dpm.ac_power)
2916                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac;
2917         else
2918                 max_limits = &rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc;
2919
2920         for (i = ps->performance_level_count - 2; i >= 0; i--) {
2921                 if (ps->performance_levels[i].vddc > ps->performance_levels[i+1].vddc)
2922                         ps->performance_levels[i].vddc = ps->performance_levels[i+1].vddc;
2923         }
2924         if (rdev->pm.dpm.ac_power == false) {
2925                 for (i = 0; i < ps->performance_level_count; i++) {
2926                         if (ps->performance_levels[i].mclk > max_limits->mclk)
2927                                 ps->performance_levels[i].mclk = max_limits->mclk;
2928                         if (ps->performance_levels[i].sclk > max_limits->sclk)
2929                                 ps->performance_levels[i].sclk = max_limits->sclk;
2930                         if (ps->performance_levels[i].vddc > max_limits->vddc)
2931                                 ps->performance_levels[i].vddc = max_limits->vddc;
2932                         if (ps->performance_levels[i].vddci > max_limits->vddci)
2933                                 ps->performance_levels[i].vddci = max_limits->vddci;
2934                 }
2935         }
2936
2937         /* XXX validate the min clocks required for display */
2938
2939         if (disable_mclk_switching) {
2940                 mclk  = ps->performance_levels[ps->performance_level_count - 1].mclk;
2941                 sclk = ps->performance_levels[0].sclk;
2942                 vddc = ps->performance_levels[0].vddc;
2943                 vddci = ps->performance_levels[ps->performance_level_count - 1].vddci;
2944         } else {
2945                 sclk = ps->performance_levels[0].sclk;
2946                 mclk = ps->performance_levels[0].mclk;
2947                 vddc = ps->performance_levels[0].vddc;
2948                 vddci = ps->performance_levels[0].vddci;
2949         }
2950
2951         /* adjusted low state */
2952         ps->performance_levels[0].sclk = sclk;
2953         ps->performance_levels[0].mclk = mclk;
2954         ps->performance_levels[0].vddc = vddc;
2955         ps->performance_levels[0].vddci = vddci;
2956
2957         for (i = 1; i < ps->performance_level_count; i++) {
2958                 if (ps->performance_levels[i].sclk < ps->performance_levels[i - 1].sclk)
2959                         ps->performance_levels[i].sclk = ps->performance_levels[i - 1].sclk;
2960                 if (ps->performance_levels[i].vddc < ps->performance_levels[i - 1].vddc)
2961                         ps->performance_levels[i].vddc = ps->performance_levels[i - 1].vddc;
2962         }
2963
2964         if (disable_mclk_switching) {
2965                 mclk = ps->performance_levels[0].mclk;
2966                 for (i = 1; i < ps->performance_level_count; i++) {
2967                         if (mclk < ps->performance_levels[i].mclk)
2968                                 mclk = ps->performance_levels[i].mclk;
2969                 }
2970                 for (i = 0; i < ps->performance_level_count; i++) {
2971                         ps->performance_levels[i].mclk = mclk;
2972                         ps->performance_levels[i].vddci = vddci;
2973                 }
2974         } else {
2975                 for (i = 1; i < ps->performance_level_count; i++) {
2976                         if (ps->performance_levels[i].mclk < ps->performance_levels[i - 1].mclk)
2977                                 ps->performance_levels[i].mclk = ps->performance_levels[i - 1].mclk;
2978                         if (ps->performance_levels[i].vddci < ps->performance_levels[i - 1].vddci)
2979                                 ps->performance_levels[i].vddci = ps->performance_levels[i - 1].vddci;
2980                 }
2981         }
2982
2983         for (i = 0; i < ps->performance_level_count; i++)
2984                 btc_adjust_clock_combinations(rdev, max_limits,
2985                                               &ps->performance_levels[i]);
2986
2987         for (i = 0; i < ps->performance_level_count; i++) {
2988                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk,
2989                                                    ps->performance_levels[i].sclk,
2990                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2991                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk,
2992                                                    ps->performance_levels[i].mclk,
2993                                                    max_limits->vddci, &ps->performance_levels[i].vddci);
2994                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk,
2995                                                    ps->performance_levels[i].mclk,
2996                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
2997                 btc_apply_voltage_dependency_rules(&rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk,
2998                                                    rdev->clock.current_dispclk,
2999                                                    max_limits->vddc,  &ps->performance_levels[i].vddc);
3000         }
3001
3002         for (i = 0; i < ps->performance_level_count; i++) {
3003                 btc_apply_voltage_delta_rules(rdev,
3004                                               max_limits->vddc, max_limits->vddci,
3005                                               &ps->performance_levels[i].vddc,
3006                                               &ps->performance_levels[i].vddci);
3007         }
3008
3009         ps->dc_compatible = true;
3010         for (i = 0; i < ps->performance_level_count; i++) {
3011                 if (ps->performance_levels[i].vddc > rdev->pm.dpm.dyn_state.max_clock_voltage_on_dc.vddc)
3012                         ps->dc_compatible = false;
3013         }
3014
3015 }
3016
3017 #if 0
3018 static int si_read_smc_soft_register(struct radeon_device *rdev,
3019                                      u16 reg_offset, u32 *value)
3020 {
3021         struct si_power_info *si_pi = si_get_pi(rdev);
3022
3023         return si_read_smc_sram_dword(rdev,
3024                                       si_pi->soft_regs_start + reg_offset, value,
3025                                       si_pi->sram_end);
3026 }
3027 #endif
3028
3029 static int si_write_smc_soft_register(struct radeon_device *rdev,
3030                                       u16 reg_offset, u32 value)
3031 {
3032         struct si_power_info *si_pi = si_get_pi(rdev);
3033
3034         return si_write_smc_sram_dword(rdev,
3035                                        si_pi->soft_regs_start + reg_offset,
3036                                        value, si_pi->sram_end);
3037 }
3038
3039 static bool si_is_special_1gb_platform(struct radeon_device *rdev)
3040 {
3041         bool ret = false;
3042         u32 tmp, width, row, column, bank, density;
3043         bool is_memory_gddr5, is_special;
3044
3045         tmp = RREG32(MC_SEQ_MISC0);
3046         is_memory_gddr5 = (MC_SEQ_MISC0_GDDR5_VALUE == ((tmp & MC_SEQ_MISC0_GDDR5_MASK) >> MC_SEQ_MISC0_GDDR5_SHIFT));
3047         is_special = (MC_SEQ_MISC0_REV_ID_VALUE == ((tmp & MC_SEQ_MISC0_REV_ID_MASK) >> MC_SEQ_MISC0_REV_ID_SHIFT))
3048                 & (MC_SEQ_MISC0_VEN_ID_VALUE == ((tmp & MC_SEQ_MISC0_VEN_ID_MASK) >> MC_SEQ_MISC0_VEN_ID_SHIFT));
3049
3050         WREG32(MC_SEQ_IO_DEBUG_INDEX, 0xb);
3051         width = ((RREG32(MC_SEQ_IO_DEBUG_DATA) >> 1) & 1) ? 16 : 32;
3052
3053         tmp = RREG32(MC_ARB_RAMCFG);
3054         row = ((tmp & NOOFROWS_MASK) >> NOOFROWS_SHIFT) + 10;
3055         column = ((tmp & NOOFCOLS_MASK) >> NOOFCOLS_SHIFT) + 8;
3056         bank = ((tmp & NOOFBANK_MASK) >> NOOFBANK_SHIFT) + 2;
3057
3058         density = (1 << (row + column - 20 + bank)) * width;
3059
3060         if ((rdev->pdev->device == 0x6819) &&
3061             is_memory_gddr5 && is_special && (density == 0x400))
3062                 ret = true;
3063
3064         return ret;
3065 }
3066
3067 static void si_get_leakage_vddc(struct radeon_device *rdev)
3068 {
3069         struct si_power_info *si_pi = si_get_pi(rdev);
3070         u16 vddc, count = 0;
3071         int i, ret;
3072
3073         for (i = 0; i < SISLANDS_MAX_LEAKAGE_COUNT; i++) {
3074                 ret = radeon_atom_get_leakage_vddc_based_on_leakage_idx(rdev, &vddc, SISLANDS_LEAKAGE_INDEX0 + i);
3075
3076                 if (!ret && (vddc > 0) && (vddc != (SISLANDS_LEAKAGE_INDEX0 + i))) {
3077                         si_pi->leakage_voltage.entries[count].voltage = vddc;
3078                         si_pi->leakage_voltage.entries[count].leakage_index =
3079                                 SISLANDS_LEAKAGE_INDEX0 + i;
3080                         count++;
3081                 }
3082         }
3083         si_pi->leakage_voltage.count = count;
3084 }
3085
3086 static int si_get_leakage_voltage_from_leakage_index(struct radeon_device *rdev,
3087                                                      u32 index, u16 *leakage_voltage)
3088 {
3089         struct si_power_info *si_pi = si_get_pi(rdev);
3090         int i;
3091
3092         if (leakage_voltage == NULL)
3093                 return -EINVAL;
3094
3095         if ((index & 0xff00) != 0xff00)
3096                 return -EINVAL;
3097
3098         if ((index & 0xff) > SISLANDS_MAX_LEAKAGE_COUNT + 1)
3099                 return -EINVAL;
3100
3101         if (index < SISLANDS_LEAKAGE_INDEX0)
3102                 return -EINVAL;
3103
3104         for (i = 0; i < si_pi->leakage_voltage.count; i++) {
3105                 if (si_pi->leakage_voltage.entries[i].leakage_index == index) {
3106                         *leakage_voltage = si_pi->leakage_voltage.entries[i].voltage;
3107                         return 0;
3108                 }
3109         }
3110         return -EAGAIN;
3111 }
3112
3113 static void si_set_dpm_event_sources(struct radeon_device *rdev, u32 sources)
3114 {
3115         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3116         bool want_thermal_protection;
3117         enum radeon_dpm_event_src dpm_event_src;
3118
3119         switch (sources) {
3120         case 0:
3121         default:
3122                 want_thermal_protection = false;
3123                 break;
3124         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL):
3125                 want_thermal_protection = true;
3126                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGITAL;
3127                 break;
3128         case (1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL):
3129                 want_thermal_protection = true;
3130                 dpm_event_src = RADEON_DPM_EVENT_SRC_EXTERNAL;
3131                 break;
3132         case ((1 << RADEON_DPM_AUTO_THROTTLE_SRC_EXTERNAL) |
3133               (1 << RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL)):
3134                 want_thermal_protection = true;
3135                 dpm_event_src = RADEON_DPM_EVENT_SRC_DIGIAL_OR_EXTERNAL;
3136                 break;
3137         }
3138
3139         if (want_thermal_protection) {
3140                 WREG32_P(CG_THERMAL_CTRL, DPM_EVENT_SRC(dpm_event_src), ~DPM_EVENT_SRC_MASK);
3141                 if (pi->thermal_protection)
3142                         WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3143         } else {
3144                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3145         }
3146 }
3147
3148 static void si_enable_auto_throttle_source(struct radeon_device *rdev,
3149                                            enum radeon_dpm_auto_throttle_src source,
3150                                            bool enable)
3151 {
3152         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3153
3154         if (enable) {
3155                 if (!(pi->active_auto_throttle_sources & (1 << source))) {
3156                         pi->active_auto_throttle_sources |= 1 << source;
3157                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3158                 }
3159         } else {
3160                 if (pi->active_auto_throttle_sources & (1 << source)) {
3161                         pi->active_auto_throttle_sources &= ~(1 << source);
3162                         si_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources);
3163                 }
3164         }
3165 }
3166
3167 static void si_start_dpm(struct radeon_device *rdev)
3168 {
3169         WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN);
3170 }
3171
3172 static void si_stop_dpm(struct radeon_device *rdev)
3173 {
3174         WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN);
3175 }
3176
3177 static void si_enable_sclk_control(struct radeon_device *rdev, bool enable)
3178 {
3179         if (enable)
3180                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF);
3181         else
3182                 WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF);
3183
3184 }
3185
3186 #if 0
3187 static int si_notify_hardware_of_thermal_state(struct radeon_device *rdev,
3188                                                u32 thermal_level)
3189 {
3190         PPSMC_Result ret;
3191
3192         if (thermal_level == 0) {
3193                 ret = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
3194                 if (ret == PPSMC_Result_OK)
3195                         return 0;
3196                 else
3197                         return -EINVAL;
3198         }
3199         return 0;
3200 }
3201
3202 static void si_notify_hardware_vpu_recovery_event(struct radeon_device *rdev)
3203 {
3204         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_tdr_is_about_to_happen, true);
3205 }
3206 #endif
3207
3208 #if 0
3209 static int si_notify_hw_of_powersource(struct radeon_device *rdev, bool ac_power)
3210 {
3211         if (ac_power)
3212                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_RunningOnAC) == PPSMC_Result_OK) ?
3213                         0 : -EINVAL;
3214
3215         return 0;
3216 }
3217 #endif
3218
3219 static PPSMC_Result si_send_msg_to_smc_with_parameter(struct radeon_device *rdev,
3220                                                       PPSMC_Msg msg, u32 parameter)
3221 {
3222         WREG32(SMC_SCRATCH0, parameter);
3223         return si_send_msg_to_smc(rdev, msg);
3224 }
3225
3226 static int si_restrict_performance_levels_before_switch(struct radeon_device *rdev)
3227 {
3228         if (si_send_msg_to_smc(rdev, PPSMC_MSG_NoForcedLevel) != PPSMC_Result_OK)
3229                 return -EINVAL;
3230
3231         return (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 1) == PPSMC_Result_OK) ?
3232                 0 : -EINVAL;
3233 }
3234
3235 int si_dpm_force_performance_level(struct radeon_device *rdev,
3236                                    enum radeon_dpm_forced_level level)
3237 {
3238         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
3239         struct ni_ps *ps = ni_get_ps(rps);
3240         u32 levels;
3241
3242         if (level == RADEON_DPM_FORCED_LEVEL_HIGH) {
3243                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3244                         return -EINVAL;
3245
3246                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 1) != PPSMC_Result_OK)
3247                         return -EINVAL;
3248         } else if (level == RADEON_DPM_FORCED_LEVEL_LOW) {
3249                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3250                         return -EINVAL;
3251
3252                 levels = ps->performance_level_count - 1;
3253                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, levels) != PPSMC_Result_OK)
3254                         return -EINVAL;
3255         } else if (level == RADEON_DPM_FORCED_LEVEL_AUTO) {
3256                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetForcedLevels, 0) != PPSMC_Result_OK)
3257                         return -EINVAL;
3258
3259                 if (si_send_msg_to_smc_with_parameter(rdev, PPSMC_MSG_SetEnabledLevels, 0) != PPSMC_Result_OK)
3260                         return -EINVAL;
3261         }
3262
3263         rdev->pm.dpm.forced_level = level;
3264
3265         return 0;
3266 }
3267
3268 static int si_set_boot_state(struct radeon_device *rdev)
3269 {
3270         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToInitialState) == PPSMC_Result_OK) ?
3271                 0 : -EINVAL;
3272 }
3273
3274 static int si_set_sw_state(struct radeon_device *rdev)
3275 {
3276         return (si_send_msg_to_smc(rdev, PPSMC_MSG_SwitchToSwState) == PPSMC_Result_OK) ?
3277                 0 : -EINVAL;
3278 }
3279
3280 static int si_halt_smc(struct radeon_device *rdev)
3281 {
3282         if (si_send_msg_to_smc(rdev, PPSMC_MSG_Halt) != PPSMC_Result_OK)
3283                 return -EINVAL;
3284
3285         return (si_wait_for_smc_inactive(rdev) == PPSMC_Result_OK) ?
3286                 0 : -EINVAL;
3287 }
3288
3289 static int si_resume_smc(struct radeon_device *rdev)
3290 {
3291         if (si_send_msg_to_smc(rdev, PPSMC_FlushDataCache) != PPSMC_Result_OK)
3292                 return -EINVAL;
3293
3294         return (si_send_msg_to_smc(rdev, PPSMC_MSG_Resume) == PPSMC_Result_OK) ?
3295                 0 : -EINVAL;
3296 }
3297
3298 static void si_dpm_start_smc(struct radeon_device *rdev)
3299 {
3300         si_program_jump_on_start(rdev);
3301         si_start_smc(rdev);
3302         si_start_smc_clock(rdev);
3303 }
3304
3305 static void si_dpm_stop_smc(struct radeon_device *rdev)
3306 {
3307         si_reset_smc(rdev);
3308         si_stop_smc_clock(rdev);
3309 }
3310
3311 static int si_process_firmware_header(struct radeon_device *rdev)
3312 {
3313         struct si_power_info *si_pi = si_get_pi(rdev);
3314         u32 tmp;
3315         int ret;
3316
3317         ret = si_read_smc_sram_dword(rdev,
3318                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3319                                      SISLANDS_SMC_FIRMWARE_HEADER_stateTable,
3320                                      &tmp, si_pi->sram_end);
3321         if (ret)
3322                 return ret;
3323
3324         si_pi->state_table_start = tmp;
3325
3326         ret = si_read_smc_sram_dword(rdev,
3327                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3328                                      SISLANDS_SMC_FIRMWARE_HEADER_softRegisters,
3329                                      &tmp, si_pi->sram_end);
3330         if (ret)
3331                 return ret;
3332
3333         si_pi->soft_regs_start = tmp;
3334
3335         ret = si_read_smc_sram_dword(rdev,
3336                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3337                                      SISLANDS_SMC_FIRMWARE_HEADER_mcRegisterTable,
3338                                      &tmp, si_pi->sram_end);
3339         if (ret)
3340                 return ret;
3341
3342         si_pi->mc_reg_table_start = tmp;
3343
3344         ret = si_read_smc_sram_dword(rdev,
3345                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3346                                      SISLANDS_SMC_FIRMWARE_HEADER_mcArbDramAutoRefreshTable,
3347                                      &tmp, si_pi->sram_end);
3348         if (ret)
3349                 return ret;
3350
3351         si_pi->arb_table_start = tmp;
3352
3353         ret = si_read_smc_sram_dword(rdev,
3354                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3355                                      SISLANDS_SMC_FIRMWARE_HEADER_CacConfigTable,
3356                                      &tmp, si_pi->sram_end);
3357         if (ret)
3358                 return ret;
3359
3360         si_pi->cac_table_start = tmp;
3361
3362         ret = si_read_smc_sram_dword(rdev,
3363                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3364                                      SISLANDS_SMC_FIRMWARE_HEADER_DteConfiguration,
3365                                      &tmp, si_pi->sram_end);
3366         if (ret)
3367                 return ret;
3368
3369         si_pi->dte_table_start = tmp;
3370
3371         ret = si_read_smc_sram_dword(rdev,
3372                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3373                                      SISLANDS_SMC_FIRMWARE_HEADER_spllTable,
3374                                      &tmp, si_pi->sram_end);
3375         if (ret)
3376                 return ret;
3377
3378         si_pi->spll_table_start = tmp;
3379
3380         ret = si_read_smc_sram_dword(rdev,
3381                                      SISLANDS_SMC_FIRMWARE_HEADER_LOCATION +
3382                                      SISLANDS_SMC_FIRMWARE_HEADER_PAPMParameters,
3383                                      &tmp, si_pi->sram_end);
3384         if (ret)
3385                 return ret;
3386
3387         si_pi->papm_cfg_table_start = tmp;
3388
3389         return ret;
3390 }
3391
3392 static void si_read_clock_registers(struct radeon_device *rdev)
3393 {
3394         struct si_power_info *si_pi = si_get_pi(rdev);
3395
3396         si_pi->clock_registers.cg_spll_func_cntl = RREG32(CG_SPLL_FUNC_CNTL);
3397         si_pi->clock_registers.cg_spll_func_cntl_2 = RREG32(CG_SPLL_FUNC_CNTL_2);
3398         si_pi->clock_registers.cg_spll_func_cntl_3 = RREG32(CG_SPLL_FUNC_CNTL_3);
3399         si_pi->clock_registers.cg_spll_func_cntl_4 = RREG32(CG_SPLL_FUNC_CNTL_4);
3400         si_pi->clock_registers.cg_spll_spread_spectrum = RREG32(CG_SPLL_SPREAD_SPECTRUM);
3401         si_pi->clock_registers.cg_spll_spread_spectrum_2 = RREG32(CG_SPLL_SPREAD_SPECTRUM_2);
3402         si_pi->clock_registers.dll_cntl = RREG32(DLL_CNTL);
3403         si_pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL);
3404         si_pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL);
3405         si_pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL);
3406         si_pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL);
3407         si_pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1);
3408         si_pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2);
3409         si_pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1);
3410         si_pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2);
3411 }
3412
3413 static void si_enable_thermal_protection(struct radeon_device *rdev,
3414                                           bool enable)
3415 {
3416         if (enable)
3417                 WREG32_P(GENERAL_PWRMGT, 0, ~THERMAL_PROTECTION_DIS);
3418         else
3419                 WREG32_P(GENERAL_PWRMGT, THERMAL_PROTECTION_DIS, ~THERMAL_PROTECTION_DIS);
3420 }
3421
3422 static void si_enable_acpi_power_management(struct radeon_device *rdev)
3423 {
3424         WREG32_P(GENERAL_PWRMGT, STATIC_PM_EN, ~STATIC_PM_EN);
3425 }
3426
3427 #if 0
3428 static int si_enter_ulp_state(struct radeon_device *rdev)
3429 {
3430         WREG32(SMC_MESSAGE_0, PPSMC_MSG_SwitchToMinimumPower);
3431
3432         udelay(25000);
3433
3434         return 0;
3435 }
3436
3437 static int si_exit_ulp_state(struct radeon_device *rdev)
3438 {
3439         int i;
3440
3441         WREG32(SMC_MESSAGE_0, PPSMC_MSG_ResumeFromMinimumPower);
3442
3443         udelay(7000);
3444
3445         for (i = 0; i < rdev->usec_timeout; i++) {
3446                 if (RREG32(SMC_RESP_0) == 1)
3447                         break;
3448                 udelay(1000);
3449         }
3450
3451         return 0;
3452 }
3453 #endif
3454
3455 static int si_notify_smc_display_change(struct radeon_device *rdev,
3456                                      bool has_display)
3457 {
3458         PPSMC_Msg msg = has_display ?
3459                 PPSMC_MSG_HasDisplay : PPSMC_MSG_NoDisplay;
3460
3461         return (si_send_msg_to_smc(rdev, msg) == PPSMC_Result_OK) ?
3462                 0 : -EINVAL;
3463 }
3464
3465 static void si_program_response_times(struct radeon_device *rdev)
3466 {
3467         u32 voltage_response_time, backbias_response_time, acpi_delay_time, vbi_time_out;
3468         u32 vddc_dly, acpi_dly, vbi_dly;
3469         u32 reference_clock;
3470
3471         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mvdd_chg_time, 1);
3472
3473         voltage_response_time = (u32)rdev->pm.dpm.voltage_response_time;
3474         backbias_response_time = (u32)rdev->pm.dpm.backbias_response_time;
3475
3476         if (voltage_response_time == 0)
3477                 voltage_response_time = 1000;
3478
3479         acpi_delay_time = 15000;
3480         vbi_time_out = 100000;
3481
3482         reference_clock = radeon_get_xclk(rdev);
3483
3484         vddc_dly = (voltage_response_time  * reference_clock) / 100;
3485         acpi_dly = (acpi_delay_time * reference_clock) / 100;
3486         vbi_dly  = (vbi_time_out * reference_clock) / 100;
3487
3488         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_vreg,  vddc_dly);
3489         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_delay_acpi,  acpi_dly);
3490         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mclk_chg_timeout, vbi_dly);
3491         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_mc_block_delay, 0xAA);
3492 }
3493
3494 static void si_program_ds_registers(struct radeon_device *rdev)
3495 {
3496         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3497         u32 tmp = 1; /* XXX: 0x10 on tahiti A0 */
3498
3499         if (eg_pi->sclk_deep_sleep) {
3500                 WREG32_P(MISC_CLK_CNTL, DEEP_SLEEP_CLK_SEL(tmp), ~DEEP_SLEEP_CLK_SEL_MASK);
3501                 WREG32_P(CG_SPLL_AUTOSCALE_CNTL, AUTOSCALE_ON_SS_CLEAR,
3502                          ~AUTOSCALE_ON_SS_CLEAR);
3503         }
3504 }
3505
3506 static void si_program_display_gap(struct radeon_device *rdev)
3507 {
3508         u32 tmp, pipe;
3509         int i;
3510
3511         tmp = RREG32(CG_DISPLAY_GAP_CNTL) & ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3512         if (rdev->pm.dpm.new_active_crtc_count > 0)
3513                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3514         else
3515                 tmp |= DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3516
3517         if (rdev->pm.dpm.new_active_crtc_count > 1)
3518                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_VBLANK_OR_WM);
3519         else
3520                 tmp |= DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE);
3521
3522         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3523
3524         tmp = RREG32(DCCG_DISP_SLOW_SELECT_REG);
3525         pipe = (tmp & DCCG_DISP1_SLOW_SELECT_MASK) >> DCCG_DISP1_SLOW_SELECT_SHIFT;
3526
3527         if ((rdev->pm.dpm.new_active_crtc_count > 0) &&
3528             (!(rdev->pm.dpm.new_active_crtcs & (1 << pipe)))) {
3529                 /* find the first active crtc */
3530                 for (i = 0; i < rdev->num_crtc; i++) {
3531                         if (rdev->pm.dpm.new_active_crtcs & (1 << i))
3532                                 break;
3533                 }
3534                 if (i == rdev->num_crtc)
3535                         pipe = 0;
3536                 else
3537                         pipe = i;
3538
3539                 tmp &= ~DCCG_DISP1_SLOW_SELECT_MASK;
3540                 tmp |= DCCG_DISP1_SLOW_SELECT(pipe);
3541                 WREG32(DCCG_DISP_SLOW_SELECT_REG, tmp);
3542         }
3543
3544         si_notify_smc_display_change(rdev, rdev->pm.dpm.new_active_crtc_count > 0);
3545 }
3546
3547 static void si_enable_spread_spectrum(struct radeon_device *rdev, bool enable)
3548 {
3549         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3550
3551         if (enable) {
3552                 if (pi->sclk_ss)
3553                         WREG32_P(GENERAL_PWRMGT, DYN_SPREAD_SPECTRUM_EN, ~DYN_SPREAD_SPECTRUM_EN);
3554         } else {
3555                 WREG32_P(CG_SPLL_SPREAD_SPECTRUM, 0, ~SSEN);
3556                 WREG32_P(GENERAL_PWRMGT, 0, ~DYN_SPREAD_SPECTRUM_EN);
3557         }
3558 }
3559
3560 static void si_setup_bsp(struct radeon_device *rdev)
3561 {
3562         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3563         u32 xclk = radeon_get_xclk(rdev);
3564
3565         r600_calculate_u_and_p(pi->asi,
3566                                xclk,
3567                                16,
3568                                &pi->bsp,
3569                                &pi->bsu);
3570
3571         r600_calculate_u_and_p(pi->pasi,
3572                                xclk,
3573                                16,
3574                                &pi->pbsp,
3575                                &pi->pbsu);
3576
3577
3578         pi->dsp = BSP(pi->bsp) | BSU(pi->bsu);
3579         pi->psp = BSP(pi->pbsp) | BSU(pi->pbsu);
3580
3581         WREG32(CG_BSP, pi->dsp);
3582 }
3583
3584 static void si_program_git(struct radeon_device *rdev)
3585 {
3586         WREG32_P(CG_GIT, CG_GICST(R600_GICST_DFLT), ~CG_GICST_MASK);
3587 }
3588
3589 static void si_program_tp(struct radeon_device *rdev)
3590 {
3591         int i;
3592         enum r600_td td = R600_TD_DFLT;
3593
3594         for (i = 0; i < R600_PM_NUMBER_OF_TC; i++)
3595                 WREG32(CG_FFCT_0 + (i * 4), (UTC_0(r600_utc[i]) | DTC_0(r600_dtc[i])));
3596
3597         if (td == R600_TD_AUTO)
3598                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_FORCE_TREND_SEL);
3599         else
3600                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_FORCE_TREND_SEL, ~FIR_FORCE_TREND_SEL);
3601
3602         if (td == R600_TD_UP)
3603                 WREG32_P(SCLK_PWRMGT_CNTL, 0, ~FIR_TREND_MODE);
3604
3605         if (td == R600_TD_DOWN)
3606                 WREG32_P(SCLK_PWRMGT_CNTL, FIR_TREND_MODE, ~FIR_TREND_MODE);
3607 }
3608
3609 static void si_program_tpp(struct radeon_device *rdev)
3610 {
3611         WREG32(CG_TPC, R600_TPC_DFLT);
3612 }
3613
3614 static void si_program_sstp(struct radeon_device *rdev)
3615 {
3616         WREG32(CG_SSP, (SSTU(R600_SSTU_DFLT) | SST(R600_SST_DFLT)));
3617 }
3618
3619 static void si_enable_display_gap(struct radeon_device *rdev)
3620 {
3621         u32 tmp = RREG32(CG_DISPLAY_GAP_CNTL);
3622
3623         tmp &= ~(DISP1_GAP_MASK | DISP2_GAP_MASK);
3624         tmp |= (DISP1_GAP(R600_PM_DISPLAY_GAP_IGNORE) |
3625                 DISP2_GAP(R600_PM_DISPLAY_GAP_IGNORE));
3626
3627         tmp &= ~(DISP1_GAP_MCHG_MASK | DISP2_GAP_MCHG_MASK);
3628         tmp |= (DISP1_GAP_MCHG(R600_PM_DISPLAY_GAP_VBLANK) |
3629                 DISP2_GAP_MCHG(R600_PM_DISPLAY_GAP_IGNORE));
3630         WREG32(CG_DISPLAY_GAP_CNTL, tmp);
3631 }
3632
3633 static void si_program_vc(struct radeon_device *rdev)
3634 {
3635         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3636
3637         WREG32(CG_FTV, pi->vrc);
3638 }
3639
3640 static void si_clear_vc(struct radeon_device *rdev)
3641 {
3642         WREG32(CG_FTV, 0);
3643 }
3644
3645 static u8 si_get_ddr3_mclk_frequency_ratio(u32 memory_clock)
3646 {
3647         u8 mc_para_index;
3648
3649         if (memory_clock < 10000)
3650                 mc_para_index = 0;
3651         else if (memory_clock >= 80000)
3652                 mc_para_index = 0x0f;
3653         else
3654                 mc_para_index = (u8)((memory_clock - 10000) / 5000 + 1);
3655         return mc_para_index;
3656 }
3657
3658 static u8 si_get_mclk_frequency_ratio(u32 memory_clock, bool strobe_mode)
3659 {
3660         u8 mc_para_index;
3661
3662         if (strobe_mode) {
3663                 if (memory_clock < 12500)
3664                         mc_para_index = 0x00;
3665                 else if (memory_clock > 47500)
3666                         mc_para_index = 0x0f;
3667                 else
3668                         mc_para_index = (u8)((memory_clock - 10000) / 2500);
3669         } else {
3670                 if (memory_clock < 65000)
3671                         mc_para_index = 0x00;
3672                 else if (memory_clock > 135000)
3673                         mc_para_index = 0x0f;
3674                 else
3675                         mc_para_index = (u8)((memory_clock - 60000) / 5000);
3676         }
3677         return mc_para_index;
3678 }
3679
3680 static u8 si_get_strobe_mode_settings(struct radeon_device *rdev, u32 mclk)
3681 {
3682         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3683         bool strobe_mode = false;
3684         u8 result = 0;
3685
3686         if (mclk <= pi->mclk_strobe_mode_threshold)
3687                 strobe_mode = true;
3688
3689         if (pi->mem_gddr5)
3690                 result = si_get_mclk_frequency_ratio(mclk, strobe_mode);
3691         else
3692                 result = si_get_ddr3_mclk_frequency_ratio(mclk);
3693
3694         if (strobe_mode)
3695                 result |= SISLANDS_SMC_STROBE_ENABLE;
3696
3697         return result;
3698 }
3699
3700 static int si_upload_firmware(struct radeon_device *rdev)
3701 {
3702         struct si_power_info *si_pi = si_get_pi(rdev);
3703         int ret;
3704
3705         si_reset_smc(rdev);
3706         si_stop_smc_clock(rdev);
3707
3708         ret = si_load_smc_ucode(rdev, si_pi->sram_end);
3709
3710         return ret;
3711 }
3712
3713 static bool si_validate_phase_shedding_tables(struct radeon_device *rdev,
3714                                               const struct atom_voltage_table *table,
3715                                               const struct radeon_phase_shedding_limits_table *limits)
3716 {
3717         u32 data, num_bits, num_levels;
3718
3719         if ((table == NULL) || (limits == NULL))
3720                 return false;
3721
3722         data = table->mask_low;
3723
3724         num_bits = hweight32(data);
3725
3726         if (num_bits == 0)
3727                 return false;
3728
3729         num_levels = (1 << num_bits);
3730
3731         if (table->count != num_levels)
3732                 return false;
3733
3734         if (limits->count != (num_levels - 1))
3735                 return false;
3736
3737         return true;
3738 }
3739
3740 static void si_trim_voltage_table_to_fit_state_table(struct radeon_device *rdev,
3741                                                      struct atom_voltage_table *voltage_table)
3742 {
3743         unsigned int i, diff;
3744
3745         if (voltage_table->count <= SISLANDS_MAX_NO_VREG_STEPS)
3746                 return;
3747
3748         diff = voltage_table->count - SISLANDS_MAX_NO_VREG_STEPS;
3749
3750         for (i= 0; i < SISLANDS_MAX_NO_VREG_STEPS; i++)
3751                 voltage_table->entries[i] = voltage_table->entries[i + diff];
3752
3753         voltage_table->count = SISLANDS_MAX_NO_VREG_STEPS;
3754 }
3755
3756 static int si_construct_voltage_tables(struct radeon_device *rdev)
3757 {
3758         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3759         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3760         struct si_power_info *si_pi = si_get_pi(rdev);
3761         int ret;
3762
3763         ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3764                                             VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddc_voltage_table);
3765         if (ret)
3766                 return ret;
3767
3768         if (eg_pi->vddc_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3769                 si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddc_voltage_table);
3770
3771         if (eg_pi->vddci_control) {
3772                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDCI,
3773                                                     VOLTAGE_OBJ_GPIO_LUT, &eg_pi->vddci_voltage_table);
3774                 if (ret)
3775                         return ret;
3776
3777                 if (eg_pi->vddci_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3778                         si_trim_voltage_table_to_fit_state_table(rdev, &eg_pi->vddci_voltage_table);
3779         }
3780
3781         if (pi->mvdd_control) {
3782                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_MVDDC,
3783                                                     VOLTAGE_OBJ_GPIO_LUT, &si_pi->mvdd_voltage_table);
3784
3785                 if (ret) {
3786                         pi->mvdd_control = false;
3787                         return ret;
3788                 }
3789
3790                 if (si_pi->mvdd_voltage_table.count == 0) {
3791                         pi->mvdd_control = false;
3792                         return -EINVAL;
3793                 }
3794
3795                 if (si_pi->mvdd_voltage_table.count > SISLANDS_MAX_NO_VREG_STEPS)
3796                         si_trim_voltage_table_to_fit_state_table(rdev, &si_pi->mvdd_voltage_table);
3797         }
3798
3799         if (si_pi->vddc_phase_shed_control) {
3800                 ret = radeon_atom_get_voltage_table(rdev, VOLTAGE_TYPE_VDDC,
3801                                                     VOLTAGE_OBJ_PHASE_LUT, &si_pi->vddc_phase_shed_table);
3802                 if (ret)
3803                         si_pi->vddc_phase_shed_control = false;
3804
3805                 if ((si_pi->vddc_phase_shed_table.count == 0) ||
3806                     (si_pi->vddc_phase_shed_table.count > SISLANDS_MAX_NO_VREG_STEPS))
3807                         si_pi->vddc_phase_shed_control = false;
3808         }
3809
3810         return 0;
3811 }
3812
3813 static void si_populate_smc_voltage_table(struct radeon_device *rdev,
3814                                           const struct atom_voltage_table *voltage_table,
3815                                           SISLANDS_SMC_STATETABLE *table)
3816 {
3817         unsigned int i;
3818
3819         for (i = 0; i < voltage_table->count; i++)
3820                 table->lowSMIO[i] |= cpu_to_be32(voltage_table->entries[i].smio_low);
3821 }
3822
3823 static int si_populate_smc_voltage_tables(struct radeon_device *rdev,
3824                                           SISLANDS_SMC_STATETABLE *table)
3825 {
3826         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3827         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
3828         struct si_power_info *si_pi = si_get_pi(rdev);
3829         u8 i;
3830
3831         if (eg_pi->vddc_voltage_table.count) {
3832                 si_populate_smc_voltage_table(rdev, &eg_pi->vddc_voltage_table, table);
3833                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3834                         cpu_to_be32(eg_pi->vddc_voltage_table.mask_low);
3835
3836                 for (i = 0; i < eg_pi->vddc_voltage_table.count; i++) {
3837                         if (pi->max_vddc_in_table <= eg_pi->vddc_voltage_table.entries[i].value) {
3838                                 table->maxVDDCIndexInPPTable = i;
3839                                 break;
3840                         }
3841                 }
3842         }
3843
3844         if (eg_pi->vddci_voltage_table.count) {
3845                 si_populate_smc_voltage_table(rdev, &eg_pi->vddci_voltage_table, table);
3846
3847                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDCI] =
3848                         cpu_to_be32(eg_pi->vddci_voltage_table.mask_low);
3849         }
3850
3851
3852         if (si_pi->mvdd_voltage_table.count) {
3853                 si_populate_smc_voltage_table(rdev, &si_pi->mvdd_voltage_table, table);
3854
3855                 table->voltageMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_MVDD] =
3856                         cpu_to_be32(si_pi->mvdd_voltage_table.mask_low);
3857         }
3858
3859         if (si_pi->vddc_phase_shed_control) {
3860                 if (si_validate_phase_shedding_tables(rdev, &si_pi->vddc_phase_shed_table,
3861                                                       &rdev->pm.dpm.dyn_state.phase_shedding_limits_table)) {
3862                         si_populate_smc_voltage_table(rdev, &si_pi->vddc_phase_shed_table, table);
3863
3864                         table->phaseMaskTable.lowMask[SISLANDS_SMC_VOLTAGEMASK_VDDC] =
3865                                 cpu_to_be32(si_pi->vddc_phase_shed_table.mask_low);
3866
3867                         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_phase_shedding_delay,
3868                                                    (u32)si_pi->vddc_phase_shed_table.phase_delay);
3869                 } else {
3870                         si_pi->vddc_phase_shed_control = false;
3871                 }
3872         }
3873
3874         return 0;
3875 }
3876
3877 static int si_populate_voltage_value(struct radeon_device *rdev,
3878                                      const struct atom_voltage_table *table,
3879                                      u16 value, SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3880 {
3881         unsigned int i;
3882
3883         for (i = 0; i < table->count; i++) {
3884                 if (value <= table->entries[i].value) {
3885                         voltage->index = (u8)i;
3886                         voltage->value = cpu_to_be16(table->entries[i].value);
3887                         break;
3888                 }
3889         }
3890
3891         if (i >= table->count)
3892                 return -EINVAL;
3893
3894         return 0;
3895 }
3896
3897 static int si_populate_mvdd_value(struct radeon_device *rdev, u32 mclk,
3898                                   SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3899 {
3900         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
3901         struct si_power_info *si_pi = si_get_pi(rdev);
3902
3903         if (pi->mvdd_control) {
3904                 if (mclk <= pi->mvdd_split_frequency)
3905                         voltage->index = 0;
3906                 else
3907                         voltage->index = (u8)(si_pi->mvdd_voltage_table.count) - 1;
3908
3909                 voltage->value = cpu_to_be16(si_pi->mvdd_voltage_table.entries[voltage->index].value);
3910         }
3911         return 0;
3912 }
3913
3914 static int si_get_std_voltage_value(struct radeon_device *rdev,
3915                                     SISLANDS_SMC_VOLTAGE_VALUE *voltage,
3916                                     u16 *std_voltage)
3917 {
3918         u16 v_index;
3919         bool voltage_found = false;
3920         *std_voltage = be16_to_cpu(voltage->value);
3921
3922         if (rdev->pm.dpm.dyn_state.cac_leakage_table.entries) {
3923                 if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_NEW_CAC_VOLTAGE) {
3924                         if (rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries == NULL)
3925                                 return -EINVAL;
3926
3927                         for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3928                                 if (be16_to_cpu(voltage->value) ==
3929                                     (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3930                                         voltage_found = true;
3931                                         if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3932                                                 *std_voltage =
3933                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3934                                         else
3935                                                 *std_voltage =
3936                                                         rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3937                                         break;
3938                                 }
3939                         }
3940
3941                         if (!voltage_found) {
3942                                 for (v_index = 0; (u32)v_index < rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.count; v_index++) {
3943                                         if (be16_to_cpu(voltage->value) <=
3944                                             (u16)rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk.entries[v_index].v) {
3945                                                 voltage_found = true;
3946                                                 if ((u32)v_index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3947                                                         *std_voltage =
3948                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[v_index].vddc;
3949                                                 else
3950                                                         *std_voltage =
3951                                                                 rdev->pm.dpm.dyn_state.cac_leakage_table.entries[rdev->pm.dpm.dyn_state.cac_leakage_table.count-1].vddc;
3952                                                 break;
3953                                         }
3954                                 }
3955                         }
3956                 } else {
3957                         if ((u32)voltage->index < rdev->pm.dpm.dyn_state.cac_leakage_table.count)
3958                                 *std_voltage = rdev->pm.dpm.dyn_state.cac_leakage_table.entries[voltage->index].vddc;
3959                 }
3960         }
3961
3962         return 0;
3963 }
3964
3965 static int si_populate_std_voltage_value(struct radeon_device *rdev,
3966                                          u16 value, u8 index,
3967                                          SISLANDS_SMC_VOLTAGE_VALUE *voltage)
3968 {
3969         voltage->index = index;
3970         voltage->value = cpu_to_be16(value);
3971
3972         return 0;
3973 }
3974
3975 static int si_populate_phase_shedding_value(struct radeon_device *rdev,
3976                                             const struct radeon_phase_shedding_limits_table *limits,
3977                                             u16 voltage, u32 sclk, u32 mclk,
3978                                             SISLANDS_SMC_VOLTAGE_VALUE *smc_voltage)
3979 {
3980         unsigned int i;
3981
3982         for (i = 0; i < limits->count; i++) {
3983                 if ((voltage <= limits->entries[i].voltage) &&
3984                     (sclk <= limits->entries[i].sclk) &&
3985                     (mclk <= limits->entries[i].mclk))
3986                         break;
3987         }
3988
3989         smc_voltage->phase_settings = (u8)i;
3990
3991         return 0;
3992 }
3993
3994 static int si_init_arb_table_index(struct radeon_device *rdev)
3995 {
3996         struct si_power_info *si_pi = si_get_pi(rdev);
3997         u32 tmp;
3998         int ret;
3999
4000         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start, &tmp, si_pi->sram_end);
4001         if (ret)
4002                 return ret;
4003
4004         tmp &= 0x00FFFFFF;
4005         tmp |= MC_CG_ARB_FREQ_F1 << 24;
4006
4007         return si_write_smc_sram_dword(rdev, si_pi->arb_table_start,  tmp, si_pi->sram_end);
4008 }
4009
4010 static int si_initial_switch_from_arb_f0_to_f1(struct radeon_device *rdev)
4011 {
4012         return ni_copy_and_switch_arb_sets(rdev, MC_CG_ARB_FREQ_F0, MC_CG_ARB_FREQ_F1);
4013 }
4014
4015 static int si_reset_to_default(struct radeon_device *rdev)
4016 {
4017         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ResetToDefaults) == PPSMC_Result_OK) ?
4018                 0 : -EINVAL;
4019 }
4020
4021 static int si_force_switch_to_arb_f0(struct radeon_device *rdev)
4022 {
4023         struct si_power_info *si_pi = si_get_pi(rdev);
4024         u32 tmp;
4025         int ret;
4026
4027         ret = si_read_smc_sram_dword(rdev, si_pi->arb_table_start,
4028                                      &tmp, si_pi->sram_end);
4029         if (ret)
4030                 return ret;
4031
4032         tmp = (tmp >> 24) & 0xff;
4033
4034         if (tmp == MC_CG_ARB_FREQ_F0)
4035                 return 0;
4036
4037         return ni_copy_and_switch_arb_sets(rdev, tmp, MC_CG_ARB_FREQ_F0);
4038 }
4039
4040 static u32 si_calculate_memory_refresh_rate(struct radeon_device *rdev,
4041                                             u32 engine_clock)
4042 {
4043         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4044         u32 dram_rows;
4045         u32 dram_refresh_rate;
4046         u32 mc_arb_rfsh_rate;
4047         u32 tmp = (RREG32(MC_ARB_RAMCFG) & NOOFROWS_MASK) >> NOOFROWS_SHIFT;
4048
4049         if (pi->mem_gddr5)
4050                 dram_rows = 1 << (tmp + 10);
4051         else
4052                 dram_rows = DDR3_DRAM_ROWS;
4053
4054         dram_refresh_rate = 1 << ((RREG32(MC_SEQ_MISC0) & 0x3) + 3);
4055         mc_arb_rfsh_rate = ((engine_clock * 10) * dram_refresh_rate / dram_rows - 32) / 64;
4056
4057         return mc_arb_rfsh_rate;
4058 }
4059
4060 static int si_populate_memory_timing_parameters(struct radeon_device *rdev,
4061                                                 struct rv7xx_pl *pl,
4062                                                 SMC_SIslands_MCArbDramTimingRegisterSet *arb_regs)
4063 {
4064         u32 dram_timing;
4065         u32 dram_timing2;
4066         u32 burst_time;
4067
4068         arb_regs->mc_arb_rfsh_rate =
4069                 (u8)si_calculate_memory_refresh_rate(rdev, pl->sclk);
4070
4071         radeon_atom_set_engine_dram_timings(rdev,
4072                                             pl->sclk,
4073                                             pl->mclk);
4074
4075         dram_timing  = RREG32(MC_ARB_DRAM_TIMING);
4076         dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2);
4077         burst_time = RREG32(MC_ARB_BURST_TIME) & STATE0_MASK;
4078
4079         arb_regs->mc_arb_dram_timing  = cpu_to_be32(dram_timing);
4080         arb_regs->mc_arb_dram_timing2 = cpu_to_be32(dram_timing2);
4081         arb_regs->mc_arb_burst_time = (u8)burst_time;
4082
4083         return 0;
4084 }
4085
4086 static int si_do_program_memory_timing_parameters(struct radeon_device *rdev,
4087                                                   struct radeon_ps *radeon_state,
4088                                                   unsigned int first_arb_set)
4089 {
4090         struct si_power_info *si_pi = si_get_pi(rdev);
4091         struct ni_ps *state = ni_get_ps(radeon_state);
4092         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4093         int i, ret = 0;
4094
4095         for (i = 0; i < state->performance_level_count; i++) {
4096                 ret = si_populate_memory_timing_parameters(rdev, &state->performance_levels[i], &arb_regs);
4097                 if (ret)
4098                         break;
4099                 ret = si_copy_bytes_to_smc(rdev,
4100                                            si_pi->arb_table_start +
4101                                            offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4102                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * (first_arb_set + i),
4103                                            (u8 *)&arb_regs,
4104                                            sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4105                                            si_pi->sram_end);
4106                 if (ret)
4107                         break;
4108         }
4109
4110         return ret;
4111 }
4112
4113 static int si_program_memory_timing_parameters(struct radeon_device *rdev,
4114                                                struct radeon_ps *radeon_new_state)
4115 {
4116         return si_do_program_memory_timing_parameters(rdev, radeon_new_state,
4117                                                       SISLANDS_DRIVER_STATE_ARB_INDEX);
4118 }
4119
4120 static int si_populate_initial_mvdd_value(struct radeon_device *rdev,
4121                                           struct SISLANDS_SMC_VOLTAGE_VALUE *voltage)
4122 {
4123         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4124         struct si_power_info *si_pi = si_get_pi(rdev);
4125
4126         if (pi->mvdd_control)
4127                 return si_populate_voltage_value(rdev, &si_pi->mvdd_voltage_table,
4128                                                  si_pi->mvdd_bootup_value, voltage);
4129
4130         return 0;
4131 }
4132
4133 static int si_populate_smc_initial_state(struct radeon_device *rdev,
4134                                          struct radeon_ps *radeon_initial_state,
4135                                          SISLANDS_SMC_STATETABLE *table)
4136 {
4137         struct ni_ps *initial_state = ni_get_ps(radeon_initial_state);
4138         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4139         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4140         struct si_power_info *si_pi = si_get_pi(rdev);
4141         u32 reg;
4142         int ret;
4143
4144         table->initialState.levels[0].mclk.vDLL_CNTL =
4145                 cpu_to_be32(si_pi->clock_registers.dll_cntl);
4146         table->initialState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4147                 cpu_to_be32(si_pi->clock_registers.mclk_pwrmgt_cntl);
4148         table->initialState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4149                 cpu_to_be32(si_pi->clock_registers.mpll_ad_func_cntl);
4150         table->initialState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4151                 cpu_to_be32(si_pi->clock_registers.mpll_dq_func_cntl);
4152         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL =
4153                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl);
4154         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4155                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_1);
4156         table->initialState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4157                 cpu_to_be32(si_pi->clock_registers.mpll_func_cntl_2);
4158         table->initialState.levels[0].mclk.vMPLL_SS =
4159                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4160         table->initialState.levels[0].mclk.vMPLL_SS2 =
4161                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4162
4163         table->initialState.levels[0].mclk.mclk_value =
4164                 cpu_to_be32(initial_state->performance_levels[0].mclk);
4165
4166         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4167                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl);
4168         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4169                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_2);
4170         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4171                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_3);
4172         table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4173                 cpu_to_be32(si_pi->clock_registers.cg_spll_func_cntl_4);
4174         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM =
4175                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum);
4176         table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2  =
4177                 cpu_to_be32(si_pi->clock_registers.cg_spll_spread_spectrum_2);
4178
4179         table->initialState.levels[0].sclk.sclk_value =
4180                 cpu_to_be32(initial_state->performance_levels[0].sclk);
4181
4182         table->initialState.levels[0].arbRefreshState =
4183                 SISLANDS_INITIAL_STATE_ARB_INDEX;
4184
4185         table->initialState.levels[0].ACIndex = 0;
4186
4187         ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4188                                         initial_state->performance_levels[0].vddc,
4189                                         &table->initialState.levels[0].vddc);
4190
4191         if (!ret) {
4192                 u16 std_vddc;
4193
4194                 ret = si_get_std_voltage_value(rdev,
4195                                                &table->initialState.levels[0].vddc,
4196                                                &std_vddc);
4197                 if (!ret)
4198                         si_populate_std_voltage_value(rdev, std_vddc,
4199                                                       table->initialState.levels[0].vddc.index,
4200                                                       &table->initialState.levels[0].std_vddc);
4201         }
4202
4203         if (eg_pi->vddci_control)
4204                 si_populate_voltage_value(rdev,
4205                                           &eg_pi->vddci_voltage_table,
4206                                           initial_state->performance_levels[0].vddci,
4207                                           &table->initialState.levels[0].vddci);
4208
4209         if (si_pi->vddc_phase_shed_control)
4210                 si_populate_phase_shedding_value(rdev,
4211                                                  &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4212                                                  initial_state->performance_levels[0].vddc,
4213                                                  initial_state->performance_levels[0].sclk,
4214                                                  initial_state->performance_levels[0].mclk,
4215                                                  &table->initialState.levels[0].vddc);
4216
4217         si_populate_initial_mvdd_value(rdev, &table->initialState.levels[0].mvdd);
4218
4219         reg = CG_R(0xffff) | CG_L(0);
4220         table->initialState.levels[0].aT = cpu_to_be32(reg);
4221
4222         table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp);
4223
4224         table->initialState.levels[0].gen2PCIE = (u8)si_pi->boot_pcie_gen;
4225
4226         if (pi->mem_gddr5) {
4227                 table->initialState.levels[0].strobeMode =
4228                         si_get_strobe_mode_settings(rdev,
4229                                                     initial_state->performance_levels[0].mclk);
4230
4231                 if (initial_state->performance_levels[0].mclk > pi->mclk_edc_enable_threshold)
4232                         table->initialState.levels[0].mcFlags = SISLANDS_SMC_MC_EDC_RD_FLAG | SISLANDS_SMC_MC_EDC_WR_FLAG;
4233                 else
4234                         table->initialState.levels[0].mcFlags =  0;
4235         }
4236
4237         table->initialState.levelCount = 1;
4238
4239         table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC;
4240
4241         table->initialState.levels[0].dpm2.MaxPS = 0;
4242         table->initialState.levels[0].dpm2.NearTDPDec = 0;
4243         table->initialState.levels[0].dpm2.AboveSafeInc = 0;
4244         table->initialState.levels[0].dpm2.BelowSafeInc = 0;
4245         table->initialState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4246
4247         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4248         table->initialState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4249
4250         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4251         table->initialState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4252
4253         return 0;
4254 }
4255
4256 static int si_populate_smc_acpi_state(struct radeon_device *rdev,
4257                                       SISLANDS_SMC_STATETABLE *table)
4258 {
4259         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4260         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4261         struct si_power_info *si_pi = si_get_pi(rdev);
4262         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4263         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4264         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4265         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4266         u32 dll_cntl = si_pi->clock_registers.dll_cntl;
4267         u32 mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4268         u32 mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4269         u32 mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4270         u32 mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4271         u32 mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4272         u32 mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4273         u32 reg;
4274         int ret;
4275
4276         table->ACPIState = table->initialState;
4277
4278         table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC;
4279
4280         if (pi->acpi_vddc) {
4281                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4282                                                 pi->acpi_vddc, &table->ACPIState.levels[0].vddc);
4283                 if (!ret) {
4284                         u16 std_vddc;
4285
4286                         ret = si_get_std_voltage_value(rdev,
4287                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4288                         if (!ret)
4289                                 si_populate_std_voltage_value(rdev, std_vddc,
4290                                                               table->ACPIState.levels[0].vddc.index,
4291                                                               &table->ACPIState.levels[0].std_vddc);
4292                 }
4293                 table->ACPIState.levels[0].gen2PCIE = si_pi->acpi_pcie_gen;
4294
4295                 if (si_pi->vddc_phase_shed_control) {
4296                         si_populate_phase_shedding_value(rdev,
4297                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4298                                                          pi->acpi_vddc,
4299                                                          0,
4300                                                          0,
4301                                                          &table->ACPIState.levels[0].vddc);
4302                 }
4303         } else {
4304                 ret = si_populate_voltage_value(rdev, &eg_pi->vddc_voltage_table,
4305                                                 pi->min_vddc_in_table, &table->ACPIState.levels[0].vddc);
4306                 if (!ret) {
4307                         u16 std_vddc;
4308
4309                         ret = si_get_std_voltage_value(rdev,
4310                                                        &table->ACPIState.levels[0].vddc, &std_vddc);
4311
4312                         if (!ret)
4313                                 si_populate_std_voltage_value(rdev, std_vddc,
4314                                                               table->ACPIState.levels[0].vddc.index,
4315                                                               &table->ACPIState.levels[0].std_vddc);
4316                 }
4317                 table->ACPIState.levels[0].gen2PCIE = (u8)r600_get_pcie_gen_support(rdev,
4318                                                                                     si_pi->sys_pcie_mask,
4319                                                                                     si_pi->boot_pcie_gen,
4320                                                                                     RADEON_PCIE_GEN1);
4321
4322                 if (si_pi->vddc_phase_shed_control)
4323                         si_populate_phase_shedding_value(rdev,
4324                                                          &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4325                                                          pi->min_vddc_in_table,
4326                                                          0,
4327                                                          0,
4328                                                          &table->ACPIState.levels[0].vddc);
4329         }
4330
4331         if (pi->acpi_vddc) {
4332                 if (eg_pi->acpi_vddci)
4333                         si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4334                                                   eg_pi->acpi_vddci,
4335                                                   &table->ACPIState.levels[0].vddci);
4336         }
4337
4338         mclk_pwrmgt_cntl |= MRDCK0_RESET | MRDCK1_RESET;
4339         mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4340
4341         dll_cntl &= ~(MRDCK0_BYPASS | MRDCK1_BYPASS);
4342
4343         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4344         spll_func_cntl_2 |= SCLK_MUX_SEL(4);
4345
4346         table->ACPIState.levels[0].mclk.vDLL_CNTL =
4347                 cpu_to_be32(dll_cntl);
4348         table->ACPIState.levels[0].mclk.vMCLK_PWRMGT_CNTL =
4349                 cpu_to_be32(mclk_pwrmgt_cntl);
4350         table->ACPIState.levels[0].mclk.vMPLL_AD_FUNC_CNTL =
4351                 cpu_to_be32(mpll_ad_func_cntl);
4352         table->ACPIState.levels[0].mclk.vMPLL_DQ_FUNC_CNTL =
4353                 cpu_to_be32(mpll_dq_func_cntl);
4354         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL =
4355                 cpu_to_be32(mpll_func_cntl);
4356         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_1 =
4357                 cpu_to_be32(mpll_func_cntl_1);
4358         table->ACPIState.levels[0].mclk.vMPLL_FUNC_CNTL_2 =
4359                 cpu_to_be32(mpll_func_cntl_2);
4360         table->ACPIState.levels[0].mclk.vMPLL_SS =
4361                 cpu_to_be32(si_pi->clock_registers.mpll_ss1);
4362         table->ACPIState.levels[0].mclk.vMPLL_SS2 =
4363                 cpu_to_be32(si_pi->clock_registers.mpll_ss2);
4364
4365         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL =
4366                 cpu_to_be32(spll_func_cntl);
4367         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 =
4368                 cpu_to_be32(spll_func_cntl_2);
4369         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 =
4370                 cpu_to_be32(spll_func_cntl_3);
4371         table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_4 =
4372                 cpu_to_be32(spll_func_cntl_4);
4373
4374         table->ACPIState.levels[0].mclk.mclk_value = 0;
4375         table->ACPIState.levels[0].sclk.sclk_value = 0;
4376
4377         si_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd);
4378
4379         if (eg_pi->dynamic_ac_timing)
4380                 table->ACPIState.levels[0].ACIndex = 0;
4381
4382         table->ACPIState.levels[0].dpm2.MaxPS = 0;
4383         table->ACPIState.levels[0].dpm2.NearTDPDec = 0;
4384         table->ACPIState.levels[0].dpm2.AboveSafeInc = 0;
4385         table->ACPIState.levels[0].dpm2.BelowSafeInc = 0;
4386         table->ACPIState.levels[0].dpm2.PwrEfficiencyRatio = 0;
4387
4388         reg = MIN_POWER_MASK | MAX_POWER_MASK;
4389         table->ACPIState.levels[0].SQPowerThrottle = cpu_to_be32(reg);
4390
4391         reg = MAX_POWER_DELTA_MASK | STI_SIZE_MASK | LTI_RATIO_MASK;
4392         table->ACPIState.levels[0].SQPowerThrottle_2 = cpu_to_be32(reg);
4393
4394         return 0;
4395 }
4396
4397 static int si_populate_ulv_state(struct radeon_device *rdev,
4398                                  SISLANDS_SMC_SWSTATE *state)
4399 {
4400         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4401         struct si_power_info *si_pi = si_get_pi(rdev);
4402         struct si_ulv_param *ulv = &si_pi->ulv;
4403         u32 sclk_in_sr = 1350; /* ??? */
4404         int ret;
4405
4406         ret = si_convert_power_level_to_smc(rdev, &ulv->pl,
4407                                             &state->levels[0]);
4408         if (!ret) {
4409                 if (eg_pi->sclk_deep_sleep) {
4410                         if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4411                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4412                         else
4413                                 state->levels[0].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4414                 }
4415                 if (ulv->one_pcie_lane_in_ulv)
4416                         state->flags |= PPSMC_SWSTATE_FLAG_PCIE_X1;
4417                 state->levels[0].arbRefreshState = (u8)(SISLANDS_ULV_STATE_ARB_INDEX);
4418                 state->levels[0].ACIndex = 1;
4419                 state->levels[0].std_vddc = state->levels[0].vddc;
4420                 state->levelCount = 1;
4421
4422                 state->flags |= PPSMC_SWSTATE_FLAG_DC;
4423         }
4424
4425         return ret;
4426 }
4427
4428 static int si_program_ulv_memory_timing_parameters(struct radeon_device *rdev)
4429 {
4430         struct si_power_info *si_pi = si_get_pi(rdev);
4431         struct si_ulv_param *ulv = &si_pi->ulv;
4432         SMC_SIslands_MCArbDramTimingRegisterSet arb_regs = { 0 };
4433         int ret;
4434
4435         ret = si_populate_memory_timing_parameters(rdev, &ulv->pl,
4436                                                    &arb_regs);
4437         if (ret)
4438                 return ret;
4439
4440         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_ulv_volt_change_delay,
4441                                    ulv->volt_change_delay);
4442
4443         ret = si_copy_bytes_to_smc(rdev,
4444                                    si_pi->arb_table_start +
4445                                    offsetof(SMC_SIslands_MCArbDramTimingRegisters, data) +
4446                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet) * SISLANDS_ULV_STATE_ARB_INDEX,
4447                                    (u8 *)&arb_regs,
4448                                    sizeof(SMC_SIslands_MCArbDramTimingRegisterSet),
4449                                    si_pi->sram_end);
4450
4451         return ret;
4452 }
4453
4454 static void si_get_mvdd_configuration(struct radeon_device *rdev)
4455 {
4456         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4457
4458         pi->mvdd_split_frequency = 30000;
4459 }
4460
4461 static int si_init_smc_table(struct radeon_device *rdev)
4462 {
4463         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4464         struct si_power_info *si_pi = si_get_pi(rdev);
4465         struct radeon_ps *radeon_boot_state = rdev->pm.dpm.boot_ps;
4466         const struct si_ulv_param *ulv = &si_pi->ulv;
4467         SISLANDS_SMC_STATETABLE  *table = &si_pi->smc_statetable;
4468         int ret;
4469         u32 lane_width;
4470         u32 vr_hot_gpio;
4471
4472         si_populate_smc_voltage_tables(rdev, table);
4473
4474         switch (rdev->pm.int_thermal_type) {
4475         case THERMAL_TYPE_SI:
4476         case THERMAL_TYPE_EMC2103_WITH_INTERNAL:
4477                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_INTERNAL;
4478                 break;
4479         case THERMAL_TYPE_NONE:
4480                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_NONE;
4481                 break;
4482         default:
4483                 table->thermalProtectType = PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL;
4484                 break;
4485         }
4486
4487         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_HARDWAREDC)
4488                 table->systemFlags |= PPSMC_SYSTEMFLAG_GPIO_DC;
4489
4490         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REGULATOR_HOT) {
4491                 if ((rdev->pdev->device != 0x6818) && (rdev->pdev->device != 0x6819))
4492                         table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT;
4493         }
4494
4495         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_STEPVDDC)
4496                 table->systemFlags |= PPSMC_SYSTEMFLAG_STEPVDDC;
4497
4498         if (pi->mem_gddr5)
4499                 table->systemFlags |= PPSMC_SYSTEMFLAG_GDDR5;
4500
4501         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_REVERT_GPIO5_POLARITY)
4502                 table->systemFlags |= PPSMC_EXTRAFLAGS_AC2DC_GPIO5_POLARITY_HIGH;
4503
4504         if (rdev->pm.dpm.platform_caps & ATOM_PP_PLATFORM_CAP_VRHOT_GPIO_CONFIGURABLE) {
4505                 table->systemFlags |= PPSMC_SYSTEMFLAG_REGULATOR_HOT_PROG_GPIO;
4506                 vr_hot_gpio = rdev->pm.dpm.backbias_response_time;
4507                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_vr_hot_gpio,
4508                                            vr_hot_gpio);
4509         }
4510
4511         ret = si_populate_smc_initial_state(rdev, radeon_boot_state, table);
4512         if (ret)
4513                 return ret;
4514
4515         ret = si_populate_smc_acpi_state(rdev, table);
4516         if (ret)
4517                 return ret;
4518
4519         table->driverState = table->initialState;
4520
4521         ret = si_do_program_memory_timing_parameters(rdev, radeon_boot_state,
4522                                                      SISLANDS_INITIAL_STATE_ARB_INDEX);
4523         if (ret)
4524                 return ret;
4525
4526         if (ulv->supported && ulv->pl.vddc) {
4527                 ret = si_populate_ulv_state(rdev, &table->ULVState);
4528                 if (ret)
4529                         return ret;
4530
4531                 ret = si_program_ulv_memory_timing_parameters(rdev);
4532                 if (ret)
4533                         return ret;
4534
4535                 WREG32(CG_ULV_CONTROL, ulv->cg_ulv_control);
4536                 WREG32(CG_ULV_PARAMETER, ulv->cg_ulv_parameter);
4537
4538                 lane_width = radeon_get_pcie_lanes(rdev);
4539                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
4540         } else {
4541                 table->ULVState = table->initialState;
4542         }
4543
4544         return si_copy_bytes_to_smc(rdev, si_pi->state_table_start,
4545                                     (u8 *)table, sizeof(SISLANDS_SMC_STATETABLE),
4546                                     si_pi->sram_end);
4547 }
4548
4549 static int si_calculate_sclk_params(struct radeon_device *rdev,
4550                                     u32 engine_clock,
4551                                     SISLANDS_SMC_SCLK_VALUE *sclk)
4552 {
4553         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4554         struct si_power_info *si_pi = si_get_pi(rdev);
4555         struct atom_clock_dividers dividers;
4556         u32 spll_func_cntl = si_pi->clock_registers.cg_spll_func_cntl;
4557         u32 spll_func_cntl_2 = si_pi->clock_registers.cg_spll_func_cntl_2;
4558         u32 spll_func_cntl_3 = si_pi->clock_registers.cg_spll_func_cntl_3;
4559         u32 spll_func_cntl_4 = si_pi->clock_registers.cg_spll_func_cntl_4;
4560         u32 cg_spll_spread_spectrum = si_pi->clock_registers.cg_spll_spread_spectrum;
4561         u32 cg_spll_spread_spectrum_2 = si_pi->clock_registers.cg_spll_spread_spectrum_2;
4562         u64 tmp;
4563         u32 reference_clock = rdev->clock.spll.reference_freq;
4564         u32 reference_divider;
4565         u32 fbdiv;
4566         int ret;
4567
4568         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
4569                                              engine_clock, false, &dividers);
4570         if (ret)
4571                 return ret;
4572
4573         reference_divider = 1 + dividers.ref_div;
4574
4575         tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384;
4576         do_div(tmp, reference_clock);
4577         fbdiv = (u32) tmp;
4578
4579         spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK);
4580         spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div);
4581         spll_func_cntl |= SPLL_PDIV_A(dividers.post_div);
4582
4583         spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK;
4584         spll_func_cntl_2 |= SCLK_MUX_SEL(2);
4585
4586         spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK;
4587         spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv);
4588         spll_func_cntl_3 |= SPLL_DITHEN;
4589
4590         if (pi->sclk_ss) {
4591                 struct radeon_atom_ss ss;
4592                 u32 vco_freq = engine_clock * dividers.post_div;
4593
4594                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4595                                                      ASIC_INTERNAL_ENGINE_SS, vco_freq)) {
4596                         u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate);
4597                         u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000);
4598
4599                         cg_spll_spread_spectrum &= ~CLK_S_MASK;
4600                         cg_spll_spread_spectrum |= CLK_S(clk_s);
4601                         cg_spll_spread_spectrum |= SSEN;
4602
4603                         cg_spll_spread_spectrum_2 &= ~CLK_V_MASK;
4604                         cg_spll_spread_spectrum_2 |= CLK_V(clk_v);
4605                 }
4606         }
4607
4608         sclk->sclk_value = engine_clock;
4609         sclk->vCG_SPLL_FUNC_CNTL = spll_func_cntl;
4610         sclk->vCG_SPLL_FUNC_CNTL_2 = spll_func_cntl_2;
4611         sclk->vCG_SPLL_FUNC_CNTL_3 = spll_func_cntl_3;
4612         sclk->vCG_SPLL_FUNC_CNTL_4 = spll_func_cntl_4;
4613         sclk->vCG_SPLL_SPREAD_SPECTRUM = cg_spll_spread_spectrum;
4614         sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cg_spll_spread_spectrum_2;
4615
4616         return 0;
4617 }
4618
4619 static int si_populate_sclk_value(struct radeon_device *rdev,
4620                                   u32 engine_clock,
4621                                   SISLANDS_SMC_SCLK_VALUE *sclk)
4622 {
4623         SISLANDS_SMC_SCLK_VALUE sclk_tmp;
4624         int ret;
4625
4626         ret = si_calculate_sclk_params(rdev, engine_clock, &sclk_tmp);
4627         if (!ret) {
4628                 sclk->sclk_value = cpu_to_be32(sclk_tmp.sclk_value);
4629                 sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL);
4630                 sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_2);
4631                 sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_3);
4632                 sclk->vCG_SPLL_FUNC_CNTL_4 = cpu_to_be32(sclk_tmp.vCG_SPLL_FUNC_CNTL_4);
4633                 sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM);
4634                 sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(sclk_tmp.vCG_SPLL_SPREAD_SPECTRUM_2);
4635         }
4636
4637         return ret;
4638 }
4639
4640 static int si_populate_mclk_value(struct radeon_device *rdev,
4641                                   u32 engine_clock,
4642                                   u32 memory_clock,
4643                                   SISLANDS_SMC_MCLK_VALUE *mclk,
4644                                   bool strobe_mode,
4645                                   bool dll_state_on)
4646 {
4647         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4648         struct si_power_info *si_pi = si_get_pi(rdev);
4649         u32  dll_cntl = si_pi->clock_registers.dll_cntl;
4650         u32  mclk_pwrmgt_cntl = si_pi->clock_registers.mclk_pwrmgt_cntl;
4651         u32  mpll_ad_func_cntl = si_pi->clock_registers.mpll_ad_func_cntl;
4652         u32  mpll_dq_func_cntl = si_pi->clock_registers.mpll_dq_func_cntl;
4653         u32  mpll_func_cntl = si_pi->clock_registers.mpll_func_cntl;
4654         u32  mpll_func_cntl_1 = si_pi->clock_registers.mpll_func_cntl_1;
4655         u32  mpll_func_cntl_2 = si_pi->clock_registers.mpll_func_cntl_2;
4656         u32  mpll_ss1 = si_pi->clock_registers.mpll_ss1;
4657         u32  mpll_ss2 = si_pi->clock_registers.mpll_ss2;
4658         struct atom_mpll_param mpll_param;
4659         int ret;
4660
4661         ret = radeon_atom_get_memory_pll_dividers(rdev, memory_clock, strobe_mode, &mpll_param);
4662         if (ret)
4663                 return ret;
4664
4665         mpll_func_cntl &= ~BWCTRL_MASK;
4666         mpll_func_cntl |= BWCTRL(mpll_param.bwcntl);
4667
4668         mpll_func_cntl_1 &= ~(CLKF_MASK | CLKFRAC_MASK | VCO_MODE_MASK);
4669         mpll_func_cntl_1 |= CLKF(mpll_param.clkf) |
4670                 CLKFRAC(mpll_param.clkfrac) | VCO_MODE(mpll_param.vco_mode);
4671
4672         mpll_ad_func_cntl &= ~YCLK_POST_DIV_MASK;
4673         mpll_ad_func_cntl |= YCLK_POST_DIV(mpll_param.post_div);
4674
4675         if (pi->mem_gddr5) {
4676                 mpll_dq_func_cntl &= ~(YCLK_SEL_MASK | YCLK_POST_DIV_MASK);
4677                 mpll_dq_func_cntl |= YCLK_SEL(mpll_param.yclk_sel) |
4678                         YCLK_POST_DIV(mpll_param.post_div);
4679         }
4680
4681         if (pi->mclk_ss) {
4682                 struct radeon_atom_ss ss;
4683                 u32 freq_nom;
4684                 u32 tmp;
4685                 u32 reference_clock = rdev->clock.mpll.reference_freq;
4686
4687                 if (pi->mem_gddr5)
4688                         freq_nom = memory_clock * 4;
4689                 else
4690                         freq_nom = memory_clock * 2;
4691
4692                 tmp = freq_nom / reference_clock;
4693                 tmp = tmp * tmp;
4694                 if (radeon_atombios_get_asic_ss_info(rdev, &ss,
4695                                                      ASIC_INTERNAL_MEMORY_SS, freq_nom)) {
4696                         u32 clks = reference_clock * 5 / ss.rate;
4697                         u32 clkv = (u32)((((131 * ss.percentage * ss.rate) / 100) * tmp) / freq_nom);
4698
4699                         mpll_ss1 &= ~CLKV_MASK;
4700                         mpll_ss1 |= CLKV(clkv);
4701
4702                         mpll_ss2 &= ~CLKS_MASK;
4703                         mpll_ss2 |= CLKS(clks);
4704                 }
4705         }
4706
4707         mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK;
4708         mclk_pwrmgt_cntl |= DLL_SPEED(mpll_param.dll_speed);
4709
4710         if (dll_state_on)
4711                 mclk_pwrmgt_cntl |= MRDCK0_PDNB | MRDCK1_PDNB;
4712         else
4713                 mclk_pwrmgt_cntl &= ~(MRDCK0_PDNB | MRDCK1_PDNB);
4714
4715         mclk->mclk_value = cpu_to_be32(memory_clock);
4716         mclk->vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl);
4717         mclk->vMPLL_FUNC_CNTL_1 = cpu_to_be32(mpll_func_cntl_1);
4718         mclk->vMPLL_FUNC_CNTL_2 = cpu_to_be32(mpll_func_cntl_2);
4719         mclk->vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl);
4720         mclk->vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl);
4721         mclk->vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl);
4722         mclk->vDLL_CNTL = cpu_to_be32(dll_cntl);
4723         mclk->vMPLL_SS = cpu_to_be32(mpll_ss1);
4724         mclk->vMPLL_SS2 = cpu_to_be32(mpll_ss2);
4725
4726         return 0;
4727 }
4728
4729 static void si_populate_smc_sp(struct radeon_device *rdev,
4730                                struct radeon_ps *radeon_state,
4731                                SISLANDS_SMC_SWSTATE *smc_state)
4732 {
4733         struct ni_ps *ps = ni_get_ps(radeon_state);
4734         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4735         int i;
4736
4737         for (i = 0; i < ps->performance_level_count - 1; i++)
4738                 smc_state->levels[i].bSP = cpu_to_be32(pi->dsp);
4739
4740         smc_state->levels[ps->performance_level_count - 1].bSP =
4741                 cpu_to_be32(pi->psp);
4742 }
4743
4744 static int si_convert_power_level_to_smc(struct radeon_device *rdev,
4745                                          struct rv7xx_pl *pl,
4746                                          SISLANDS_SMC_HW_PERFORMANCE_LEVEL *level)
4747 {
4748         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4749         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4750         struct si_power_info *si_pi = si_get_pi(rdev);
4751         int ret;
4752         bool dll_state_on;
4753         u16 std_vddc;
4754         bool gmc_pg = false;
4755
4756         if (eg_pi->pcie_performance_request &&
4757             (si_pi->force_pcie_gen != RADEON_PCIE_GEN_INVALID))
4758                 level->gen2PCIE = (u8)si_pi->force_pcie_gen;
4759         else
4760                 level->gen2PCIE = (u8)pl->pcie_gen;
4761
4762         ret = si_populate_sclk_value(rdev, pl->sclk, &level->sclk);
4763         if (ret)
4764                 return ret;
4765
4766         level->mcFlags =  0;
4767
4768         if (pi->mclk_stutter_mode_threshold &&
4769             (pl->mclk <= pi->mclk_stutter_mode_threshold) &&
4770             !eg_pi->uvd_enabled &&
4771             (RREG32(DPG_PIPE_STUTTER_CONTROL) & STUTTER_ENABLE) &&
4772             (rdev->pm.dpm.new_active_crtc_count <= 2)) {
4773                 level->mcFlags |= SISLANDS_SMC_MC_STUTTER_EN;
4774
4775                 if (gmc_pg)
4776                         level->mcFlags |= SISLANDS_SMC_MC_PG_EN;
4777         }
4778
4779         if (pi->mem_gddr5) {
4780                 if (pl->mclk > pi->mclk_edc_enable_threshold)
4781                         level->mcFlags |= SISLANDS_SMC_MC_EDC_RD_FLAG;
4782
4783                 if (pl->mclk > eg_pi->mclk_edc_wr_enable_threshold)
4784                         level->mcFlags |= SISLANDS_SMC_MC_EDC_WR_FLAG;
4785
4786                 level->strobeMode = si_get_strobe_mode_settings(rdev, pl->mclk);
4787
4788                 if (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) {
4789                         if (si_get_mclk_frequency_ratio(pl->mclk, true) >=
4790                             ((RREG32(MC_SEQ_MISC7) >> 16) & 0xf))
4791                                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4792                         else
4793                                 dll_state_on = ((RREG32(MC_SEQ_MISC6) >> 1) & 0x1) ? true : false;
4794                 } else {
4795                         dll_state_on = false;
4796                 }
4797         } else {
4798                 level->strobeMode = si_get_strobe_mode_settings(rdev,
4799                                                                 pl->mclk);
4800
4801                 dll_state_on = ((RREG32(MC_SEQ_MISC5) >> 1) & 0x1) ? true : false;
4802         }
4803
4804         ret = si_populate_mclk_value(rdev,
4805                                      pl->sclk,
4806                                      pl->mclk,
4807                                      &level->mclk,
4808                                      (level->strobeMode & SISLANDS_SMC_STROBE_ENABLE) != 0, dll_state_on);
4809         if (ret)
4810                 return ret;
4811
4812         ret = si_populate_voltage_value(rdev,
4813                                         &eg_pi->vddc_voltage_table,
4814                                         pl->vddc, &level->vddc);
4815         if (ret)
4816                 return ret;
4817
4818
4819         ret = si_get_std_voltage_value(rdev, &level->vddc, &std_vddc);
4820         if (ret)
4821                 return ret;
4822
4823         ret = si_populate_std_voltage_value(rdev, std_vddc,
4824                                             level->vddc.index, &level->std_vddc);
4825         if (ret)
4826                 return ret;
4827
4828         if (eg_pi->vddci_control) {
4829                 ret = si_populate_voltage_value(rdev, &eg_pi->vddci_voltage_table,
4830                                                 pl->vddci, &level->vddci);
4831                 if (ret)
4832                         return ret;
4833         }
4834
4835         if (si_pi->vddc_phase_shed_control) {
4836                 ret = si_populate_phase_shedding_value(rdev,
4837                                                        &rdev->pm.dpm.dyn_state.phase_shedding_limits_table,
4838                                                        pl->vddc,
4839                                                        pl->sclk,
4840                                                        pl->mclk,
4841                                                        &level->vddc);
4842                 if (ret)
4843                         return ret;
4844         }
4845
4846         level->MaxPoweredUpCU = si_pi->max_cu;
4847
4848         ret = si_populate_mvdd_value(rdev, pl->mclk, &level->mvdd);
4849
4850         return ret;
4851 }
4852
4853 static int si_populate_smc_t(struct radeon_device *rdev,
4854                              struct radeon_ps *radeon_state,
4855                              SISLANDS_SMC_SWSTATE *smc_state)
4856 {
4857         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
4858         struct ni_ps *state = ni_get_ps(radeon_state);
4859         u32 a_t;
4860         u32 t_l, t_h;
4861         u32 high_bsp;
4862         int i, ret;
4863
4864         if (state->performance_level_count >= 9)
4865                 return -EINVAL;
4866
4867         if (state->performance_level_count < 2) {
4868                 a_t = CG_R(0xffff) | CG_L(0);
4869                 smc_state->levels[0].aT = cpu_to_be32(a_t);
4870                 return 0;
4871         }
4872
4873         smc_state->levels[0].aT = cpu_to_be32(0);
4874
4875         for (i = 0; i <= state->performance_level_count - 2; i++) {
4876                 ret = r600_calculate_at(
4877                         (50 / SISLANDS_MAX_HARDWARE_POWERLEVELS) * 100 * (i + 1),
4878                         100 * R600_AH_DFLT,
4879                         state->performance_levels[i + 1].sclk,
4880                         state->performance_levels[i].sclk,
4881                         &t_l,
4882                         &t_h);
4883
4884                 if (ret) {
4885                         t_h = (i + 1) * 1000 - 50 * R600_AH_DFLT;
4886                         t_l = (i + 1) * 1000 + 50 * R600_AH_DFLT;
4887                 }
4888
4889                 a_t = be32_to_cpu(smc_state->levels[i].aT) & ~CG_R_MASK;
4890                 a_t |= CG_R(t_l * pi->bsp / 20000);
4891                 smc_state->levels[i].aT = cpu_to_be32(a_t);
4892
4893                 high_bsp = (i == state->performance_level_count - 2) ?
4894                         pi->pbsp : pi->bsp;
4895                 a_t = CG_R(0xffff) | CG_L(t_h * high_bsp / 20000);
4896                 smc_state->levels[i + 1].aT = cpu_to_be32(a_t);
4897         }
4898
4899         return 0;
4900 }
4901
4902 static int si_disable_ulv(struct radeon_device *rdev)
4903 {
4904         struct si_power_info *si_pi = si_get_pi(rdev);
4905         struct si_ulv_param *ulv = &si_pi->ulv;
4906
4907         if (ulv->supported)
4908                 return (si_send_msg_to_smc(rdev, PPSMC_MSG_DisableULV) == PPSMC_Result_OK) ?
4909                         0 : -EINVAL;
4910
4911         return 0;
4912 }
4913
4914 static bool si_is_state_ulv_compatible(struct radeon_device *rdev,
4915                                        struct radeon_ps *radeon_state)
4916 {
4917         const struct si_power_info *si_pi = si_get_pi(rdev);
4918         const struct si_ulv_param *ulv = &si_pi->ulv;
4919         const struct ni_ps *state = ni_get_ps(radeon_state);
4920         int i;
4921
4922         if (state->performance_levels[0].mclk != ulv->pl.mclk)
4923                 return false;
4924
4925         /* XXX validate against display requirements! */
4926
4927         for (i = 0; i < rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count; i++) {
4928                 if (rdev->clock.current_dispclk <=
4929                     rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].clk) {
4930                         if (ulv->pl.vddc <
4931                             rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[i].v)
4932                                 return false;
4933                 }
4934         }
4935
4936         if ((radeon_state->vclk != 0) || (radeon_state->dclk != 0))
4937                 return false;
4938
4939         return true;
4940 }
4941
4942 static int si_set_power_state_conditionally_enable_ulv(struct radeon_device *rdev,
4943                                                        struct radeon_ps *radeon_new_state)
4944 {
4945         const struct si_power_info *si_pi = si_get_pi(rdev);
4946         const struct si_ulv_param *ulv = &si_pi->ulv;
4947
4948         if (ulv->supported) {
4949                 if (si_is_state_ulv_compatible(rdev, radeon_new_state))
4950                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_EnableULV) == PPSMC_Result_OK) ?
4951                                 0 : -EINVAL;
4952         }
4953         return 0;
4954 }
4955
4956 static int si_convert_power_state_to_smc(struct radeon_device *rdev,
4957                                          struct radeon_ps *radeon_state,
4958                                          SISLANDS_SMC_SWSTATE *smc_state)
4959 {
4960         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
4961         struct ni_power_info *ni_pi = ni_get_pi(rdev);
4962         struct si_power_info *si_pi = si_get_pi(rdev);
4963         struct ni_ps *state = ni_get_ps(radeon_state);
4964         int i, ret;
4965         u32 threshold;
4966         u32 sclk_in_sr = 1350; /* ??? */
4967
4968         if (state->performance_level_count > SISLANDS_MAX_HARDWARE_POWERLEVELS)
4969                 return -EINVAL;
4970
4971         threshold = state->performance_levels[state->performance_level_count-1].sclk * 100 / 100;
4972
4973         if (radeon_state->vclk && radeon_state->dclk) {
4974                 eg_pi->uvd_enabled = true;
4975                 if (eg_pi->smu_uvd_hs)
4976                         smc_state->flags |= PPSMC_SWSTATE_FLAG_UVD;
4977         } else {
4978                 eg_pi->uvd_enabled = false;
4979         }
4980
4981         if (state->dc_compatible)
4982                 smc_state->flags |= PPSMC_SWSTATE_FLAG_DC;
4983
4984         smc_state->levelCount = 0;
4985         for (i = 0; i < state->performance_level_count; i++) {
4986                 if (eg_pi->sclk_deep_sleep) {
4987                         if ((i == 0) || si_pi->sclk_deep_sleep_above_low) {
4988                                 if (sclk_in_sr <= SCLK_MIN_DEEPSLEEP_FREQ)
4989                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_BYPASS;
4990                                 else
4991                                         smc_state->levels[i].stateFlags |= PPSMC_STATEFLAG_DEEPSLEEP_THROTTLE;
4992                         }
4993                 }
4994
4995                 ret = si_convert_power_level_to_smc(rdev, &state->performance_levels[i],
4996                                                     &smc_state->levels[i]);
4997                 smc_state->levels[i].arbRefreshState =
4998                         (u8)(SISLANDS_DRIVER_STATE_ARB_INDEX + i);
4999
5000                 if (ret)
5001                         return ret;
5002
5003                 if (ni_pi->enable_power_containment)
5004                         smc_state->levels[i].displayWatermark =
5005                                 (state->performance_levels[i].sclk < threshold) ?
5006                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5007                 else
5008                         smc_state->levels[i].displayWatermark = (i < 2) ?
5009                                 PPSMC_DISPLAY_WATERMARK_LOW : PPSMC_DISPLAY_WATERMARK_HIGH;
5010
5011                 if (eg_pi->dynamic_ac_timing)
5012                         smc_state->levels[i].ACIndex = SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i;
5013                 else
5014                         smc_state->levels[i].ACIndex = 0;
5015
5016                 smc_state->levelCount++;
5017         }
5018
5019         si_write_smc_soft_register(rdev,
5020                                    SI_SMC_SOFT_REGISTER_watermark_threshold,
5021                                    threshold / 512);
5022
5023         si_populate_smc_sp(rdev, radeon_state, smc_state);
5024
5025         ret = si_populate_power_containment_values(rdev, radeon_state, smc_state);
5026         if (ret)
5027                 ni_pi->enable_power_containment = false;
5028
5029         ret = si_populate_sq_ramping_values(rdev, radeon_state, smc_state);
5030         if (ret)
5031                 ni_pi->enable_sq_ramping = false;
5032
5033         return si_populate_smc_t(rdev, radeon_state, smc_state);
5034 }
5035
5036 static int si_upload_sw_state(struct radeon_device *rdev,
5037                               struct radeon_ps *radeon_new_state)
5038 {
5039         struct si_power_info *si_pi = si_get_pi(rdev);
5040         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5041         int ret;
5042         u32 address = si_pi->state_table_start +
5043                 offsetof(SISLANDS_SMC_STATETABLE, driverState);
5044         u32 state_size = sizeof(SISLANDS_SMC_SWSTATE) +
5045                 ((new_state->performance_level_count - 1) *
5046                  sizeof(SISLANDS_SMC_HW_PERFORMANCE_LEVEL));
5047         SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.driverState;
5048
5049         memset(smc_state, 0, state_size);
5050
5051         ret = si_convert_power_state_to_smc(rdev, radeon_new_state, smc_state);
5052         if (ret)
5053                 return ret;
5054
5055         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5056                                    state_size, si_pi->sram_end);
5057
5058         return ret;
5059 }
5060
5061 static int si_upload_ulv_state(struct radeon_device *rdev)
5062 {
5063         struct si_power_info *si_pi = si_get_pi(rdev);
5064         struct si_ulv_param *ulv = &si_pi->ulv;
5065         int ret = 0;
5066
5067         if (ulv->supported && ulv->pl.vddc) {
5068                 u32 address = si_pi->state_table_start +
5069                         offsetof(SISLANDS_SMC_STATETABLE, ULVState);
5070                 SISLANDS_SMC_SWSTATE *smc_state = &si_pi->smc_statetable.ULVState;
5071                 u32 state_size = sizeof(SISLANDS_SMC_SWSTATE);
5072
5073                 memset(smc_state, 0, state_size);
5074
5075                 ret = si_populate_ulv_state(rdev, smc_state);
5076                 if (!ret)
5077                         ret = si_copy_bytes_to_smc(rdev, address, (u8 *)smc_state,
5078                                                    state_size, si_pi->sram_end);
5079         }
5080
5081         return ret;
5082 }
5083
5084 static int si_upload_smc_data(struct radeon_device *rdev)
5085 {
5086         struct radeon_crtc *radeon_crtc = NULL;
5087         int i;
5088
5089         if (rdev->pm.dpm.new_active_crtc_count == 0)
5090                 return 0;
5091
5092         for (i = 0; i < rdev->num_crtc; i++) {
5093                 if (rdev->pm.dpm.new_active_crtcs & (1 << i)) {
5094                         radeon_crtc = rdev->mode_info.crtcs[i];
5095                         break;
5096                 }
5097         }
5098
5099         if (radeon_crtc == NULL)
5100                 return 0;
5101
5102         if (radeon_crtc->line_time <= 0)
5103                 return 0;
5104
5105         if (si_write_smc_soft_register(rdev,
5106                                        SI_SMC_SOFT_REGISTER_crtc_index,
5107                                        radeon_crtc->crtc_id) != PPSMC_Result_OK)
5108                 return 0;
5109
5110         if (si_write_smc_soft_register(rdev,
5111                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_min,
5112                                        radeon_crtc->wm_high / radeon_crtc->line_time) != PPSMC_Result_OK)
5113                 return 0;
5114
5115         if (si_write_smc_soft_register(rdev,
5116                                        SI_SMC_SOFT_REGISTER_mclk_change_block_cp_max,
5117                                        radeon_crtc->wm_low / radeon_crtc->line_time) != PPSMC_Result_OK)
5118                 return 0;
5119
5120         return 0;
5121 }
5122
5123 static int si_set_mc_special_registers(struct radeon_device *rdev,
5124                                        struct si_mc_reg_table *table)
5125 {
5126         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5127         u8 i, j, k;
5128         u32 temp_reg;
5129
5130         for (i = 0, j = table->last; i < table->last; i++) {
5131                 if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5132                         return -EINVAL;
5133                 switch (table->mc_reg_address[i].s1 << 2) {
5134                 case MC_SEQ_MISC1:
5135                         temp_reg = RREG32(MC_PMG_CMD_EMRS);
5136                         table->mc_reg_address[j].s1 = MC_PMG_CMD_EMRS >> 2;
5137                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5138                         for (k = 0; k < table->num_entries; k++)
5139                                 table->mc_reg_table_entry[k].mc_data[j] =
5140                                         ((temp_reg & 0xffff0000)) |
5141                                         ((table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16);
5142                         j++;
5143                         if (j >= SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5144                                 return -EINVAL;
5145
5146                         temp_reg = RREG32(MC_PMG_CMD_MRS);
5147                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS >> 2;
5148                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5149                         for (k = 0; k < table->num_entries; k++) {
5150                                 table->mc_reg_table_entry[k].mc_data[j] =
5151                                         (temp_reg & 0xffff0000) |
5152                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5153                                 if (!pi->mem_gddr5)
5154                                         table->mc_reg_table_entry[k].mc_data[j] |= 0x100;
5155                         }
5156                         j++;
5157                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5158                                 return -EINVAL;
5159
5160                         if (!pi->mem_gddr5) {
5161                                 table->mc_reg_address[j].s1 = MC_PMG_AUTO_CMD >> 2;
5162                                 table->mc_reg_address[j].s0 = MC_PMG_AUTO_CMD >> 2;
5163                                 for (k = 0; k < table->num_entries; k++)
5164                                         table->mc_reg_table_entry[k].mc_data[j] =
5165                                                 (table->mc_reg_table_entry[k].mc_data[i] & 0xffff0000) >> 16;
5166                                 j++;
5167                                 if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5168                                         return -EINVAL;
5169                         }
5170                         break;
5171                 case MC_SEQ_RESERVE_M:
5172                         temp_reg = RREG32(MC_PMG_CMD_MRS1);
5173                         table->mc_reg_address[j].s1 = MC_PMG_CMD_MRS1 >> 2;
5174                         table->mc_reg_address[j].s0 = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5175                         for(k = 0; k < table->num_entries; k++)
5176                                 table->mc_reg_table_entry[k].mc_data[j] =
5177                                         (temp_reg & 0xffff0000) |
5178                                         (table->mc_reg_table_entry[k].mc_data[i] & 0x0000ffff);
5179                         j++;
5180                         if (j > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5181                                 return -EINVAL;
5182                         break;
5183                 default:
5184                         break;
5185                 }
5186         }
5187
5188         table->last = j;
5189
5190         return 0;
5191 }
5192
5193 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg)
5194 {
5195         bool result = true;
5196
5197         switch (in_reg) {
5198         case  MC_SEQ_RAS_TIMING >> 2:
5199                 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2;
5200                 break;
5201         case MC_SEQ_CAS_TIMING >> 2:
5202                 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2;
5203                 break;
5204         case MC_SEQ_MISC_TIMING >> 2:
5205                 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2;
5206                 break;
5207         case MC_SEQ_MISC_TIMING2 >> 2:
5208                 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2;
5209                 break;
5210         case MC_SEQ_RD_CTL_D0 >> 2:
5211                 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2;
5212                 break;
5213         case MC_SEQ_RD_CTL_D1 >> 2:
5214                 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2;
5215                 break;
5216         case MC_SEQ_WR_CTL_D0 >> 2:
5217                 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2;
5218                 break;
5219         case MC_SEQ_WR_CTL_D1 >> 2:
5220                 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2;
5221                 break;
5222         case MC_PMG_CMD_EMRS >> 2:
5223                 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2;
5224                 break;
5225         case MC_PMG_CMD_MRS >> 2:
5226                 *out_reg = MC_SEQ_PMG_CMD_MRS_LP >> 2;
5227                 break;
5228         case MC_PMG_CMD_MRS1 >> 2:
5229                 *out_reg = MC_SEQ_PMG_CMD_MRS1_LP >> 2;
5230                 break;
5231         case MC_SEQ_PMG_TIMING >> 2:
5232                 *out_reg = MC_SEQ_PMG_TIMING_LP >> 2;
5233                 break;
5234         case MC_PMG_CMD_MRS2 >> 2:
5235                 *out_reg = MC_SEQ_PMG_CMD_MRS2_LP >> 2;
5236                 break;
5237         case MC_SEQ_WR_CTL_2 >> 2:
5238                 *out_reg = MC_SEQ_WR_CTL_2_LP >> 2;
5239                 break;
5240         default:
5241                 result = false;
5242                 break;
5243         }
5244
5245         return result;
5246 }
5247
5248 static void si_set_valid_flag(struct si_mc_reg_table *table)
5249 {
5250         u8 i, j;
5251
5252         for (i = 0; i < table->last; i++) {
5253                 for (j = 1; j < table->num_entries; j++) {
5254                         if (table->mc_reg_table_entry[j-1].mc_data[i] != table->mc_reg_table_entry[j].mc_data[i]) {
5255                                 table->valid_flag |= 1 << i;
5256                                 break;
5257                         }
5258                 }
5259         }
5260 }
5261
5262 static void si_set_s0_mc_reg_index(struct si_mc_reg_table *table)
5263 {
5264         u32 i;
5265         u16 address;
5266
5267         for (i = 0; i < table->last; i++)
5268                 table->mc_reg_address[i].s0 = si_check_s0_mc_reg_index(table->mc_reg_address[i].s1, &address) ?
5269                         address : table->mc_reg_address[i].s1;
5270
5271 }
5272
5273 static int si_copy_vbios_mc_reg_table(struct atom_mc_reg_table *table,
5274                                       struct si_mc_reg_table *si_table)
5275 {
5276         u8 i, j;
5277
5278         if (table->last > SMC_SISLANDS_MC_REGISTER_ARRAY_SIZE)
5279                 return -EINVAL;
5280         if (table->num_entries > MAX_AC_TIMING_ENTRIES)
5281                 return -EINVAL;
5282
5283         for (i = 0; i < table->last; i++)
5284                 si_table->mc_reg_address[i].s1 = table->mc_reg_address[i].s1;
5285         si_table->last = table->last;
5286
5287         for (i = 0; i < table->num_entries; i++) {
5288                 si_table->mc_reg_table_entry[i].mclk_max =
5289                         table->mc_reg_table_entry[i].mclk_max;
5290                 for (j = 0; j < table->last; j++) {
5291                         si_table->mc_reg_table_entry[i].mc_data[j] =
5292                                 table->mc_reg_table_entry[i].mc_data[j];
5293                 }
5294         }
5295         si_table->num_entries = table->num_entries;
5296
5297         return 0;
5298 }
5299
5300 static int si_initialize_mc_reg_table(struct radeon_device *rdev)
5301 {
5302         struct si_power_info *si_pi = si_get_pi(rdev);
5303         struct atom_mc_reg_table *table;
5304         struct si_mc_reg_table *si_table = &si_pi->mc_reg_table;
5305         u8 module_index = rv770_get_memory_module_index(rdev);
5306         int ret;
5307
5308         table = kzalloc(sizeof(struct atom_mc_reg_table), GFP_KERNEL);
5309         if (!table)
5310                 return -ENOMEM;
5311
5312         WREG32(MC_SEQ_RAS_TIMING_LP, RREG32(MC_SEQ_RAS_TIMING));
5313         WREG32(MC_SEQ_CAS_TIMING_LP, RREG32(MC_SEQ_CAS_TIMING));
5314         WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING));
5315         WREG32(MC_SEQ_MISC_TIMING2_LP, RREG32(MC_SEQ_MISC_TIMING2));
5316         WREG32(MC_SEQ_PMG_CMD_EMRS_LP, RREG32(MC_PMG_CMD_EMRS));
5317         WREG32(MC_SEQ_PMG_CMD_MRS_LP, RREG32(MC_PMG_CMD_MRS));
5318         WREG32(MC_SEQ_PMG_CMD_MRS1_LP, RREG32(MC_PMG_CMD_MRS1));
5319         WREG32(MC_SEQ_WR_CTL_D0_LP, RREG32(MC_SEQ_WR_CTL_D0));
5320         WREG32(MC_SEQ_WR_CTL_D1_LP, RREG32(MC_SEQ_WR_CTL_D1));
5321         WREG32(MC_SEQ_RD_CTL_D0_LP, RREG32(MC_SEQ_RD_CTL_D0));
5322         WREG32(MC_SEQ_RD_CTL_D1_LP, RREG32(MC_SEQ_RD_CTL_D1));
5323         WREG32(MC_SEQ_PMG_TIMING_LP, RREG32(MC_SEQ_PMG_TIMING));
5324         WREG32(MC_SEQ_PMG_CMD_MRS2_LP, RREG32(MC_PMG_CMD_MRS2));
5325         WREG32(MC_SEQ_WR_CTL_2_LP, RREG32(MC_SEQ_WR_CTL_2));
5326
5327         ret = radeon_atom_init_mc_reg_table(rdev, module_index, table);
5328         if (ret)
5329                 goto init_mc_done;
5330
5331         ret = si_copy_vbios_mc_reg_table(table, si_table);
5332         if (ret)
5333                 goto init_mc_done;
5334
5335         si_set_s0_mc_reg_index(si_table);
5336
5337         ret = si_set_mc_special_registers(rdev, si_table);
5338         if (ret)
5339                 goto init_mc_done;
5340
5341         si_set_valid_flag(si_table);
5342
5343 init_mc_done:
5344         kfree(table);
5345
5346         return ret;
5347
5348 }
5349
5350 static void si_populate_mc_reg_addresses(struct radeon_device *rdev,
5351                                          SMC_SIslands_MCRegisters *mc_reg_table)
5352 {
5353         struct si_power_info *si_pi = si_get_pi(rdev);
5354         u32 i, j;
5355
5356         for (i = 0, j = 0; j < si_pi->mc_reg_table.last; j++) {
5357                 if (si_pi->mc_reg_table.valid_flag & (1 << j)) {
5358                         if (i >= SMC_NISLANDS_MC_REGISTER_ARRAY_SIZE)
5359                                 break;
5360                         mc_reg_table->address[i].s0 =
5361                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s0);
5362                         mc_reg_table->address[i].s1 =
5363                                 cpu_to_be16(si_pi->mc_reg_table.mc_reg_address[j].s1);
5364                         i++;
5365                 }
5366         }
5367         mc_reg_table->last = (u8)i;
5368 }
5369
5370 static void si_convert_mc_registers(const struct si_mc_reg_entry *entry,
5371                                     SMC_SIslands_MCRegisterSet *data,
5372                                     u32 num_entries, u32 valid_flag)
5373 {
5374         u32 i, j;
5375
5376         for(i = 0, j = 0; j < num_entries; j++) {
5377                 if (valid_flag & (1 << j)) {
5378                         data->value[i] = cpu_to_be32(entry->mc_data[j]);
5379                         i++;
5380                 }
5381         }
5382 }
5383
5384 static void si_convert_mc_reg_table_entry_to_smc(struct radeon_device *rdev,
5385                                                  struct rv7xx_pl *pl,
5386                                                  SMC_SIslands_MCRegisterSet *mc_reg_table_data)
5387 {
5388         struct si_power_info *si_pi = si_get_pi(rdev);
5389         u32 i = 0;
5390
5391         for (i = 0; i < si_pi->mc_reg_table.num_entries; i++) {
5392                 if (pl->mclk <= si_pi->mc_reg_table.mc_reg_table_entry[i].mclk_max)
5393                         break;
5394         }
5395
5396         if ((i == si_pi->mc_reg_table.num_entries) && (i > 0))
5397                 --i;
5398
5399         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[i],
5400                                 mc_reg_table_data, si_pi->mc_reg_table.last,
5401                                 si_pi->mc_reg_table.valid_flag);
5402 }
5403
5404 static void si_convert_mc_reg_table_to_smc(struct radeon_device *rdev,
5405                                            struct radeon_ps *radeon_state,
5406                                            SMC_SIslands_MCRegisters *mc_reg_table)
5407 {
5408         struct ni_ps *state = ni_get_ps(radeon_state);
5409         int i;
5410
5411         for (i = 0; i < state->performance_level_count; i++) {
5412                 si_convert_mc_reg_table_entry_to_smc(rdev,
5413                                                      &state->performance_levels[i],
5414                                                      &mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT + i]);
5415         }
5416 }
5417
5418 static int si_populate_mc_reg_table(struct radeon_device *rdev,
5419                                     struct radeon_ps *radeon_boot_state)
5420 {
5421         struct ni_ps *boot_state = ni_get_ps(radeon_boot_state);
5422         struct si_power_info *si_pi = si_get_pi(rdev);
5423         struct si_ulv_param *ulv = &si_pi->ulv;
5424         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5425
5426         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5427
5428         si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_seq_index, 1);
5429
5430         si_populate_mc_reg_addresses(rdev, smc_mc_reg_table);
5431
5432         si_convert_mc_reg_table_entry_to_smc(rdev, &boot_state->performance_levels[0],
5433                                              &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_INITIAL_SLOT]);
5434
5435         si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5436                                 &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ACPI_SLOT],
5437                                 si_pi->mc_reg_table.last,
5438                                 si_pi->mc_reg_table.valid_flag);
5439
5440         if (ulv->supported && ulv->pl.vddc != 0)
5441                 si_convert_mc_reg_table_entry_to_smc(rdev, &ulv->pl,
5442                                                      &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT]);
5443         else
5444                 si_convert_mc_registers(&si_pi->mc_reg_table.mc_reg_table_entry[0],
5445                                         &smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_ULV_SLOT],
5446                                         si_pi->mc_reg_table.last,
5447                                         si_pi->mc_reg_table.valid_flag);
5448
5449         si_convert_mc_reg_table_to_smc(rdev, radeon_boot_state, smc_mc_reg_table);
5450
5451         return si_copy_bytes_to_smc(rdev, si_pi->mc_reg_table_start,
5452                                     (u8 *)smc_mc_reg_table,
5453                                     sizeof(SMC_SIslands_MCRegisters), si_pi->sram_end);
5454 }
5455
5456 static int si_upload_mc_reg_table(struct radeon_device *rdev,
5457                                   struct radeon_ps *radeon_new_state)
5458 {
5459         struct ni_ps *new_state = ni_get_ps(radeon_new_state);
5460         struct si_power_info *si_pi = si_get_pi(rdev);
5461         u32 address = si_pi->mc_reg_table_start +
5462                 offsetof(SMC_SIslands_MCRegisters,
5463                          data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT]);
5464         SMC_SIslands_MCRegisters *smc_mc_reg_table = &si_pi->smc_mc_reg_table;
5465
5466         memset(smc_mc_reg_table, 0, sizeof(SMC_SIslands_MCRegisters));
5467
5468         si_convert_mc_reg_table_to_smc(rdev, radeon_new_state, smc_mc_reg_table);
5469
5470
5471         return si_copy_bytes_to_smc(rdev, address,
5472                                     (u8 *)&smc_mc_reg_table->data[SISLANDS_MCREGISTERTABLE_FIRST_DRIVERSTATE_SLOT],
5473                                     sizeof(SMC_SIslands_MCRegisterSet) * new_state->performance_level_count,
5474                                     si_pi->sram_end);
5475
5476 }
5477
5478 static void si_enable_voltage_control(struct radeon_device *rdev, bool enable)
5479 {
5480         if (enable)
5481                 WREG32_P(GENERAL_PWRMGT, VOLT_PWRMGT_EN, ~VOLT_PWRMGT_EN);
5482         else
5483                 WREG32_P(GENERAL_PWRMGT, 0, ~VOLT_PWRMGT_EN);
5484 }
5485
5486 static enum radeon_pcie_gen si_get_maximum_link_speed(struct radeon_device *rdev,
5487                                                       struct radeon_ps *radeon_state)
5488 {
5489         struct ni_ps *state = ni_get_ps(radeon_state);
5490         int i;
5491         u16 pcie_speed, max_speed = 0;
5492
5493         for (i = 0; i < state->performance_level_count; i++) {
5494                 pcie_speed = state->performance_levels[i].pcie_gen;
5495                 if (max_speed < pcie_speed)
5496                         max_speed = pcie_speed;
5497         }
5498         return max_speed;
5499 }
5500
5501 static u16 si_get_current_pcie_speed(struct radeon_device *rdev)
5502 {
5503         u32 speed_cntl;
5504
5505         speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL) & LC_CURRENT_DATA_RATE_MASK;
5506         speed_cntl >>= LC_CURRENT_DATA_RATE_SHIFT;
5507
5508         return (u16)speed_cntl;
5509 }
5510
5511 static void si_request_link_speed_change_before_state_change(struct radeon_device *rdev,
5512                                                              struct radeon_ps *radeon_new_state,
5513                                                              struct radeon_ps *radeon_current_state)
5514 {
5515         struct si_power_info *si_pi = si_get_pi(rdev);
5516         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5517         enum radeon_pcie_gen current_link_speed;
5518
5519         if (si_pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID)
5520                 current_link_speed = si_get_maximum_link_speed(rdev, radeon_current_state);
5521         else
5522                 current_link_speed = si_pi->force_pcie_gen;
5523
5524         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
5525         si_pi->pspp_notify_required = false;
5526         if (target_link_speed > current_link_speed) {
5527                 switch (target_link_speed) {
5528 #if defined(CONFIG_ACPI)
5529                 case RADEON_PCIE_GEN3:
5530                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN3, false) == 0)
5531                                 break;
5532                         si_pi->force_pcie_gen = RADEON_PCIE_GEN2;
5533                         if (current_link_speed == RADEON_PCIE_GEN2)
5534                                 break;
5535                 case RADEON_PCIE_GEN2:
5536                         if (radeon_acpi_pcie_performance_request(rdev, PCIE_PERF_REQ_PECI_GEN2, false) == 0)
5537                                 break;
5538 #endif
5539                 default:
5540                         si_pi->force_pcie_gen = si_get_current_pcie_speed(rdev);
5541                         break;
5542                 }
5543         } else {
5544                 if (target_link_speed < current_link_speed)
5545                         si_pi->pspp_notify_required = true;
5546         }
5547 }
5548
5549 static void si_notify_link_speed_change_after_state_change(struct radeon_device *rdev,
5550                                                            struct radeon_ps *radeon_new_state,
5551                                                            struct radeon_ps *radeon_current_state)
5552 {
5553         struct si_power_info *si_pi = si_get_pi(rdev);
5554         enum radeon_pcie_gen target_link_speed = si_get_maximum_link_speed(rdev, radeon_new_state);
5555         u8 request;
5556
5557         if (si_pi->pspp_notify_required) {
5558                 if (target_link_speed == RADEON_PCIE_GEN3)
5559                         request = PCIE_PERF_REQ_PECI_GEN3;
5560                 else if (target_link_speed == RADEON_PCIE_GEN2)
5561                         request = PCIE_PERF_REQ_PECI_GEN2;
5562                 else
5563                         request = PCIE_PERF_REQ_PECI_GEN1;
5564
5565                 if ((request == PCIE_PERF_REQ_PECI_GEN1) &&
5566                     (si_get_current_pcie_speed(rdev) > 0))
5567                         return;
5568
5569 #if defined(CONFIG_ACPI)
5570                 radeon_acpi_pcie_performance_request(rdev, request, false);
5571 #endif
5572         }
5573 }
5574
5575 #if 0
5576 static int si_ds_request(struct radeon_device *rdev,
5577                          bool ds_status_on, u32 count_write)
5578 {
5579         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5580
5581         if (eg_pi->sclk_deep_sleep) {
5582                 if (ds_status_on)
5583                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_CancelThrottleOVRDSCLKDS) ==
5584                                 PPSMC_Result_OK) ?
5585                                 0 : -EINVAL;
5586                 else
5587                         return (si_send_msg_to_smc(rdev, PPSMC_MSG_ThrottleOVRDSCLKDS) ==
5588                                 PPSMC_Result_OK) ? 0 : -EINVAL;
5589         }
5590         return 0;
5591 }
5592 #endif
5593
5594 static void si_set_max_cu_value(struct radeon_device *rdev)
5595 {
5596         struct si_power_info *si_pi = si_get_pi(rdev);
5597
5598         if (rdev->family == CHIP_VERDE) {
5599                 switch (rdev->pdev->device) {
5600                 case 0x6820:
5601                 case 0x6825:
5602                 case 0x6821:
5603                 case 0x6823:
5604                 case 0x6827:
5605                         si_pi->max_cu = 10;
5606                         break;
5607                 case 0x682D:
5608                 case 0x6824:
5609                 case 0x682F:
5610                 case 0x6826:
5611                         si_pi->max_cu = 8;
5612                         break;
5613                 case 0x6828:
5614                 case 0x6830:
5615                 case 0x6831:
5616                 case 0x6838:
5617                 case 0x6839:
5618                 case 0x683D:
5619                         si_pi->max_cu = 10;
5620                         break;
5621                 case 0x683B:
5622                 case 0x683F:
5623                 case 0x6829:
5624                         si_pi->max_cu = 8;
5625                         break;
5626                 default:
5627                         si_pi->max_cu = 0;
5628                         break;
5629                 }
5630         } else {
5631                 si_pi->max_cu = 0;
5632         }
5633 }
5634
5635 static int si_patch_single_dependency_table_based_on_leakage(struct radeon_device *rdev,
5636                                                              struct radeon_clock_voltage_dependency_table *table)
5637 {
5638         u32 i;
5639         int j;
5640         u16 leakage_voltage;
5641
5642         if (table) {
5643                 for (i = 0; i < table->count; i++) {
5644                         switch (si_get_leakage_voltage_from_leakage_index(rdev,
5645                                                                           table->entries[i].v,
5646                                                                           &leakage_voltage)) {
5647                         case 0:
5648                                 table->entries[i].v = leakage_voltage;
5649                                 break;
5650                         case -EAGAIN:
5651                                 return -EINVAL;
5652                         case -EINVAL:
5653                         default:
5654                                 break;
5655                         }
5656                 }
5657
5658                 for (j = (table->count - 2); j >= 0; j--) {
5659                         table->entries[j].v = (table->entries[j].v <= table->entries[j + 1].v) ?
5660                                 table->entries[j].v : table->entries[j + 1].v;
5661                 }
5662         }
5663         return 0;
5664 }
5665
5666 static int si_patch_dependency_tables_based_on_leakage(struct radeon_device *rdev)
5667 {
5668         int ret = 0;
5669
5670         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5671                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_sclk);
5672         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5673                                                                 &rdev->pm.dpm.dyn_state.vddc_dependency_on_mclk);
5674         ret = si_patch_single_dependency_table_based_on_leakage(rdev,
5675                                                                 &rdev->pm.dpm.dyn_state.vddci_dependency_on_mclk);
5676         return ret;
5677 }
5678
5679 static void si_set_pcie_lane_width_in_smc(struct radeon_device *rdev,
5680                                           struct radeon_ps *radeon_new_state,
5681                                           struct radeon_ps *radeon_current_state)
5682 {
5683         u32 lane_width;
5684         u32 new_lane_width =
5685                 (radeon_new_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5686         u32 current_lane_width =
5687                 (radeon_current_state->caps & ATOM_PPLIB_PCIE_LINK_WIDTH_MASK) >> ATOM_PPLIB_PCIE_LINK_WIDTH_SHIFT;
5688
5689         if (new_lane_width != current_lane_width) {
5690                 radeon_set_pcie_lanes(rdev, new_lane_width);
5691                 lane_width = radeon_get_pcie_lanes(rdev);
5692                 si_write_smc_soft_register(rdev, SI_SMC_SOFT_REGISTER_non_ulv_pcie_link_width, lane_width);
5693         }
5694 }
5695
5696 void si_dpm_setup_asic(struct radeon_device *rdev)
5697 {
5698         rv770_get_memory_type(rdev);
5699         si_read_clock_registers(rdev);
5700         si_enable_acpi_power_management(rdev);
5701 }
5702
5703 static int si_set_thermal_temperature_range(struct radeon_device *rdev,
5704                                         int min_temp, int max_temp)
5705 {
5706         int low_temp = 0 * 1000;
5707         int high_temp = 255 * 1000;
5708
5709         if (low_temp < min_temp)
5710                 low_temp = min_temp;
5711         if (high_temp > max_temp)
5712                 high_temp = max_temp;
5713         if (high_temp < low_temp) {
5714                 DRM_ERROR("invalid thermal range: %d - %d\n", low_temp, high_temp);
5715                 return -EINVAL;
5716         }
5717
5718         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTH(high_temp / 1000), ~DIG_THERM_INTH_MASK);
5719         WREG32_P(CG_THERMAL_INT, DIG_THERM_INTL(low_temp / 1000), ~DIG_THERM_INTL_MASK);
5720         WREG32_P(CG_THERMAL_CTRL, DIG_THERM_DPM(high_temp / 1000), ~DIG_THERM_DPM_MASK);
5721
5722         rdev->pm.dpm.thermal.min_temp = low_temp;
5723         rdev->pm.dpm.thermal.max_temp = high_temp;
5724
5725         return 0;
5726 }
5727
5728 int si_dpm_enable(struct radeon_device *rdev)
5729 {
5730         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5731         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5732         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5733         int ret;
5734
5735         if (si_is_smc_running(rdev))
5736                 return -EINVAL;
5737         if (pi->voltage_control)
5738                 si_enable_voltage_control(rdev, true);
5739         if (pi->mvdd_control)
5740                 si_get_mvdd_configuration(rdev);
5741         if (pi->voltage_control) {
5742                 ret = si_construct_voltage_tables(rdev);
5743                 if (ret) {
5744                         DRM_ERROR("si_construct_voltage_tables failed\n");
5745                         return ret;
5746                 }
5747         }
5748         if (eg_pi->dynamic_ac_timing) {
5749                 ret = si_initialize_mc_reg_table(rdev);
5750                 if (ret)
5751                         eg_pi->dynamic_ac_timing = false;
5752         }
5753         if (pi->dynamic_ss)
5754                 si_enable_spread_spectrum(rdev, true);
5755         if (pi->thermal_protection)
5756                 si_enable_thermal_protection(rdev, true);
5757         si_setup_bsp(rdev);
5758         si_program_git(rdev);
5759         si_program_tp(rdev);
5760         si_program_tpp(rdev);
5761         si_program_sstp(rdev);
5762         si_enable_display_gap(rdev);
5763         si_program_vc(rdev);
5764         ret = si_upload_firmware(rdev);
5765         if (ret) {
5766                 DRM_ERROR("si_upload_firmware failed\n");
5767                 return ret;
5768         }
5769         ret = si_process_firmware_header(rdev);
5770         if (ret) {
5771                 DRM_ERROR("si_process_firmware_header failed\n");
5772                 return ret;
5773         }
5774         ret = si_initial_switch_from_arb_f0_to_f1(rdev);
5775         if (ret) {
5776                 DRM_ERROR("si_initial_switch_from_arb_f0_to_f1 failed\n");
5777                 return ret;
5778         }
5779         ret = si_init_smc_table(rdev);
5780         if (ret) {
5781                 DRM_ERROR("si_init_smc_table failed\n");
5782                 return ret;
5783         }
5784         ret = si_init_smc_spll_table(rdev);
5785         if (ret) {
5786                 DRM_ERROR("si_init_smc_spll_table failed\n");
5787                 return ret;
5788         }
5789         ret = si_init_arb_table_index(rdev);
5790         if (ret) {
5791                 DRM_ERROR("si_init_arb_table_index failed\n");
5792                 return ret;
5793         }
5794         if (eg_pi->dynamic_ac_timing) {
5795                 ret = si_populate_mc_reg_table(rdev, boot_ps);
5796                 if (ret) {
5797                         DRM_ERROR("si_populate_mc_reg_table failed\n");
5798                         return ret;
5799                 }
5800         }
5801         ret = si_initialize_smc_cac_tables(rdev);
5802         if (ret) {
5803                 DRM_ERROR("si_initialize_smc_cac_tables failed\n");
5804                 return ret;
5805         }
5806         ret = si_initialize_hardware_cac_manager(rdev);
5807         if (ret) {
5808                 DRM_ERROR("si_initialize_hardware_cac_manager failed\n");
5809                 return ret;
5810         }
5811         ret = si_initialize_smc_dte_tables(rdev);
5812         if (ret) {
5813                 DRM_ERROR("si_initialize_smc_dte_tables failed\n");
5814                 return ret;
5815         }
5816         ret = si_populate_smc_tdp_limits(rdev, boot_ps);
5817         if (ret) {
5818                 DRM_ERROR("si_populate_smc_tdp_limits failed\n");
5819                 return ret;
5820         }
5821         ret = si_populate_smc_tdp_limits_2(rdev, boot_ps);
5822         if (ret) {
5823                 DRM_ERROR("si_populate_smc_tdp_limits_2 failed\n");
5824                 return ret;
5825         }
5826         si_program_response_times(rdev);
5827         si_program_ds_registers(rdev);
5828         si_dpm_start_smc(rdev);
5829         ret = si_notify_smc_display_change(rdev, false);
5830         if (ret) {
5831                 DRM_ERROR("si_notify_smc_display_change failed\n");
5832                 return ret;
5833         }
5834         si_enable_sclk_control(rdev, true);
5835         si_start_dpm(rdev);
5836
5837         if (rdev->irq.installed &&
5838             r600_is_internal_thermal_sensor(rdev->pm.int_thermal_type)) {
5839                 PPSMC_Result result;
5840
5841                 ret = si_set_thermal_temperature_range(rdev, R600_TEMP_RANGE_MIN, R600_TEMP_RANGE_MAX);
5842                 if (ret)
5843                         return ret;
5844                 rdev->irq.dpm_thermal = true;
5845                 radeon_irq_set(rdev);
5846                 result = si_send_msg_to_smc(rdev, PPSMC_MSG_EnableThermalInterrupt);
5847
5848                 if (result != PPSMC_Result_OK)
5849                         DRM_DEBUG_KMS("Could not enable thermal interrupts.\n");
5850         }
5851
5852         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, true);
5853
5854         ni_update_current_ps(rdev, boot_ps);
5855
5856         return 0;
5857 }
5858
5859 void si_dpm_disable(struct radeon_device *rdev)
5860 {
5861         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
5862         struct radeon_ps *boot_ps = rdev->pm.dpm.boot_ps;
5863
5864         if (!si_is_smc_running(rdev))
5865                 return;
5866         si_disable_ulv(rdev);
5867         si_clear_vc(rdev);
5868         if (pi->thermal_protection)
5869                 si_enable_thermal_protection(rdev, false);
5870         si_enable_power_containment(rdev, boot_ps, false);
5871         si_enable_smc_cac(rdev, boot_ps, false);
5872         si_enable_spread_spectrum(rdev, false);
5873         si_enable_auto_throttle_source(rdev, RADEON_DPM_AUTO_THROTTLE_SRC_THERMAL, false);
5874         si_stop_dpm(rdev);
5875         si_reset_to_default(rdev);
5876         si_dpm_stop_smc(rdev);
5877         si_force_switch_to_arb_f0(rdev);
5878
5879         ni_update_current_ps(rdev, boot_ps);
5880 }
5881
5882 int si_dpm_pre_set_power_state(struct radeon_device *rdev)
5883 {
5884         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5885         struct radeon_ps requested_ps = *rdev->pm.dpm.requested_ps;
5886         struct radeon_ps *new_ps = &requested_ps;
5887
5888         ni_update_requested_ps(rdev, new_ps);
5889
5890         si_apply_state_adjust_rules(rdev, &eg_pi->requested_rps);
5891
5892         return 0;
5893 }
5894
5895 static int si_power_control_set_level(struct radeon_device *rdev)
5896 {
5897         struct radeon_ps *new_ps = rdev->pm.dpm.requested_ps;
5898         int ret;
5899
5900         ret = si_restrict_performance_levels_before_switch(rdev);
5901         if (ret)
5902                 return ret;
5903         ret = si_halt_smc(rdev);
5904         if (ret)
5905                 return ret;
5906         ret = si_populate_smc_tdp_limits(rdev, new_ps);
5907         if (ret)
5908                 return ret;
5909         ret = si_populate_smc_tdp_limits_2(rdev, new_ps);
5910         if (ret)
5911                 return ret;
5912         ret = si_resume_smc(rdev);
5913         if (ret)
5914                 return ret;
5915         ret = si_set_sw_state(rdev);
5916         if (ret)
5917                 return ret;
5918         return 0;
5919 }
5920
5921 int si_dpm_set_power_state(struct radeon_device *rdev)
5922 {
5923         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
5924         struct radeon_ps *new_ps = &eg_pi->requested_rps;
5925         struct radeon_ps *old_ps = &eg_pi->current_rps;
5926         int ret;
5927
5928         ret = si_disable_ulv(rdev);
5929         if (ret) {
5930                 DRM_ERROR("si_disable_ulv failed\n");
5931                 return ret;
5932         }
5933         ret = si_restrict_performance_levels_before_switch(rdev);
5934         if (ret) {
5935                 DRM_ERROR("si_restrict_performance_levels_before_switch failed\n");
5936                 return ret;
5937         }
5938         if (eg_pi->pcie_performance_request)
5939                 si_request_link_speed_change_before_state_change(rdev, new_ps, old_ps);
5940         ni_set_uvd_clock_before_set_eng_clock(rdev, new_ps, old_ps);
5941         ret = si_enable_power_containment(rdev, new_ps, false);
5942         if (ret) {
5943                 DRM_ERROR("si_enable_power_containment failed\n");
5944                 return ret;
5945         }
5946         ret = si_enable_smc_cac(rdev, new_ps, false);
5947         if (ret) {
5948                 DRM_ERROR("si_enable_smc_cac failed\n");
5949                 return ret;
5950         }
5951         ret = si_halt_smc(rdev);
5952         if (ret) {
5953                 DRM_ERROR("si_halt_smc failed\n");
5954                 return ret;
5955         }
5956         ret = si_upload_sw_state(rdev, new_ps);
5957         if (ret) {
5958                 DRM_ERROR("si_upload_sw_state failed\n");
5959                 return ret;
5960         }
5961         ret = si_upload_smc_data(rdev);
5962         if (ret) {
5963                 DRM_ERROR("si_upload_smc_data failed\n");
5964                 return ret;
5965         }
5966         ret = si_upload_ulv_state(rdev);
5967         if (ret) {
5968                 DRM_ERROR("si_upload_ulv_state failed\n");
5969                 return ret;
5970         }
5971         if (eg_pi->dynamic_ac_timing) {
5972                 ret = si_upload_mc_reg_table(rdev, new_ps);
5973                 if (ret) {
5974                         DRM_ERROR("si_upload_mc_reg_table failed\n");
5975                         return ret;
5976                 }
5977         }
5978         ret = si_program_memory_timing_parameters(rdev, new_ps);
5979         if (ret) {
5980                 DRM_ERROR("si_program_memory_timing_parameters failed\n");
5981                 return ret;
5982         }
5983         si_set_pcie_lane_width_in_smc(rdev, new_ps, old_ps);
5984
5985         ret = si_resume_smc(rdev);
5986         if (ret) {
5987                 DRM_ERROR("si_resume_smc failed\n");
5988                 return ret;
5989         }
5990         ret = si_set_sw_state(rdev);
5991         if (ret) {
5992                 DRM_ERROR("si_set_sw_state failed\n");
5993                 return ret;
5994         }
5995         ni_set_uvd_clock_after_set_eng_clock(rdev, new_ps, old_ps);
5996         if (eg_pi->pcie_performance_request)
5997                 si_notify_link_speed_change_after_state_change(rdev, new_ps, old_ps);
5998         ret = si_set_power_state_conditionally_enable_ulv(rdev, new_ps);
5999         if (ret) {
6000                 DRM_ERROR("si_set_power_state_conditionally_enable_ulv failed\n");
6001                 return ret;
6002         }
6003         ret = si_enable_smc_cac(rdev, new_ps, true);
6004         if (ret) {
6005                 DRM_ERROR("si_enable_smc_cac failed\n");
6006                 return ret;
6007         }
6008         ret = si_enable_power_containment(rdev, new_ps, true);
6009         if (ret) {
6010                 DRM_ERROR("si_enable_power_containment failed\n");
6011                 return ret;
6012         }
6013
6014         ret = si_power_control_set_level(rdev);
6015         if (ret) {
6016                 DRM_ERROR("si_power_control_set_level failed\n");
6017                 return ret;
6018         }
6019
6020 #if 0
6021         /* XXX */
6022         ret = si_dpm_force_performance_level(rdev, RADEON_DPM_FORCED_LEVEL_AUTO);
6023         if (ret) {
6024                 DRM_ERROR("si_dpm_force_performance_level failed\n");
6025                 return ret;
6026         }
6027 #else
6028         rdev->pm.dpm.forced_level = RADEON_DPM_FORCED_LEVEL_AUTO;
6029 #endif
6030
6031         return 0;
6032 }
6033
6034 void si_dpm_post_set_power_state(struct radeon_device *rdev)
6035 {
6036         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6037         struct radeon_ps *new_ps = &eg_pi->requested_rps;
6038
6039         ni_update_current_ps(rdev, new_ps);
6040 }
6041
6042
6043 void si_dpm_reset_asic(struct radeon_device *rdev)
6044 {
6045         si_restrict_performance_levels_before_switch(rdev);
6046         si_disable_ulv(rdev);
6047         si_set_boot_state(rdev);
6048 }
6049
6050 void si_dpm_display_configuration_changed(struct radeon_device *rdev)
6051 {
6052         si_program_display_gap(rdev);
6053 }
6054
6055 union power_info {
6056         struct _ATOM_POWERPLAY_INFO info;
6057         struct _ATOM_POWERPLAY_INFO_V2 info_2;
6058         struct _ATOM_POWERPLAY_INFO_V3 info_3;
6059         struct _ATOM_PPLIB_POWERPLAYTABLE pplib;
6060         struct _ATOM_PPLIB_POWERPLAYTABLE2 pplib2;
6061         struct _ATOM_PPLIB_POWERPLAYTABLE3 pplib3;
6062 };
6063
6064 union pplib_clock_info {
6065         struct _ATOM_PPLIB_R600_CLOCK_INFO r600;
6066         struct _ATOM_PPLIB_RS780_CLOCK_INFO rs780;
6067         struct _ATOM_PPLIB_EVERGREEN_CLOCK_INFO evergreen;
6068         struct _ATOM_PPLIB_SUMO_CLOCK_INFO sumo;
6069         struct _ATOM_PPLIB_SI_CLOCK_INFO si;
6070 };
6071
6072 union pplib_power_state {
6073         struct _ATOM_PPLIB_STATE v1;
6074         struct _ATOM_PPLIB_STATE_V2 v2;
6075 };
6076
6077 static void si_parse_pplib_non_clock_info(struct radeon_device *rdev,
6078                                           struct radeon_ps *rps,
6079                                           struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info,
6080                                           u8 table_rev)
6081 {
6082         rps->caps = le32_to_cpu(non_clock_info->ulCapsAndSettings);
6083         rps->class = le16_to_cpu(non_clock_info->usClassification);
6084         rps->class2 = le16_to_cpu(non_clock_info->usClassification2);
6085
6086         if (ATOM_PPLIB_NONCLOCKINFO_VER1 < table_rev) {
6087                 rps->vclk = le32_to_cpu(non_clock_info->ulVCLK);
6088                 rps->dclk = le32_to_cpu(non_clock_info->ulDCLK);
6089         } else if (r600_is_uvd_state(rps->class, rps->class2)) {
6090                 rps->vclk = RV770_DEFAULT_VCLK_FREQ;
6091                 rps->dclk = RV770_DEFAULT_DCLK_FREQ;
6092         } else {
6093                 rps->vclk = 0;
6094                 rps->dclk = 0;
6095         }
6096
6097         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT)
6098                 rdev->pm.dpm.boot_ps = rps;
6099         if (rps->class & ATOM_PPLIB_CLASSIFICATION_UVDSTATE)
6100                 rdev->pm.dpm.uvd_ps = rps;
6101 }
6102
6103 static void si_parse_pplib_clock_info(struct radeon_device *rdev,
6104                                       struct radeon_ps *rps, int index,
6105                                       union pplib_clock_info *clock_info)
6106 {
6107         struct rv7xx_power_info *pi = rv770_get_pi(rdev);
6108         struct evergreen_power_info *eg_pi = evergreen_get_pi(rdev);
6109         struct si_power_info *si_pi = si_get_pi(rdev);
6110         struct ni_ps *ps = ni_get_ps(rps);
6111         u16 leakage_voltage;
6112         struct rv7xx_pl *pl = &ps->performance_levels[index];
6113         int ret;
6114
6115         ps->performance_level_count = index + 1;
6116
6117         pl->sclk = le16_to_cpu(clock_info->si.usEngineClockLow);
6118         pl->sclk |= clock_info->si.ucEngineClockHigh << 16;
6119         pl->mclk = le16_to_cpu(clock_info->si.usMemoryClockLow);
6120         pl->mclk |= clock_info->si.ucMemoryClockHigh << 16;
6121
6122         pl->vddc = le16_to_cpu(clock_info->si.usVDDC);
6123         pl->vddci = le16_to_cpu(clock_info->si.usVDDCI);
6124         pl->flags = le32_to_cpu(clock_info->si.ulFlags);
6125         pl->pcie_gen = r600_get_pcie_gen_support(rdev,
6126                                                  si_pi->sys_pcie_mask,
6127                                                  si_pi->boot_pcie_gen,
6128                                                  clock_info->si.ucPCIEGen);
6129
6130         /* patch up vddc if necessary */
6131         ret = si_get_leakage_voltage_from_leakage_index(rdev, pl->vddc,
6132                                                         &leakage_voltage);
6133         if (ret == 0)
6134                 pl->vddc = leakage_voltage;
6135
6136         if (rps->class & ATOM_PPLIB_CLASSIFICATION_ACPI) {
6137                 pi->acpi_vddc = pl->vddc;
6138                 eg_pi->acpi_vddci = pl->vddci;
6139                 si_pi->acpi_pcie_gen = pl->pcie_gen;
6140         }
6141
6142         if ((rps->class2 & ATOM_PPLIB_CLASSIFICATION2_ULV) &&
6143             index == 0) {
6144                 /* XXX disable for A0 tahiti */
6145                 si_pi->ulv.supported = true;
6146                 si_pi->ulv.pl = *pl;
6147                 si_pi->ulv.one_pcie_lane_in_ulv = false;
6148                 si_pi->ulv.volt_change_delay = SISLANDS_ULVVOLTAGECHANGEDELAY_DFLT;
6149                 si_pi->ulv.cg_ulv_parameter = SISLANDS_CGULVPARAMETER_DFLT;
6150                 si_pi->ulv.cg_ulv_control = SISLANDS_CGULVCONTROL_DFLT;
6151         }
6152
6153         if (pi->min_vddc_in_table > pl->vddc)
6154                 pi->min_vddc_in_table = pl->vddc;
6155
6156         if (pi->max_vddc_in_table < pl->vddc)
6157                 pi->max_vddc_in_table = pl->vddc;
6158
6159         /* patch up boot state */
6160         if (rps->class & ATOM_PPLIB_CLASSIFICATION_BOOT) {
6161                 u16 vddc, vddci, mvdd;
6162                 radeon_atombios_get_default_voltages(rdev, &vddc, &vddci, &mvdd);
6163                 pl->mclk = rdev->clock.default_mclk;
6164                 pl->sclk = rdev->clock.default_sclk;
6165                 pl->vddc = vddc;
6166                 pl->vddci = vddci;
6167                 si_pi->mvdd_bootup_value = mvdd;
6168         }
6169
6170         if ((rps->class & ATOM_PPLIB_CLASSIFICATION_UI_MASK) ==
6171             ATOM_PPLIB_CLASSIFICATION_UI_PERFORMANCE) {
6172                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.sclk = pl->sclk;
6173                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.mclk = pl->mclk;
6174                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddc = pl->vddc;
6175                 rdev->pm.dpm.dyn_state.max_clock_voltage_on_ac.vddci = pl->vddci;
6176         }
6177 }
6178
6179 static int si_parse_power_table(struct radeon_device *rdev)
6180 {
6181         struct radeon_mode_info *mode_info = &rdev->mode_info;
6182         struct _ATOM_PPLIB_NONCLOCK_INFO *non_clock_info;
6183         union pplib_power_state *power_state;
6184         int i, j, k, non_clock_array_index, clock_array_index;
6185         union pplib_clock_info *clock_info;
6186         struct _StateArray *state_array;
6187         struct _ClockInfoArray *clock_info_array;
6188         struct _NonClockInfoArray *non_clock_info_array;
6189         union power_info *power_info;
6190         int index = GetIndexIntoMasterTable(DATA, PowerPlayInfo);
6191         u16 data_offset;
6192         u8 frev, crev;
6193         u8 *power_state_offset;
6194         struct ni_ps *ps;
6195
6196         if (!atom_parse_data_header(mode_info->atom_context, index, NULL,
6197                                    &frev, &crev, &data_offset))
6198                 return -EINVAL;
6199         power_info = (union power_info *)(mode_info->atom_context->bios + data_offset);
6200
6201         state_array = (struct _StateArray *)
6202                 (mode_info->atom_context->bios + data_offset +
6203                  le16_to_cpu(power_info->pplib.usStateArrayOffset));
6204         clock_info_array = (struct _ClockInfoArray *)
6205                 (mode_info->atom_context->bios + data_offset +
6206                  le16_to_cpu(power_info->pplib.usClockInfoArrayOffset));
6207         non_clock_info_array = (struct _NonClockInfoArray *)
6208                 (mode_info->atom_context->bios + data_offset +
6209                  le16_to_cpu(power_info->pplib.usNonClockInfoArrayOffset));
6210
6211         rdev->pm.dpm.ps = kzalloc(sizeof(struct radeon_ps) *
6212                                   state_array->ucNumEntries, GFP_KERNEL);
6213         if (!rdev->pm.dpm.ps)
6214                 return -ENOMEM;
6215         power_state_offset = (u8 *)state_array->states;
6216         rdev->pm.dpm.platform_caps = le32_to_cpu(power_info->pplib.ulPlatformCaps);
6217         rdev->pm.dpm.backbias_response_time = le16_to_cpu(power_info->pplib.usBackbiasTime);
6218         rdev->pm.dpm.voltage_response_time = le16_to_cpu(power_info->pplib.usVoltageTime);
6219         for (i = 0; i < state_array->ucNumEntries; i++) {
6220                 power_state = (union pplib_power_state *)power_state_offset;
6221                 non_clock_array_index = power_state->v2.nonClockInfoIndex;
6222                 non_clock_info = (struct _ATOM_PPLIB_NONCLOCK_INFO *)
6223                         &non_clock_info_array->nonClockInfo[non_clock_array_index];
6224                 if (!rdev->pm.power_state[i].clock_info)
6225                         return -EINVAL;
6226                 ps = kzalloc(sizeof(struct ni_ps), GFP_KERNEL);
6227                 if (ps == NULL) {
6228                         kfree(rdev->pm.dpm.ps);
6229                         return -ENOMEM;
6230                 }
6231                 rdev->pm.dpm.ps[i].ps_priv = ps;
6232                 si_parse_pplib_non_clock_info(rdev, &rdev->pm.dpm.ps[i],
6233                                               non_clock_info,
6234                                               non_clock_info_array->ucEntrySize);
6235                 k = 0;
6236                 for (j = 0; j < power_state->v2.ucNumDPMLevels; j++) {
6237                         clock_array_index = power_state->v2.clockInfoIndex[j];
6238                         if (clock_array_index >= clock_info_array->ucNumEntries)
6239                                 continue;
6240                         if (k >= SISLANDS_MAX_HARDWARE_POWERLEVELS)
6241                                 break;
6242                         clock_info = (union pplib_clock_info *)
6243                                 &clock_info_array->clockInfo[clock_array_index * clock_info_array->ucEntrySize];
6244                         si_parse_pplib_clock_info(rdev,
6245                                                   &rdev->pm.dpm.ps[i], k,
6246                                                   clock_info);
6247                         k++;
6248                 }
6249                 power_state_offset += 2 + power_state->v2.ucNumDPMLevels;
6250         }
6251         rdev->pm.dpm.num_ps = state_array->ucNumEntries;
6252         return 0;
6253 }
6254
6255 int si_dpm_init(struct radeon_device *rdev)
6256 {
6257         struct rv7xx_power_info *pi;
6258         struct evergreen_power_info *eg_pi;
6259         struct ni_power_info *ni_pi;
6260         struct si_power_info *si_pi;
6261         int index = GetIndexIntoMasterTable(DATA, ASIC_InternalSS_Info);
6262         u16 data_offset, size;
6263         u8 frev, crev;
6264         struct atom_clock_dividers dividers;
6265         int ret;
6266         u32 mask;
6267
6268         si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL);
6269         if (si_pi == NULL)
6270                 return -ENOMEM;
6271         rdev->pm.dpm.priv = si_pi;
6272         ni_pi = &si_pi->ni;
6273         eg_pi = &ni_pi->eg;
6274         pi = &eg_pi->rv7xx;
6275
6276         ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask);
6277         if (ret)
6278                 si_pi->sys_pcie_mask = 0;
6279         else
6280                 si_pi->sys_pcie_mask = mask;
6281         si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID;
6282         si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);
6283
6284         si_set_max_cu_value(rdev);
6285
6286         rv770_get_max_vddc(rdev);
6287         si_get_leakage_vddc(rdev);
6288         si_patch_dependency_tables_based_on_leakage(rdev);
6289
6290         pi->acpi_vddc = 0;
6291         eg_pi->acpi_vddci = 0;
6292         pi->min_vddc_in_table = 0;
6293         pi->max_vddc_in_table = 0;
6294
6295         ret = si_parse_power_table(rdev);
6296         if (ret)
6297                 return ret;
6298         ret = r600_parse_extended_power_table(rdev);
6299         if (ret)
6300                 return ret;
6301
6302         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries =
6303                 kzalloc(4 * sizeof(struct radeon_clock_voltage_dependency_entry), GFP_KERNEL);
6304         if (!rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries) {
6305                 r600_free_extended_power_table(rdev);
6306                 return -ENOMEM;
6307         }
6308         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.count = 4;
6309         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].clk = 0;
6310         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[0].v = 0;
6311         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].clk = 36000;
6312         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[1].v = 720;
6313         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].clk = 54000;
6314         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[2].v = 810;
6315         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].clk = 72000;
6316         rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries[3].v = 900;
6317
6318         if (rdev->pm.dpm.voltage_response_time == 0)
6319                 rdev->pm.dpm.voltage_response_time = R600_VOLTAGERESPONSETIME_DFLT;
6320         if (rdev->pm.dpm.backbias_response_time == 0)
6321                 rdev->pm.dpm.backbias_response_time = R600_BACKBIASRESPONSETIME_DFLT;
6322
6323         ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM,
6324                                              0, false, &dividers);
6325         if (ret)
6326                 pi->ref_div = dividers.ref_div + 1;
6327         else
6328                 pi->ref_div = R600_REFERENCEDIVIDER_DFLT;
6329
6330         eg_pi->smu_uvd_hs = false;
6331
6332         pi->mclk_strobe_mode_threshold = 40000;
6333         if (si_is_special_1gb_platform(rdev))
6334                 pi->mclk_stutter_mode_threshold = 0;
6335         else
6336                 pi->mclk_stutter_mode_threshold = pi->mclk_strobe_mode_threshold;
6337         pi->mclk_edc_enable_threshold = 40000;
6338         eg_pi->mclk_edc_wr_enable_threshold = 40000;
6339
6340         ni_pi->mclk_rtt_mode_threshold = eg_pi->mclk_edc_wr_enable_threshold;
6341
6342         pi->voltage_control =
6343                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_GPIO_LUT);
6344
6345         pi->mvdd_control =
6346                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_MVDDC, VOLTAGE_OBJ_GPIO_LUT);
6347
6348         eg_pi->vddci_control =
6349                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDCI, VOLTAGE_OBJ_GPIO_LUT);
6350
6351         si_pi->vddc_phase_shed_control =
6352                 radeon_atom_is_voltage_gpio(rdev, SET_VOLTAGE_TYPE_ASIC_VDDC, VOLTAGE_OBJ_PHASE_LUT);
6353
6354         if (atom_parse_data_header(rdev->mode_info.atom_context, index, &size,
6355                                    &frev, &crev, &data_offset)) {
6356                 pi->sclk_ss = true;
6357                 pi->mclk_ss = true;
6358                 pi->dynamic_ss = true;
6359         } else {
6360                 pi->sclk_ss = false;
6361                 pi->mclk_ss = false;
6362                 pi->dynamic_ss = true;
6363         }
6364
6365         pi->asi = RV770_ASI_DFLT;
6366         pi->pasi = CYPRESS_HASI_DFLT;
6367         pi->vrc = SISLANDS_VRC_DFLT;
6368
6369         pi->gfx_clock_gating = true;
6370
6371         eg_pi->sclk_deep_sleep = true;
6372         si_pi->sclk_deep_sleep_above_low = false;
6373
6374         if (pi->gfx_clock_gating &&
6375             (rdev->pm.int_thermal_type != THERMAL_TYPE_NONE))
6376                 pi->thermal_protection = true;
6377         else
6378                 pi->thermal_protection = false;
6379
6380         eg_pi->dynamic_ac_timing = true;
6381
6382         eg_pi->light_sleep = true;
6383 #if defined(CONFIG_ACPI)
6384         eg_pi->pcie_performance_request =
6385                 radeon_acpi_is_pcie_performance_request_supported(rdev);
6386 #else
6387         eg_pi->pcie_performance_request = false;
6388 #endif
6389
6390         si_pi->sram_end = SMC_RAM_END;
6391
6392         rdev->pm.dpm.dyn_state.mclk_sclk_ratio = 4;
6393         rdev->pm.dpm.dyn_state.sclk_mclk_delta = 15000;
6394         rdev->pm.dpm.dyn_state.vddc_vddci_delta = 200;
6395         rdev->pm.dpm.dyn_state.valid_sclk_values.count = 0;
6396         rdev->pm.dpm.dyn_state.valid_sclk_values.values = NULL;
6397         rdev->pm.dpm.dyn_state.valid_mclk_values.count = 0;
6398         rdev->pm.dpm.dyn_state.valid_mclk_values.values = NULL;
6399
6400         si_initialize_powertune_defaults(rdev);
6401
6402         return 0;
6403 }
6404
6405 void si_dpm_fini(struct radeon_device *rdev)
6406 {
6407         int i;
6408
6409         for (i = 0; i < rdev->pm.dpm.num_ps; i++) {
6410                 kfree(rdev->pm.dpm.ps[i].ps_priv);
6411         }
6412         kfree(rdev->pm.dpm.ps);
6413         kfree(rdev->pm.dpm.priv);
6414         kfree(rdev->pm.dpm.dyn_state.vddc_dependency_on_dispclk.entries);
6415         r600_free_extended_power_table(rdev);
6416 }
6417
6418 void si_dpm_debugfs_print_current_performance_level(struct radeon_device *rdev,
6419                                                     struct seq_file *m)
6420 {
6421         struct radeon_ps *rps = rdev->pm.dpm.current_ps;
6422         struct ni_ps *ps = ni_get_ps(rps);
6423         struct rv7xx_pl *pl;
6424         u32 current_index =
6425                 (RREG32(TARGET_AND_CURRENT_PROFILE_INDEX) & CURRENT_STATE_INDEX_MASK) >>
6426                 CURRENT_STATE_INDEX_SHIFT;
6427
6428         if (current_index >= ps->performance_level_count) {
6429                 seq_printf(m, "invalid dpm profile %d\n", current_index);
6430         } else {
6431                 pl = &ps->performance_levels[current_index];
6432                 seq_printf(m, "uvd    vclk: %d dclk: %d\n", rps->vclk, rps->dclk);
6433                 seq_printf(m, "power level %d    sclk: %u mclk: %u vddc: %u vddci: %u pcie gen: %u\n",
6434                            current_index, pl->sclk, pl->mclk, pl->vddc, pl->vddci, pl->pcie_gen + 1);
6435         }
6436 }