drivers/gpu/drm/i915/intel_display.c

   1 /*
   2  * Copyright © 2006-2007 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21  * DEALINGS IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *      Eric Anholt <eric@anholt.net>
  25  */
  26
  27 #include <linux/dmi.h>
  28 #include <linux/module.h>
  29 #include <linux/input.h>
  30 #include <linux/i2c.h>
  31 #include <linux/kernel.h>
  32 #include <linux/slab.h>
  33 #include <linux/vgaarb.h>
  34 #include <drm/drm_edid.h>
  35 #include <drm/drmP.h>
  36 #include "intel_drv.h"
  37 #include <drm/i915_drm.h>
  38 #include "i915_drv.h"
  39 #include "i915_trace.h"
  40 #include <drm/drm_dp_helper.h>
  41 #include <drm/drm_crtc_helper.h>
  42 #include <linux/dma_remapping.h>
  43
  44 bool intel_pipe_has_type(struct drm_crtc *crtc, int type);
  45 static void intel_increase_pllclock(struct drm_crtc *crtc);
  46 static void intel_crtc_update_cursor(struct drm_crtc *crtc, bool on);
  47
  48 typedef struct {
  49         /* given values */
  50         int n;
  51         int m1, m2;
  52         int p1, p2;
  53         /* derived values */
  54         int     dot;
  55         int     vco;
  56         int     m;
  57         int     p;
  58 } intel_clock_t;
  59
  60 typedef struct {
  61         int     min, max;
  62 } intel_range_t;
  63
  64 typedef struct {
  65         int     dot_limit;
  66         int     p2_slow, p2_fast;
  67 } intel_p2_t;
  68
  69 #define INTEL_P2_NUM                  2
  70 typedef struct intel_limit intel_limit_t;
  71 struct intel_limit {
  72         intel_range_t   dot, vco, n, m, m1, m2, p, p1;
  73         intel_p2_t          p2;
  74         bool (* find_pll)(const intel_limit_t *, struct drm_crtc *,
  75                         int, int, intel_clock_t *, intel_clock_t *);
  76 };
  77
  78 /* FDI */
  79 #define IRONLAKE_FDI_FREQ               2700000 /* in kHz for mode->clock */
  80
  81 int
  82 intel_pch_rawclk(struct drm_device *dev)
  83 {
  84         struct drm_i915_private *dev_priv = dev->dev_private;
  85
  86         WARN_ON(!HAS_PCH_SPLIT(dev));
  87
  88         return I915_READ(PCH_RAWCLK_FREQ) & RAWCLK_FREQ_MASK;
  89 }
  90
  91 static bool
  92 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  93                     int target, int refclk, intel_clock_t *match_clock,
  94                     intel_clock_t *best_clock);
  95 static bool
  96 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
  97                         int target, int refclk, intel_clock_t *match_clock,
  98                         intel_clock_t *best_clock);
  99
 100 static bool
 101 intel_find_pll_g4x_dp(const intel_limit_t *, struct drm_crtc *crtc,
 102                       int target, int refclk, intel_clock_t *match_clock,
 103                       intel_clock_t *best_clock);
 104 static bool
 105 intel_find_pll_ironlake_dp(const intel_limit_t *, struct drm_crtc *crtc,
 106                            int target, int refclk, intel_clock_t *match_clock,
 107                            intel_clock_t *best_clock);
 108
 109 static bool
 110 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 111                         int target, int refclk, intel_clock_t *match_clock,
 112                         intel_clock_t *best_clock);
 113
 114 static inline u32 /* units of 100MHz */
 115 intel_fdi_link_freq(struct drm_device *dev)
 116 {
 117         if (IS_GEN5(dev)) {
 118                 struct drm_i915_private *dev_priv = dev->dev_private;
 119                 return (I915_READ(FDI_PLL_BIOS_0) & FDI_PLL_FB_CLOCK_MASK) + 2;
 120         } else
 121                 return 27;
 122 }
 123
 124 static const intel_limit_t intel_limits_i8xx_dvo = {
 125         .dot = { .min = 25000, .max = 350000 },
 126         .vco = { .min = 930000, .max = 1400000 },
 127         .n = { .min = 3, .max = 16 },
 128         .m = { .min = 96, .max = 140 },
 129         .m1 = { .min = 18, .max = 26 },
 130         .m2 = { .min = 6, .max = 16 },
 131         .p = { .min = 4, .max = 128 },
 132         .p1 = { .min = 2, .max = 33 },
 133         .p2 = { .dot_limit = 165000,
 134                 .p2_slow = 4, .p2_fast = 2 },
 135         .find_pll = intel_find_best_PLL,
 136 };
 137
 138 static const intel_limit_t intel_limits_i8xx_lvds = {
 139         .dot = { .min = 25000, .max = 350000 },
 140         .vco = { .min = 930000, .max = 1400000 },
 141         .n = { .min = 3, .max = 16 },
 142         .m = { .min = 96, .max = 140 },
 143         .m1 = { .min = 18, .max = 26 },
 144         .m2 = { .min = 6, .max = 16 },
 145         .p = { .min = 4, .max = 128 },
 146         .p1 = { .min = 1, .max = 6 },
 147         .p2 = { .dot_limit = 165000,
 148                 .p2_slow = 14, .p2_fast = 7 },
 149         .find_pll = intel_find_best_PLL,
 150 };
 151
 152 static const intel_limit_t intel_limits_i9xx_sdvo = {
 153         .dot = { .min = 20000, .max = 400000 },
 154         .vco = { .min = 1400000, .max = 2800000 },
 155         .n = { .min = 1, .max = 6 },
 156         .m = { .min = 70, .max = 120 },
 157         .m1 = { .min = 10, .max = 22 },
 158         .m2 = { .min = 5, .max = 9 },
 159         .p = { .min = 5, .max = 80 },
 160         .p1 = { .min = 1, .max = 8 },
 161         .p2 = { .dot_limit = 200000,
 162                 .p2_slow = 10, .p2_fast = 5 },
 163         .find_pll = intel_find_best_PLL,
 164 };
 165
 166 static const intel_limit_t intel_limits_i9xx_lvds = {
 167         .dot = { .min = 20000, .max = 400000 },
 168         .vco = { .min = 1400000, .max = 2800000 },
 169         .n = { .min = 1, .max = 6 },
 170         .m = { .min = 70, .max = 120 },
 171         .m1 = { .min = 10, .max = 22 },
 172         .m2 = { .min = 5, .max = 9 },
 173         .p = { .min = 7, .max = 98 },
 174         .p1 = { .min = 1, .max = 8 },
 175         .p2 = { .dot_limit = 112000,
 176                 .p2_slow = 14, .p2_fast = 7 },
 177         .find_pll = intel_find_best_PLL,
 178 };
 179
 180
 181 static const intel_limit_t intel_limits_g4x_sdvo = {
 182         .dot = { .min = 25000, .max = 270000 },
 183         .vco = { .min = 1750000, .max = 3500000},
 184         .n = { .min = 1, .max = 4 },
 185         .m = { .min = 104, .max = 138 },
 186         .m1 = { .min = 17, .max = 23 },
 187         .m2 = { .min = 5, .max = 11 },
 188         .p = { .min = 10, .max = 30 },
 189         .p1 = { .min = 1, .max = 3},
 190         .p2 = { .dot_limit = 270000,
 191                 .p2_slow = 10,
 192                 .p2_fast = 10
 193         },
 194         .find_pll = intel_g4x_find_best_PLL,
 195 };
 196
 197 static const intel_limit_t intel_limits_g4x_hdmi = {
 198         .dot = { .min = 22000, .max = 400000 },
 199         .vco = { .min = 1750000, .max = 3500000},
 200         .n = { .min = 1, .max = 4 },
 201         .m = { .min = 104, .max = 138 },
 202         .m1 = { .min = 16, .max = 23 },
 203         .m2 = { .min = 5, .max = 11 },
 204         .p = { .min = 5, .max = 80 },
 205         .p1 = { .min = 1, .max = 8},
 206         .p2 = { .dot_limit = 165000,
 207                 .p2_slow = 10, .p2_fast = 5 },
 208         .find_pll = intel_g4x_find_best_PLL,
 209 };
 210
 211 static const intel_limit_t intel_limits_g4x_single_channel_lvds = {
 212         .dot = { .min = 20000, .max = 115000 },
 213         .vco = { .min = 1750000, .max = 3500000 },
 214         .n = { .min = 1, .max = 3 },
 215         .m = { .min = 104, .max = 138 },
 216         .m1 = { .min = 17, .max = 23 },
 217         .m2 = { .min = 5, .max = 11 },
 218         .p = { .min = 28, .max = 112 },
 219         .p1 = { .min = 2, .max = 8 },
 220         .p2 = { .dot_limit = 0,
 221                 .p2_slow = 14, .p2_fast = 14
 222         },
 223         .find_pll = intel_g4x_find_best_PLL,
 224 };
 225
 226 static const intel_limit_t intel_limits_g4x_dual_channel_lvds = {
 227         .dot = { .min = 80000, .max = 224000 },
 228         .vco = { .min = 1750000, .max = 3500000 },
 229         .n = { .min = 1, .max = 3 },
 230         .m = { .min = 104, .max = 138 },
 231         .m1 = { .min = 17, .max = 23 },
 232         .m2 = { .min = 5, .max = 11 },
 233         .p = { .min = 14, .max = 42 },
 234         .p1 = { .min = 2, .max = 6 },
 235         .p2 = { .dot_limit = 0,
 236                 .p2_slow = 7, .p2_fast = 7
 237         },
 238         .find_pll = intel_g4x_find_best_PLL,
 239 };
 240
 241 static const intel_limit_t intel_limits_g4x_display_port = {
 242         .dot = { .min = 161670, .max = 227000 },
 243         .vco = { .min = 1750000, .max = 3500000},
 244         .n = { .min = 1, .max = 2 },
 245         .m = { .min = 97, .max = 108 },
 246         .m1 = { .min = 0x10, .max = 0x12 },
 247         .m2 = { .min = 0x05, .max = 0x06 },
 248         .p = { .min = 10, .max = 20 },
 249         .p1 = { .min = 1, .max = 2},
 250         .p2 = { .dot_limit = 0,
 251                 .p2_slow = 10, .p2_fast = 10 },
 252         .find_pll = intel_find_pll_g4x_dp,
 253 };
 254
 255 static const intel_limit_t intel_limits_pineview_sdvo = {
 256         .dot = { .min = 20000, .max = 400000},
 257         .vco = { .min = 1700000, .max = 3500000 },
 258         /* Pineview's Ncounter is a ring counter */
 259         .n = { .min = 3, .max = 6 },
 260         .m = { .min = 2, .max = 256 },
 261         /* Pineview only has one combined m divider, which we treat as m2. */
 262         .m1 = { .min = 0, .max = 0 },
 263         .m2 = { .min = 0, .max = 254 },
 264         .p = { .min = 5, .max = 80 },
 265         .p1 = { .min = 1, .max = 8 },
 266         .p2 = { .dot_limit = 200000,
 267                 .p2_slow = 10, .p2_fast = 5 },
 268         .find_pll = intel_find_best_PLL,
 269 };
 270
 271 static const intel_limit_t intel_limits_pineview_lvds = {
 272         .dot = { .min = 20000, .max = 400000 },
 273         .vco = { .min = 1700000, .max = 3500000 },
 274         .n = { .min = 3, .max = 6 },
 275         .m = { .min = 2, .max = 256 },
 276         .m1 = { .min = 0, .max = 0 },
 277         .m2 = { .min = 0, .max = 254 },
 278         .p = { .min = 7, .max = 112 },
 279         .p1 = { .min = 1, .max = 8 },
 280         .p2 = { .dot_limit = 112000,
 281                 .p2_slow = 14, .p2_fast = 14 },
 282         .find_pll = intel_find_best_PLL,
 283 };
 284
 285 /* Ironlake / Sandybridge
 286  *
 287  * We calculate clock using (register_value + 2) for N/M1/M2, so here
 288  * the range value for them is (actual_value - 2).
 289  */
 290 static const intel_limit_t intel_limits_ironlake_dac = {
 291         .dot = { .min = 25000, .max = 350000 },
 292         .vco = { .min = 1760000, .max = 3510000 },
 293         .n = { .min = 1, .max = 5 },
 294         .m = { .min = 79, .max = 127 },
 295         .m1 = { .min = 12, .max = 22 },
 296         .m2 = { .min = 5, .max = 9 },
 297         .p = { .min = 5, .max = 80 },
 298         .p1 = { .min = 1, .max = 8 },
 299         .p2 = { .dot_limit = 225000,
 300                 .p2_slow = 10, .p2_fast = 5 },
 301         .find_pll = intel_g4x_find_best_PLL,
 302 };
 303
 304 static const intel_limit_t intel_limits_ironlake_single_lvds = {
 305         .dot = { .min = 25000, .max = 350000 },
 306         .vco = { .min = 1760000, .max = 3510000 },
 307         .n = { .min = 1, .max = 3 },
 308         .m = { .min = 79, .max = 118 },
 309         .m1 = { .min = 12, .max = 22 },
 310         .m2 = { .min = 5, .max = 9 },
 311         .p = { .min = 28, .max = 112 },
 312         .p1 = { .min = 2, .max = 8 },
 313         .p2 = { .dot_limit = 225000,
 314                 .p2_slow = 14, .p2_fast = 14 },
 315         .find_pll = intel_g4x_find_best_PLL,
 316 };
 317
 318 static const intel_limit_t intel_limits_ironlake_dual_lvds = {
 319         .dot = { .min = 25000, .max = 350000 },
 320         .vco = { .min = 1760000, .max = 3510000 },
 321         .n = { .min = 1, .max = 3 },
 322         .m = { .min = 79, .max = 127 },
 323         .m1 = { .min = 12, .max = 22 },
 324         .m2 = { .min = 5, .max = 9 },
 325         .p = { .min = 14, .max = 56 },
 326         .p1 = { .min = 2, .max = 8 },
 327         .p2 = { .dot_limit = 225000,
 328                 .p2_slow = 7, .p2_fast = 7 },
 329         .find_pll = intel_g4x_find_best_PLL,
 330 };
 331
 332 /* LVDS 100mhz refclk limits. */
 333 static const intel_limit_t intel_limits_ironlake_single_lvds_100m = {
 334         .dot = { .min = 25000, .max = 350000 },
 335         .vco = { .min = 1760000, .max = 3510000 },
 336         .n = { .min = 1, .max = 2 },
 337         .m = { .min = 79, .max = 126 },
 338         .m1 = { .min = 12, .max = 22 },
 339         .m2 = { .min = 5, .max = 9 },
 340         .p = { .min = 28, .max = 112 },
 341         .p1 = { .min = 2, .max = 8 },
 342         .p2 = { .dot_limit = 225000,
 343                 .p2_slow = 14, .p2_fast = 14 },
 344         .find_pll = intel_g4x_find_best_PLL,
 345 };
 346
 347 static const intel_limit_t intel_limits_ironlake_dual_lvds_100m = {
 348         .dot = { .min = 25000, .max = 350000 },
 349         .vco = { .min = 1760000, .max = 3510000 },
 350         .n = { .min = 1, .max = 3 },
 351         .m = { .min = 79, .max = 126 },
 352         .m1 = { .min = 12, .max = 22 },
 353         .m2 = { .min = 5, .max = 9 },
 354         .p = { .min = 14, .max = 42 },
 355         .p1 = { .min = 2, .max = 6 },
 356         .p2 = { .dot_limit = 225000,
 357                 .p2_slow = 7, .p2_fast = 7 },
 358         .find_pll = intel_g4x_find_best_PLL,
 359 };
 360
 361 static const intel_limit_t intel_limits_ironlake_display_port = {
 362         .dot = { .min = 25000, .max = 350000 },
 363         .vco = { .min = 1760000, .max = 3510000},
 364         .n = { .min = 1, .max = 2 },
 365         .m = { .min = 81, .max = 90 },
 366         .m1 = { .min = 12, .max = 22 },
 367         .m2 = { .min = 5, .max = 9 },
 368         .p = { .min = 10, .max = 20 },
 369         .p1 = { .min = 1, .max = 2},
 370         .p2 = { .dot_limit = 0,
 371                 .p2_slow = 10, .p2_fast = 10 },
 372         .find_pll = intel_find_pll_ironlake_dp,
 373 };
 374
 375 static const intel_limit_t intel_limits_vlv_dac = {
 376         .dot = { .min = 25000, .max = 270000 },
 377         .vco = { .min = 4000000, .max = 6000000 },
 378         .n = { .min = 1, .max = 7 },
 379         .m = { .min = 22, .max = 450 }, /* guess */
 380         .m1 = { .min = 2, .max = 3 },
 381         .m2 = { .min = 11, .max = 156 },
 382         .p = { .min = 10, .max = 30 },
 383         .p1 = { .min = 2, .max = 3 },
 384         .p2 = { .dot_limit = 270000,
 385                 .p2_slow = 2, .p2_fast = 20 },
 386         .find_pll = intel_vlv_find_best_pll,
 387 };
 388
 389 static const intel_limit_t intel_limits_vlv_hdmi = {
 390         .dot = { .min = 20000, .max = 165000 },
 391         .vco = { .min = 4000000, .max = 5994000},
 392         .n = { .min = 1, .max = 7 },
 393         .m = { .min = 60, .max = 300 }, /* guess */
 394         .m1 = { .min = 2, .max = 3 },
 395         .m2 = { .min = 11, .max = 156 },
 396         .p = { .min = 10, .max = 30 },
 397         .p1 = { .min = 2, .max = 3 },
 398         .p2 = { .dot_limit = 270000,
 399                 .p2_slow = 2, .p2_fast = 20 },
 400         .find_pll = intel_vlv_find_best_pll,
 401 };
 402
 403 static const intel_limit_t intel_limits_vlv_dp = {
 404         .dot = { .min = 25000, .max = 270000 },
 405         .vco = { .min = 4000000, .max = 6000000 },
 406         .n = { .min = 1, .max = 7 },
 407         .m = { .min = 22, .max = 450 },
 408         .m1 = { .min = 2, .max = 3 },
 409         .m2 = { .min = 11, .max = 156 },
 410         .p = { .min = 10, .max = 30 },
 411         .p1 = { .min = 2, .max = 3 },
 412         .p2 = { .dot_limit = 270000,
 413                 .p2_slow = 2, .p2_fast = 20 },
 414         .find_pll = intel_vlv_find_best_pll,
 415 };
 416
 417 u32 intel_dpio_read(struct drm_i915_private *dev_priv, int reg)
 418 {
 419         unsigned long flags;
 420         u32 val = 0;
 421
 422         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 423         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 424                 DRM_ERROR("DPIO idle wait timed out\n");
 425                 goto out_unlock;
 426         }
 427
 428         I915_WRITE(DPIO_REG, reg);
 429         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_READ | DPIO_PORTID |
 430                    DPIO_BYTE);
 431         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 432                 DRM_ERROR("DPIO read wait timed out\n");
 433                 goto out_unlock;
 434         }
 435         val = I915_READ(DPIO_DATA);
 436
 437 out_unlock:
 438         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 439         return val;
 440 }
 441
 442 static void intel_dpio_write(struct drm_i915_private *dev_priv, int reg,
 443                              u32 val)
 444 {
 445         unsigned long flags;
 446
 447         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
 448         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100)) {
 449                 DRM_ERROR("DPIO idle wait timed out\n");
 450                 goto out_unlock;
 451         }
 452
 453         I915_WRITE(DPIO_DATA, val);
 454         I915_WRITE(DPIO_REG, reg);
 455         I915_WRITE(DPIO_PKT, DPIO_RID | DPIO_OP_WRITE | DPIO_PORTID |
 456                    DPIO_BYTE);
 457         if (wait_for_atomic_us((I915_READ(DPIO_PKT) & DPIO_BUSY) == 0, 100))
 458                 DRM_ERROR("DPIO write wait timed out\n");
 459
 460 out_unlock:
 461        spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
 462 }
 463
 464 static void vlv_init_dpio(struct drm_device *dev)
 465 {
 466         struct drm_i915_private *dev_priv = dev->dev_private;
 467
 468         /* Reset the DPIO config */
 469         I915_WRITE(DPIO_CTL, 0);
 470         POSTING_READ(DPIO_CTL);
 471         I915_WRITE(DPIO_CTL, 1);
 472         POSTING_READ(DPIO_CTL);
 473 }
 474
 475 static const intel_limit_t *intel_ironlake_limit(struct drm_crtc *crtc,
 476                                                 int refclk)
 477 {
 478         struct drm_device *dev = crtc->dev;
 479         const intel_limit_t *limit;
 480
 481         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 482                 if (intel_is_dual_link_lvds(dev)) {
 483                         /* LVDS dual channel */
 484                         if (refclk == 100000)
 485                                 limit = &intel_limits_ironlake_dual_lvds_100m;
 486                         else
 487                                 limit = &intel_limits_ironlake_dual_lvds;
 488                 } else {
 489                         if (refclk == 100000)
 490                                 limit = &intel_limits_ironlake_single_lvds_100m;
 491                         else
 492                                 limit = &intel_limits_ironlake_single_lvds;
 493                 }
 494         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
 495                    intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))
 496                 limit = &intel_limits_ironlake_display_port;
 497         else
 498                 limit = &intel_limits_ironlake_dac;
 499
 500         return limit;
 501 }
 502
 503 static const intel_limit_t *intel_g4x_limit(struct drm_crtc *crtc)
 504 {
 505         struct drm_device *dev = crtc->dev;
 506         const intel_limit_t *limit;
 507
 508         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 509                 if (intel_is_dual_link_lvds(dev))
 510                         /* LVDS with dual channel */
 511                         limit = &intel_limits_g4x_dual_channel_lvds;
 512                 else
 513                         /* LVDS with dual channel */
 514                         limit = &intel_limits_g4x_single_channel_lvds;
 515         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI) ||
 516                    intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
 517                 limit = &intel_limits_g4x_hdmi;
 518         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO)) {
 519                 limit = &intel_limits_g4x_sdvo;
 520         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
 521                 limit = &intel_limits_g4x_display_port;
 522         } else /* The option is for other outputs */
 523                 limit = &intel_limits_i9xx_sdvo;
 524
 525         return limit;
 526 }
 527
 528 static const intel_limit_t *intel_limit(struct drm_crtc *crtc, int refclk)
 529 {
 530         struct drm_device *dev = crtc->dev;
 531         const intel_limit_t *limit;
 532
 533         if (HAS_PCH_SPLIT(dev))
 534                 limit = intel_ironlake_limit(crtc, refclk);
 535         else if (IS_G4X(dev)) {
 536                 limit = intel_g4x_limit(crtc);
 537         } else if (IS_PINEVIEW(dev)) {
 538                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 539                         limit = &intel_limits_pineview_lvds;
 540                 else
 541                         limit = &intel_limits_pineview_sdvo;
 542         } else if (IS_VALLEYVIEW(dev)) {
 543                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG))
 544                         limit = &intel_limits_vlv_dac;
 545                 else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
 546                         limit = &intel_limits_vlv_hdmi;
 547                 else
 548                         limit = &intel_limits_vlv_dp;
 549         } else if (!IS_GEN2(dev)) {
 550                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 551                         limit = &intel_limits_i9xx_lvds;
 552                 else
 553                         limit = &intel_limits_i9xx_sdvo;
 554         } else {
 555                 if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
 556                         limit = &intel_limits_i8xx_lvds;
 557                 else
 558                         limit = &intel_limits_i8xx_dvo;
 559         }
 560         return limit;
 561 }
 562
 563 /* m1 is reserved as 0 in Pineview, n is a ring counter */
 564 static void pineview_clock(int refclk, intel_clock_t *clock)
 565 {
 566         clock->m = clock->m2 + 2;
 567         clock->p = clock->p1 * clock->p2;
 568         clock->vco = refclk * clock->m / clock->n;
 569         clock->dot = clock->vco / clock->p;
 570 }
 571
 572 static void intel_clock(struct drm_device *dev, int refclk, intel_clock_t *clock)
 573 {
 574         if (IS_PINEVIEW(dev)) {
 575                 pineview_clock(refclk, clock);
 576                 return;
 577         }
 578         clock->m = 5 * (clock->m1 + 2) + (clock->m2 + 2);
 579         clock->p = clock->p1 * clock->p2;
 580         clock->vco = refclk * clock->m / (clock->n + 2);
 581         clock->dot = clock->vco / clock->p;
 582 }
 583
 584 /**
 585  * Returns whether any output on the specified pipe is of the specified type
 586  */
 587 bool intel_pipe_has_type(struct drm_crtc *crtc, int type)
 588 {
 589         struct drm_device *dev = crtc->dev;
 590         struct intel_encoder *encoder;
 591
 592         for_each_encoder_on_crtc(dev, crtc, encoder)
 593                 if (encoder->type == type)
 594                         return true;
 595
 596         return false;
 597 }
 598
 599 #define INTELPllInvalid(s)   do { /* DRM_DEBUG(s); */ return false; } while (0)
 600 /**
 601  * Returns whether the given set of divisors are valid for a given refclk with
 602  * the given connectors.
 603  */
 604
 605 static bool intel_PLL_is_valid(struct drm_device *dev,
 606                                const intel_limit_t *limit,
 607                                const intel_clock_t *clock)
 608 {
 609         if (clock->p1  < limit->p1.min  || limit->p1.max  < clock->p1)
 610                 INTELPllInvalid("p1 out of range\n");
 611         if (clock->p   < limit->p.min   || limit->p.max   < clock->p)
 612                 INTELPllInvalid("p out of range\n");
 613         if (clock->m2  < limit->m2.min  || limit->m2.max  < clock->m2)
 614                 INTELPllInvalid("m2 out of range\n");
 615         if (clock->m1  < limit->m1.min  || limit->m1.max  < clock->m1)
 616                 INTELPllInvalid("m1 out of range\n");
 617         if (clock->m1 <= clock->m2 && !IS_PINEVIEW(dev))
 618                 INTELPllInvalid("m1 <= m2\n");
 619         if (clock->m   < limit->m.min   || limit->m.max   < clock->m)
 620                 INTELPllInvalid("m out of range\n");
 621         if (clock->n   < limit->n.min   || limit->n.max   < clock->n)
 622                 INTELPllInvalid("n out of range\n");
 623         if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
 624                 INTELPllInvalid("vco out of range\n");
 625         /* XXX: We may need to be checking "Dot clock" depending on the multiplier,
 626          * connector, etc., rather than just a single range.
 627          */
 628         if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
 629                 INTELPllInvalid("dot out of range\n");
 630
 631         return true;
 632 }
 633
 634 static bool
 635 intel_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 636                     int target, int refclk, intel_clock_t *match_clock,
 637                     intel_clock_t *best_clock)
 638
 639 {
 640         struct drm_device *dev = crtc->dev;
 641         intel_clock_t clock;
 642         int err = target;
 643
 644         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 645                 /*
 646                  * For LVDS just rely on its current settings for dual-channel.
 647                  * We haven't figured out how to reliably set up different
 648                  * single/dual channel state, if we even can.
 649                  */
 650                 if (intel_is_dual_link_lvds(dev))
 651                         clock.p2 = limit->p2.p2_fast;
 652                 else
 653                         clock.p2 = limit->p2.p2_slow;
 654         } else {
 655                 if (target < limit->p2.dot_limit)
 656                         clock.p2 = limit->p2.p2_slow;
 657                 else
 658                         clock.p2 = limit->p2.p2_fast;
 659         }
 660
 661         memset(best_clock, 0, sizeof(*best_clock));
 662
 663         for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max;
 664              clock.m1++) {
 665                 for (clock.m2 = limit->m2.min;
 666                      clock.m2 <= limit->m2.max; clock.m2++) {
 667                         /* m1 is always 0 in Pineview */
 668                         if (clock.m2 >= clock.m1 && !IS_PINEVIEW(dev))
 669                                 break;
 670                         for (clock.n = limit->n.min;
 671                              clock.n <= limit->n.max; clock.n++) {
 672                                 for (clock.p1 = limit->p1.min;
 673                                         clock.p1 <= limit->p1.max; clock.p1++) {
 674                                         int this_err;
 675
 676                                         intel_clock(dev, refclk, &clock);
 677                                         if (!intel_PLL_is_valid(dev, limit,
 678                                                                 &clock))
 679                                                 continue;
 680                                         if (match_clock &&
 681                                             clock.p != match_clock->p)
 682                                                 continue;
 683
 684                                         this_err = abs(clock.dot - target);
 685                                         if (this_err < err) {
 686                                                 *best_clock = clock;
 687                                                 err = this_err;
 688                                         }
 689                                 }
 690                         }
 691                 }
 692         }
 693
 694         return (err != target);
 695 }
 696
 697 static bool
 698 intel_g4x_find_best_PLL(const intel_limit_t *limit, struct drm_crtc *crtc,
 699                         int target, int refclk, intel_clock_t *match_clock,
 700                         intel_clock_t *best_clock)
 701 {
 702         struct drm_device *dev = crtc->dev;
 703         intel_clock_t clock;
 704         int max_n;
 705         bool found;
 706         /* approximately equals target * 0.00585 */
 707         int err_most = (target >> 8) + (target >> 9);
 708         found = false;
 709
 710         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
 711                 int lvds_reg;
 712
 713                 if (HAS_PCH_SPLIT(dev))
 714                         lvds_reg = PCH_LVDS;
 715                 else
 716                         lvds_reg = LVDS;
 717                 if (intel_is_dual_link_lvds(dev))
 718                         clock.p2 = limit->p2.p2_fast;
 719                 else
 720                         clock.p2 = limit->p2.p2_slow;
 721         } else {
 722                 if (target < limit->p2.dot_limit)
 723                         clock.p2 = limit->p2.p2_slow;
 724                 else
 725                         clock.p2 = limit->p2.p2_fast;
 726         }
 727
 728         memset(best_clock, 0, sizeof(*best_clock));
 729         max_n = limit->n.max;
 730         /* based on hardware requirement, prefer smaller n to precision */
 731         for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) {
 732                 /* based on hardware requirement, prefere larger m1,m2 */
 733                 for (clock.m1 = limit->m1.max;
 734                      clock.m1 >= limit->m1.min; clock.m1--) {
 735                         for (clock.m2 = limit->m2.max;
 736                              clock.m2 >= limit->m2.min; clock.m2--) {
 737                                 for (clock.p1 = limit->p1.max;
 738                                      clock.p1 >= limit->p1.min; clock.p1--) {
 739                                         int this_err;
 740
 741                                         intel_clock(dev, refclk, &clock);
 742                                         if (!intel_PLL_is_valid(dev, limit,
 743                                                                 &clock))
 744                                                 continue;
 745                                         if (match_clock &&
 746                                             clock.p != match_clock->p)
 747                                                 continue;
 748
 749                                         this_err = abs(clock.dot - target);
 750                                         if (this_err < err_most) {
 751                                                 *best_clock = clock;
 752                                                 err_most = this_err;
 753                                                 max_n = clock.n;
 754                                                 found = true;
 755                                         }
 756                                 }
 757                         }
 758                 }
 759         }
 760         return found;
 761 }
 762
 763 static bool
 764 intel_find_pll_ironlake_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 765                            int target, int refclk, intel_clock_t *match_clock,
 766                            intel_clock_t *best_clock)
 767 {
 768         struct drm_device *dev = crtc->dev;
 769         intel_clock_t clock;
 770
 771         if (target < 200000) {
 772                 clock.n = 1;
 773                 clock.p1 = 2;
 774                 clock.p2 = 10;
 775                 clock.m1 = 12;
 776                 clock.m2 = 9;
 777         } else {
 778                 clock.n = 2;
 779                 clock.p1 = 1;
 780                 clock.p2 = 10;
 781                 clock.m1 = 14;
 782                 clock.m2 = 8;
 783         }
 784         intel_clock(dev, refclk, &clock);
 785         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 786         return true;
 787 }
 788
 789 /* DisplayPort has only two frequencies, 162MHz and 270MHz */
 790 static bool
 791 intel_find_pll_g4x_dp(const intel_limit_t *limit, struct drm_crtc *crtc,
 792                       int target, int refclk, intel_clock_t *match_clock,
 793                       intel_clock_t *best_clock)
 794 {
 795         intel_clock_t clock;
 796         if (target < 200000) {
 797                 clock.p1 = 2;
 798                 clock.p2 = 10;
 799                 clock.n = 2;
 800                 clock.m1 = 23;
 801                 clock.m2 = 8;
 802         } else {
 803                 clock.p1 = 1;
 804                 clock.p2 = 10;
 805                 clock.n = 1;
 806                 clock.m1 = 14;
 807                 clock.m2 = 2;
 808         }
 809         clock.m = 5 * (clock.m1 + 2) + (clock.m2 + 2);
 810         clock.p = (clock.p1 * clock.p2);
 811         clock.dot = 96000 * clock.m / (clock.n + 2) / clock.p;
 812         clock.vco = 0;
 813         memcpy(best_clock, &clock, sizeof(intel_clock_t));
 814         return true;
 815 }
 816 static bool
 817 intel_vlv_find_best_pll(const intel_limit_t *limit, struct drm_crtc *crtc,
 818                         int target, int refclk, intel_clock_t *match_clock,
 819                         intel_clock_t *best_clock)
 820 {
 821         u32 p1, p2, m1, m2, vco, bestn, bestm1, bestm2, bestp1, bestp2;
 822         u32 m, n, fastclk;
 823         u32 updrate, minupdate, fracbits, p;
 824         unsigned long bestppm, ppm, absppm;
 825         int dotclk, flag;
 826
 827         flag = 0;
 828         dotclk = target * 1000;
 829         bestppm = 1000000;
 830         ppm = absppm = 0;
 831         fastclk = dotclk / (2*100);
 832         updrate = 0;
 833         minupdate = 19200;
 834         fracbits = 1;
 835         n = p = p1 = p2 = m = m1 = m2 = vco = bestn = 0;
 836         bestm1 = bestm2 = bestp1 = bestp2 = 0;
 837
 838         /* based on hardware requirement, prefer smaller n to precision */
 839         for (n = limit->n.min; n <= ((refclk) / minupdate); n++) {
 840                 updrate = refclk / n;
 841                 for (p1 = limit->p1.max; p1 > limit->p1.min; p1--) {
 842                         for (p2 = limit->p2.p2_fast+1; p2 > 0; p2--) {
 843                                 if (p2 > 10)
 844                                         p2 = p2 - 1;
 845                                 p = p1 * p2;
 846                                 /* based on hardware requirement, prefer bigger m1,m2 values */
 847                                 for (m1 = limit->m1.min; m1 <= limit->m1.max; m1++) {
 848                                         m2 = (((2*(fastclk * p * n / m1 )) +
 849                                                refclk) / (2*refclk));
 850                                         m = m1 * m2;
 851                                         vco = updrate * m;
 852                                         if (vco >= limit->vco.min && vco < limit->vco.max) {
 853                                                 ppm = 1000000 * ((vco / p) - fastclk) / fastclk;
 854                                                 absppm = (ppm > 0) ? ppm : (-ppm);
 855                                                 if (absppm < 100 && ((p1 * p2) > (bestp1 * bestp2))) {
 856                                                         bestppm = 0;
 857                                                         flag = 1;
 858                                                 }
 859                                                 if (absppm < bestppm - 10) {
 860                                                         bestppm = absppm;
 861                                                         flag = 1;
 862                                                 }
 863                                                 if (flag) {
 864                                                         bestn = n;
 865                                                         bestm1 = m1;
 866                                                         bestm2 = m2;
 867                                                         bestp1 = p1;
 868                                                         bestp2 = p2;
 869                                                         flag = 0;
 870                                                 }
 871                                         }
 872                                 }
 873                         }
 874                 }
 875         }
 876         best_clock->n = bestn;
 877         best_clock->m1 = bestm1;
 878         best_clock->m2 = bestm2;
 879         best_clock->p1 = bestp1;
 880         best_clock->p2 = bestp2;
 881
 882         return true;
 883 }
 884
 885 enum transcoder intel_pipe_to_cpu_transcoder(struct drm_i915_private *dev_priv,
 886                                              enum pipe pipe)
 887 {
 888         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
 889         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
 890
 891         return intel_crtc->cpu_transcoder;
 892 }
 893
 894 static void ironlake_wait_for_vblank(struct drm_device *dev, int pipe)
 895 {
 896         struct drm_i915_private *dev_priv = dev->dev_private;
 897         u32 frame, frame_reg = PIPEFRAME(pipe);
 898
 899         frame = I915_READ(frame_reg);
 900
 901         if (wait_for(I915_READ_NOTRACE(frame_reg) != frame, 50))
 902                 DRM_DEBUG_KMS("vblank wait timed out\n");
 903 }
 904
 905 /**
 906  * intel_wait_for_vblank - wait for vblank on a given pipe
 907  * @dev: drm device
 908  * @pipe: pipe to wait for
 909  *
 910  * Wait for vblank to occur on a given pipe.  Needed for various bits of
 911  * mode setting code.
 912  */
 913 void intel_wait_for_vblank(struct drm_device *dev, int pipe)
 914 {
 915         struct drm_i915_private *dev_priv = dev->dev_private;
 916         int pipestat_reg = PIPESTAT(pipe);
 917
 918         if (INTEL_INFO(dev)->gen >= 5) {
 919                 ironlake_wait_for_vblank(dev, pipe);
 920                 return;
 921         }
 922
 923         /* Clear existing vblank status. Note this will clear any other
 924          * sticky status fields as well.
 925          *
 926          * This races with i915_driver_irq_handler() with the result
 927          * that either function could miss a vblank event.  Here it is not
 928          * fatal, as we will either wait upon the next vblank interrupt or
 929          * timeout.  Generally speaking intel_wait_for_vblank() is only
 930          * called during modeset at which time the GPU should be idle and
 931          * should *not* be performing page flips and thus not waiting on
 932          * vblanks...
 933          * Currently, the result of us stealing a vblank from the irq
 934          * handler is that a single frame will be skipped during swapbuffers.
 935          */
 936         I915_WRITE(pipestat_reg,
 937                    I915_READ(pipestat_reg) | PIPE_VBLANK_INTERRUPT_STATUS);
 938
 939         /* Wait for vblank interrupt bit to set */
 940         if (wait_for(I915_READ(pipestat_reg) &
 941                      PIPE_VBLANK_INTERRUPT_STATUS,
 942                      50))
 943                 DRM_DEBUG_KMS("vblank wait timed out\n");
 944 }
 945
 946 /*
 947  * intel_wait_for_pipe_off - wait for pipe to turn off
 948  * @dev: drm device
 949  * @pipe: pipe to wait for
 950  *
 951  * After disabling a pipe, we can't wait for vblank in the usual way,
 952  * spinning on the vblank interrupt status bit, since we won't actually
 953  * see an interrupt when the pipe is disabled.
 954  *
 955  * On Gen4 and above:
 956  *   wait for the pipe register state bit to turn off
 957  *
 958  * Otherwise:
 959  *   wait for the display line value to settle (it usually
 960  *   ends up stopping at the start of the next frame).
 961  *
 962  */
 963 void intel_wait_for_pipe_off(struct drm_device *dev, int pipe)
 964 {
 965         struct drm_i915_private *dev_priv = dev->dev_private;
 966         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
 967                                                                       pipe);
 968
 969         if (INTEL_INFO(dev)->gen >= 4) {
 970                 int reg = PIPECONF(cpu_transcoder);
 971
 972                 /* Wait for the Pipe State to go off */
 973                 if (wait_for((I915_READ(reg) & I965_PIPECONF_ACTIVE) == 0,
 974                              100))
 975                         WARN(1, "pipe_off wait timed out\n");
 976         } else {
 977                 u32 last_line, line_mask;
 978                 int reg = PIPEDSL(pipe);
 979                 unsigned long timeout = jiffies + msecs_to_jiffies(100);
 980
 981                 if (IS_GEN2(dev))
 982                         line_mask = DSL_LINEMASK_GEN2;
 983                 else
 984                         line_mask = DSL_LINEMASK_GEN3;
 985
 986                 /* Wait for the display line to settle */
 987                 do {
 988                         last_line = I915_READ(reg) & line_mask;
 989                         mdelay(5);
 990                 } while (((I915_READ(reg) & line_mask) != last_line) &&
 991                          time_after(timeout, jiffies));
 992                 if (time_after(jiffies, timeout))
 993                         WARN(1, "pipe_off wait timed out\n");
 994         }
 995 }
 996
 997 static const char *state_string(bool enabled)
 998 {
 999         return enabled ? "on" : "off";
1000 }
1001
1002 /* Only for pre-ILK configs */
1003 static void assert_pll(struct drm_i915_private *dev_priv,
1004                        enum pipe pipe, bool state)
1005 {
1006         int reg;
1007         u32 val;
1008         bool cur_state;
1009
1010         reg = DPLL(pipe);
1011         val = I915_READ(reg);
1012         cur_state = !!(val & DPLL_VCO_ENABLE);
1013         WARN(cur_state != state,
1014              "PLL state assertion failure (expected %s, current %s)\n",
1015              state_string(state), state_string(cur_state));
1016 }
1017 #define assert_pll_enabled(d, p) assert_pll(d, p, true)
1018 #define assert_pll_disabled(d, p) assert_pll(d, p, false)
1019
1020 /* For ILK+ */
1021 static void assert_pch_pll(struct drm_i915_private *dev_priv,
1022                            struct intel_pch_pll *pll,
1023                            struct intel_crtc *crtc,
1024                            bool state)
1025 {
1026         u32 val;
1027         bool cur_state;
1028
1029         if (HAS_PCH_LPT(dev_priv->dev)) {
1030                 DRM_DEBUG_DRIVER("LPT detected: skipping PCH PLL test\n");
1031                 return;
1032         }
1033
1034         if (WARN (!pll,
1035                   "asserting PCH PLL %s with no PLL\n", state_string(state)))
1036                 return;
1037
1038         val = I915_READ(pll->pll_reg);
1039         cur_state = !!(val & DPLL_VCO_ENABLE);
1040         WARN(cur_state != state,
1041              "PCH PLL state for reg %x assertion failure (expected %s, current %s), val=%08x\n",
1042              pll->pll_reg, state_string(state), state_string(cur_state), val);
1043
1044         /* Make sure the selected PLL is correctly attached to the transcoder */
1045         if (crtc && HAS_PCH_CPT(dev_priv->dev)) {
1046                 u32 pch_dpll;
1047
1048                 pch_dpll = I915_READ(PCH_DPLL_SEL);
1049                 cur_state = pll->pll_reg == _PCH_DPLL_B;
1050                 if (!WARN(((pch_dpll >> (4 * crtc->pipe)) & 1) != cur_state,
1051                           "PLL[%d] not attached to this transcoder %d: %08x\n",
1052                           cur_state, crtc->pipe, pch_dpll)) {
1053                         cur_state = !!(val >> (4*crtc->pipe + 3));
1054                         WARN(cur_state != state,
1055                              "PLL[%d] not %s on this transcoder %d: %08x\n",
1056                              pll->pll_reg == _PCH_DPLL_B,
1057                              state_string(state),
1058                              crtc->pipe,
1059                              val);
1060                 }
1061         }
1062 }
1063 #define assert_pch_pll_enabled(d, p, c) assert_pch_pll(d, p, c, true)
1064 #define assert_pch_pll_disabled(d, p, c) assert_pch_pll(d, p, c, false)
1065
1066 static void assert_fdi_tx(struct drm_i915_private *dev_priv,
1067                           enum pipe pipe, bool state)
1068 {
1069         int reg;
1070         u32 val;
1071         bool cur_state;
1072         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1073                                                                       pipe);
1074
1075         if (IS_HASWELL(dev_priv->dev)) {
1076                 /* On Haswell, DDI is used instead of FDI_TX_CTL */
1077                 reg = TRANS_DDI_FUNC_CTL(cpu_transcoder);
1078                 val = I915_READ(reg);
1079                 cur_state = !!(val & TRANS_DDI_FUNC_ENABLE);
1080         } else {
1081                 reg = FDI_TX_CTL(pipe);
1082                 val = I915_READ(reg);
1083                 cur_state = !!(val & FDI_TX_ENABLE);
1084         }
1085         WARN(cur_state != state,
1086              "FDI TX state assertion failure (expected %s, current %s)\n",
1087              state_string(state), state_string(cur_state));
1088 }
1089 #define assert_fdi_tx_enabled(d, p) assert_fdi_tx(d, p, true)
1090 #define assert_fdi_tx_disabled(d, p) assert_fdi_tx(d, p, false)
1091
1092 static void assert_fdi_rx(struct drm_i915_private *dev_priv,
1093                           enum pipe pipe, bool state)
1094 {
1095         int reg;
1096         u32 val;
1097         bool cur_state;
1098
1099         reg = FDI_RX_CTL(pipe);
1100         val = I915_READ(reg);
1101         cur_state = !!(val & FDI_RX_ENABLE);
1102         WARN(cur_state != state,
1103              "FDI RX state assertion failure (expected %s, current %s)\n",
1104              state_string(state), state_string(cur_state));
1105 }
1106 #define assert_fdi_rx_enabled(d, p) assert_fdi_rx(d, p, true)
1107 #define assert_fdi_rx_disabled(d, p) assert_fdi_rx(d, p, false)
1108
1109 static void assert_fdi_tx_pll_enabled(struct drm_i915_private *dev_priv,
1110                                       enum pipe pipe)
1111 {
1112         int reg;
1113         u32 val;
1114
1115         /* ILK FDI PLL is always enabled */
1116         if (dev_priv->info->gen == 5)
1117                 return;
1118
1119         /* On Haswell, DDI ports are responsible for the FDI PLL setup */
1120         if (IS_HASWELL(dev_priv->dev))
1121                 return;
1122
1123         reg = FDI_TX_CTL(pipe);
1124         val = I915_READ(reg);
1125         WARN(!(val & FDI_TX_PLL_ENABLE), "FDI TX PLL assertion failure, should be active but is disabled\n");
1126 }
1127
1128 static void assert_fdi_rx_pll_enabled(struct drm_i915_private *dev_priv,
1129                                       enum pipe pipe)
1130 {
1131         int reg;
1132         u32 val;
1133
1134         reg = FDI_RX_CTL(pipe);
1135         val = I915_READ(reg);
1136         WARN(!(val & FDI_RX_PLL_ENABLE), "FDI RX PLL assertion failure, should be active but is disabled\n");
1137 }
1138
1139 static void assert_panel_unlocked(struct drm_i915_private *dev_priv,
1140                                   enum pipe pipe)
1141 {
1142         int pp_reg, lvds_reg;
1143         u32 val;
1144         enum pipe panel_pipe = PIPE_A;
1145         bool locked = true;
1146
1147         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1148                 pp_reg = PCH_PP_CONTROL;
1149                 lvds_reg = PCH_LVDS;
1150         } else {
1151                 pp_reg = PP_CONTROL;
1152                 lvds_reg = LVDS;
1153         }
1154
1155         val = I915_READ(pp_reg);
1156         if (!(val & PANEL_POWER_ON) ||
1157             ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS))
1158                 locked = false;
1159
1160         if (I915_READ(lvds_reg) & LVDS_PIPEB_SELECT)
1161                 panel_pipe = PIPE_B;
1162
1163         WARN(panel_pipe == pipe && locked,
1164              "panel assertion failure, pipe %c regs locked\n",
1165              pipe_name(pipe));
1166 }
1167
1168 void assert_pipe(struct drm_i915_private *dev_priv,
1169                  enum pipe pipe, bool state)
1170 {
1171         int reg;
1172         u32 val;
1173         bool cur_state;
1174         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1175                                                                       pipe);
1176
1177         /* if we need the pipe A quirk it must be always on */
1178         if (pipe == PIPE_A && dev_priv->quirks & QUIRK_PIPEA_FORCE)
1179                 state = true;
1180
1181         reg = PIPECONF(cpu_transcoder);
1182         val = I915_READ(reg);
1183         cur_state = !!(val & PIPECONF_ENABLE);
1184         WARN(cur_state != state,
1185              "pipe %c assertion failure (expected %s, current %s)\n",
1186              pipe_name(pipe), state_string(state), state_string(cur_state));
1187 }
1188
1189 static void assert_plane(struct drm_i915_private *dev_priv,
1190                          enum plane plane, bool state)
1191 {
1192         int reg;
1193         u32 val;
1194         bool cur_state;
1195
1196         reg = DSPCNTR(plane);
1197         val = I915_READ(reg);
1198         cur_state = !!(val & DISPLAY_PLANE_ENABLE);
1199         WARN(cur_state != state,
1200              "plane %c assertion failure (expected %s, current %s)\n",
1201              plane_name(plane), state_string(state), state_string(cur_state));
1202 }
1203
1204 #define assert_plane_enabled(d, p) assert_plane(d, p, true)
1205 #define assert_plane_disabled(d, p) assert_plane(d, p, false)
1206
1207 static void assert_planes_disabled(struct drm_i915_private *dev_priv,
1208                                    enum pipe pipe)
1209 {
1210         int reg, i;
1211         u32 val;
1212         int cur_pipe;
1213
1214         /* Planes are fixed to pipes on ILK+ */
1215         if (HAS_PCH_SPLIT(dev_priv->dev)) {
1216                 reg = DSPCNTR(pipe);
1217                 val = I915_READ(reg);
1218                 WARN((val & DISPLAY_PLANE_ENABLE),
1219                      "plane %c assertion failure, should be disabled but not\n",
1220                      plane_name(pipe));
1221                 return;
1222         }
1223
1224         /* Need to check both planes against the pipe */
1225         for (i = 0; i < 2; i++) {
1226                 reg = DSPCNTR(i);
1227                 val = I915_READ(reg);
1228                 cur_pipe = (val & DISPPLANE_SEL_PIPE_MASK) >>
1229                         DISPPLANE_SEL_PIPE_SHIFT;
1230                 WARN((val & DISPLAY_PLANE_ENABLE) && pipe == cur_pipe,
1231                      "plane %c assertion failure, should be off on pipe %c but is still active\n",
1232                      plane_name(i), pipe_name(pipe));
1233         }
1234 }
1235
1236 static void assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
1237 {
1238         u32 val;
1239         bool enabled;
1240
1241         if (HAS_PCH_LPT(dev_priv->dev)) {
1242                 DRM_DEBUG_DRIVER("LPT does not has PCH refclk, skipping check\n");
1243                 return;
1244         }
1245
1246         val = I915_READ(PCH_DREF_CONTROL);
1247         enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
1248                             DREF_SUPERSPREAD_SOURCE_MASK));
1249         WARN(!enabled, "PCH refclk assertion failure, should be active but is disabled\n");
1250 }
1251
1252 static void assert_transcoder_disabled(struct drm_i915_private *dev_priv,
1253                                        enum pipe pipe)
1254 {
1255         int reg;
1256         u32 val;
1257         bool enabled;
1258
1259         reg = TRANSCONF(pipe);
1260         val = I915_READ(reg);
1261         enabled = !!(val & TRANS_ENABLE);
1262         WARN(enabled,
1263              "transcoder assertion failed, should be off on pipe %c but is still active\n",
1264              pipe_name(pipe));
1265 }
1266
1267 static bool dp_pipe_enabled(struct drm_i915_private *dev_priv,
1268                             enum pipe pipe, u32 port_sel, u32 val)
1269 {
1270         if ((val & DP_PORT_EN) == 0)
1271                 return false;
1272
1273         if (HAS_PCH_CPT(dev_priv->dev)) {
1274                 u32     trans_dp_ctl_reg = TRANS_DP_CTL(pipe);
1275                 u32     trans_dp_ctl = I915_READ(trans_dp_ctl_reg);
1276                 if ((trans_dp_ctl & TRANS_DP_PORT_SEL_MASK) != port_sel)
1277                         return false;
1278         } else {
1279                 if ((val & DP_PIPE_MASK) != (pipe << 30))
1280                         return false;
1281         }
1282         return true;
1283 }
1284
1285 static bool hdmi_pipe_enabled(struct drm_i915_private *dev_priv,
1286                               enum pipe pipe, u32 val)
1287 {
1288         if ((val & PORT_ENABLE) == 0)
1289                 return false;
1290
1291         if (HAS_PCH_CPT(dev_priv->dev)) {
1292                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1293                         return false;
1294         } else {
1295                 if ((val & TRANSCODER_MASK) != TRANSCODER(pipe))
1296                         return false;
1297         }
1298         return true;
1299 }
1300
1301 static bool lvds_pipe_enabled(struct drm_i915_private *dev_priv,
1302                               enum pipe pipe, u32 val)
1303 {
1304         if ((val & LVDS_PORT_EN) == 0)
1305                 return false;
1306
1307         if (HAS_PCH_CPT(dev_priv->dev)) {
1308                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1309                         return false;
1310         } else {
1311                 if ((val & LVDS_PIPE_MASK) != LVDS_PIPE(pipe))
1312                         return false;
1313         }
1314         return true;
1315 }
1316
1317 static bool adpa_pipe_enabled(struct drm_i915_private *dev_priv,
1318                               enum pipe pipe, u32 val)
1319 {
1320         if ((val & ADPA_DAC_ENABLE) == 0)
1321                 return false;
1322         if (HAS_PCH_CPT(dev_priv->dev)) {
1323                 if ((val & PORT_TRANS_SEL_MASK) != PORT_TRANS_SEL_CPT(pipe))
1324                         return false;
1325         } else {
1326                 if ((val & ADPA_PIPE_SELECT_MASK) != ADPA_PIPE_SELECT(pipe))
1327                         return false;
1328         }
1329         return true;
1330 }
1331
1332 static void assert_pch_dp_disabled(struct drm_i915_private *dev_priv,
1333                                    enum pipe pipe, int reg, u32 port_sel)
1334 {
1335         u32 val = I915_READ(reg);
1336         WARN(dp_pipe_enabled(dev_priv, pipe, port_sel, val),
1337              "PCH DP (0x%08x) enabled on transcoder %c, should be disabled\n",
1338              reg, pipe_name(pipe));
1339
1340         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & DP_PORT_EN) == 0
1341              && (val & DP_PIPEB_SELECT),
1342              "IBX PCH dp port still using transcoder B\n");
1343 }
1344
1345 static void assert_pch_hdmi_disabled(struct drm_i915_private *dev_priv,
1346                                      enum pipe pipe, int reg)
1347 {
1348         u32 val = I915_READ(reg);
1349         WARN(hdmi_pipe_enabled(dev_priv, pipe, val),
1350              "PCH HDMI (0x%08x) enabled on transcoder %c, should be disabled\n",
1351              reg, pipe_name(pipe));
1352
1353         WARN(HAS_PCH_IBX(dev_priv->dev) && (val & PORT_ENABLE) == 0
1354              && (val & SDVO_PIPE_B_SELECT),
1355              "IBX PCH hdmi port still using transcoder B\n");
1356 }
1357
1358 static void assert_pch_ports_disabled(struct drm_i915_private *dev_priv,
1359                                       enum pipe pipe)
1360 {
1361         int reg;
1362         u32 val;
1363
1364         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_B, TRANS_DP_PORT_SEL_B);
1365         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_C, TRANS_DP_PORT_SEL_C);
1366         assert_pch_dp_disabled(dev_priv, pipe, PCH_DP_D, TRANS_DP_PORT_SEL_D);
1367
1368         reg = PCH_ADPA;
1369         val = I915_READ(reg);
1370         WARN(adpa_pipe_enabled(dev_priv, pipe, val),
1371              "PCH VGA enabled on transcoder %c, should be disabled\n",
1372              pipe_name(pipe));
1373
1374         reg = PCH_LVDS;
1375         val = I915_READ(reg);
1376         WARN(lvds_pipe_enabled(dev_priv, pipe, val),
1377              "PCH LVDS enabled on transcoder %c, should be disabled\n",
1378              pipe_name(pipe));
1379
1380         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIB);
1381         assert_pch_hdmi_disabled(dev_priv, pipe, HDMIC);
1382         assert_pch_hdmi_disabled(dev_priv, pipe, HDMID);
1383 }
1384
1385 /**
1386  * intel_enable_pll - enable a PLL
1387  * @dev_priv: i915 private structure
1388  * @pipe: pipe PLL to enable
1389  *
1390  * Enable @pipe's PLL so we can start pumping pixels from a plane.  Check to
1391  * make sure the PLL reg is writable first though, since the panel write
1392  * protect mechanism may be enabled.
1393  *
1394  * Note!  This is for pre-ILK only.
1395  *
1396  * Unfortunately needed by dvo_ns2501 since the dvo depends on it running.
1397  */
1398 static void intel_enable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1399 {
1400         int reg;
1401         u32 val;
1402
1403         /* No really, not for ILK+ */
1404         BUG_ON(!IS_VALLEYVIEW(dev_priv->dev) && dev_priv->info->gen >= 5);
1405
1406         /* PLL is protected by panel, make sure we can write it */
1407         if (IS_MOBILE(dev_priv->dev) && !IS_I830(dev_priv->dev))
1408                 assert_panel_unlocked(dev_priv, pipe);
1409
1410         reg = DPLL(pipe);
1411         val = I915_READ(reg);
1412         val |= DPLL_VCO_ENABLE;
1413
1414         /* We do this three times for luck */
1415         I915_WRITE(reg, val);
1416         POSTING_READ(reg);
1417         udelay(150); /* wait for warmup */
1418         I915_WRITE(reg, val);
1419         POSTING_READ(reg);
1420         udelay(150); /* wait for warmup */
1421         I915_WRITE(reg, val);
1422         POSTING_READ(reg);
1423         udelay(150); /* wait for warmup */
1424 }
1425
1426 /**
1427  * intel_disable_pll - disable a PLL
1428  * @dev_priv: i915 private structure
1429  * @pipe: pipe PLL to disable
1430  *
1431  * Disable the PLL for @pipe, making sure the pipe is off first.
1432  *
1433  * Note!  This is for pre-ILK only.
1434  */
1435 static void intel_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe)
1436 {
1437         int reg;
1438         u32 val;
1439
1440         /* Don't disable pipe A or pipe A PLLs if needed */
1441         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1442                 return;
1443
1444         /* Make sure the pipe isn't still relying on us */
1445         assert_pipe_disabled(dev_priv, pipe);
1446
1447         reg = DPLL(pipe);
1448         val = I915_READ(reg);
1449         val &= ~DPLL_VCO_ENABLE;
1450         I915_WRITE(reg, val);
1451         POSTING_READ(reg);
1452 }
1453
1454 /* SBI access */
1455 static void
1456 intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value)
1457 {
1458         unsigned long flags;
1459
1460         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1461         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1462                                 100)) {
1463                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1464                 goto out_unlock;
1465         }
1466
1467         I915_WRITE(SBI_ADDR,
1468                         (reg << 16));
1469         I915_WRITE(SBI_DATA,
1470                         value);
1471         I915_WRITE(SBI_CTL_STAT,
1472                         SBI_BUSY |
1473                         SBI_CTL_OP_CRWR);
1474
1475         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1476                                 100)) {
1477                 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
1478                 goto out_unlock;
1479         }
1480
1481 out_unlock:
1482         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1483 }
1484
1485 static u32
1486 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg)
1487 {
1488         unsigned long flags;
1489         u32 value = 0;
1490
1491         spin_lock_irqsave(&dev_priv->dpio_lock, flags);
1492         if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
1493                                 100)) {
1494                 DRM_ERROR("timeout waiting for SBI to become ready\n");
1495                 goto out_unlock;
1496         }
1497
1498         I915_WRITE(SBI_ADDR,
1499                         (reg << 16));
1500         I915_WRITE(SBI_CTL_STAT,
1501                         SBI_BUSY |
1502                         SBI_CTL_OP_CRRD);
1503
1504         if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
1505                                 100)) {
1506                 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
1507                 goto out_unlock;
1508         }
1509
1510         value = I915_READ(SBI_DATA);
1511
1512 out_unlock:
1513         spin_unlock_irqrestore(&dev_priv->dpio_lock, flags);
1514         return value;
1515 }
1516
1517 /**
1518  * ironlake_enable_pch_pll - enable PCH PLL
1519  * @dev_priv: i915 private structure
1520  * @pipe: pipe PLL to enable
1521  *
1522  * The PCH PLL needs to be enabled before the PCH transcoder, since it
1523  * drives the transcoder clock.
1524  */
1525 static void ironlake_enable_pch_pll(struct intel_crtc *intel_crtc)
1526 {
1527         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1528         struct intel_pch_pll *pll;
1529         int reg;
1530         u32 val;
1531
1532         /* PCH PLLs only available on ILK, SNB and IVB */
1533         BUG_ON(dev_priv->info->gen < 5);
1534         pll = intel_crtc->pch_pll;
1535         if (pll == NULL)
1536                 return;
1537
1538         if (WARN_ON(pll->refcount == 0))
1539                 return;
1540
1541         DRM_DEBUG_KMS("enable PCH PLL %x (active %d, on? %d)for crtc %d\n",
1542                       pll->pll_reg, pll->active, pll->on,
1543                       intel_crtc->base.base.id);
1544
1545         /* PCH refclock must be enabled first */
1546         assert_pch_refclk_enabled(dev_priv);
1547
1548         if (pll->active++ && pll->on) {
1549                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1550                 return;
1551         }
1552
1553         DRM_DEBUG_KMS("enabling PCH PLL %x\n", pll->pll_reg);
1554
1555         reg = pll->pll_reg;
1556         val = I915_READ(reg);
1557         val |= DPLL_VCO_ENABLE;
1558         I915_WRITE(reg, val);
1559         POSTING_READ(reg);
1560         udelay(200);
1561
1562         pll->on = true;
1563 }
1564
1565 static void intel_disable_pch_pll(struct intel_crtc *intel_crtc)
1566 {
1567         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
1568         struct intel_pch_pll *pll = intel_crtc->pch_pll;
1569         int reg;
1570         u32 val;
1571
1572         /* PCH only available on ILK+ */
1573         BUG_ON(dev_priv->info->gen < 5);
1574         if (pll == NULL)
1575                return;
1576
1577         if (WARN_ON(pll->refcount == 0))
1578                 return;
1579
1580         DRM_DEBUG_KMS("disable PCH PLL %x (active %d, on? %d) for crtc %d\n",
1581                       pll->pll_reg, pll->active, pll->on,
1582                       intel_crtc->base.base.id);
1583
1584         if (WARN_ON(pll->active == 0)) {
1585                 assert_pch_pll_disabled(dev_priv, pll, NULL);
1586                 return;
1587         }
1588
1589         if (--pll->active) {
1590                 assert_pch_pll_enabled(dev_priv, pll, NULL);
1591                 return;
1592         }
1593
1594         DRM_DEBUG_KMS("disabling PCH PLL %x\n", pll->pll_reg);
1595
1596         /* Make sure transcoder isn't still depending on us */
1597         assert_transcoder_disabled(dev_priv, intel_crtc->pipe);
1598
1599         reg = pll->pll_reg;
1600         val = I915_READ(reg);
1601         val &= ~DPLL_VCO_ENABLE;
1602         I915_WRITE(reg, val);
1603         POSTING_READ(reg);
1604         udelay(200);
1605
1606         pll->on = false;
1607 }
1608
1609 static void ironlake_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1610                                            enum pipe pipe)
1611 {
1612         struct drm_device *dev = dev_priv->dev;
1613         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
1614         uint32_t reg, val, pipeconf_val;
1615
1616         /* PCH only available on ILK+ */
1617         BUG_ON(dev_priv->info->gen < 5);
1618
1619         /* Make sure PCH DPLL is enabled */
1620         assert_pch_pll_enabled(dev_priv,
1621                                to_intel_crtc(crtc)->pch_pll,
1622                                to_intel_crtc(crtc));
1623
1624         /* FDI must be feeding us bits for PCH ports */
1625         assert_fdi_tx_enabled(dev_priv, pipe);
1626         assert_fdi_rx_enabled(dev_priv, pipe);
1627
1628         if (HAS_PCH_CPT(dev)) {
1629                 /* Workaround: Set the timing override bit before enabling the
1630                  * pch transcoder. */
1631                 reg = TRANS_CHICKEN2(pipe);
1632                 val = I915_READ(reg);
1633                 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1634                 I915_WRITE(reg, val);
1635         }
1636
1637         reg = TRANSCONF(pipe);
1638         val = I915_READ(reg);
1639         pipeconf_val = I915_READ(PIPECONF(pipe));
1640
1641         if (HAS_PCH_IBX(dev_priv->dev)) {
1642                 /*
1643                  * make the BPC in transcoder be consistent with
1644                  * that in pipeconf reg.
1645                  */
1646                 val &= ~PIPE_BPC_MASK;
1647                 val |= pipeconf_val & PIPE_BPC_MASK;
1648         }
1649
1650         val &= ~TRANS_INTERLACE_MASK;
1651         if ((pipeconf_val & PIPECONF_INTERLACE_MASK) == PIPECONF_INTERLACED_ILK)
1652                 if (HAS_PCH_IBX(dev_priv->dev) &&
1653                     intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO))
1654                         val |= TRANS_LEGACY_INTERLACED_ILK;
1655                 else
1656                         val |= TRANS_INTERLACED;
1657         else
1658                 val |= TRANS_PROGRESSIVE;
1659
1660         I915_WRITE(reg, val | TRANS_ENABLE);
1661         if (wait_for(I915_READ(reg) & TRANS_STATE_ENABLE, 100))
1662                 DRM_ERROR("failed to enable transcoder %d\n", pipe);
1663 }
1664
1665 static void lpt_enable_pch_transcoder(struct drm_i915_private *dev_priv,
1666                                       enum transcoder cpu_transcoder)
1667 {
1668         u32 val, pipeconf_val;
1669
1670         /* PCH only available on ILK+ */
1671         BUG_ON(dev_priv->info->gen < 5);
1672
1673         /* FDI must be feeding us bits for PCH ports */
1674         assert_fdi_tx_enabled(dev_priv, cpu_transcoder);
1675         assert_fdi_rx_enabled(dev_priv, TRANSCODER_A);
1676
1677         /* Workaround: set timing override bit. */
1678         val = I915_READ(_TRANSA_CHICKEN2);
1679         val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
1680         I915_WRITE(_TRANSA_CHICKEN2, val);
1681
1682         val = TRANS_ENABLE;
1683         pipeconf_val = I915_READ(PIPECONF(cpu_transcoder));
1684
1685         if ((pipeconf_val & PIPECONF_INTERLACE_MASK_HSW) ==
1686             PIPECONF_INTERLACED_ILK)
1687                 val |= TRANS_INTERLACED;
1688         else
1689                 val |= TRANS_PROGRESSIVE;
1690
1691         I915_WRITE(TRANSCONF(TRANSCODER_A), val);
1692         if (wait_for(I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE, 100))
1693                 DRM_ERROR("Failed to enable PCH transcoder\n");
1694 }
1695
1696 static void ironlake_disable_pch_transcoder(struct drm_i915_private *dev_priv,
1697                                             enum pipe pipe)
1698 {
1699         struct drm_device *dev = dev_priv->dev;
1700         uint32_t reg, val;
1701
1702         /* FDI relies on the transcoder */
1703         assert_fdi_tx_disabled(dev_priv, pipe);
1704         assert_fdi_rx_disabled(dev_priv, pipe);
1705
1706         /* Ports must be off as well */
1707         assert_pch_ports_disabled(dev_priv, pipe);
1708
1709         reg = TRANSCONF(pipe);
1710         val = I915_READ(reg);
1711         val &= ~TRANS_ENABLE;
1712         I915_WRITE(reg, val);
1713         /* wait for PCH transcoder off, transcoder state */
1714         if (wait_for((I915_READ(reg) & TRANS_STATE_ENABLE) == 0, 50))
1715                 DRM_ERROR("failed to disable transcoder %d\n", pipe);
1716
1717         if (!HAS_PCH_IBX(dev)) {
1718                 /* Workaround: Clear the timing override chicken bit again. */
1719                 reg = TRANS_CHICKEN2(pipe);
1720                 val = I915_READ(reg);
1721                 val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1722                 I915_WRITE(reg, val);
1723         }
1724 }
1725
1726 static void lpt_disable_pch_transcoder(struct drm_i915_private *dev_priv)
1727 {
1728         u32 val;
1729
1730         val = I915_READ(_TRANSACONF);
1731         val &= ~TRANS_ENABLE;
1732         I915_WRITE(_TRANSACONF, val);
1733         /* wait for PCH transcoder off, transcoder state */
1734         if (wait_for((I915_READ(_TRANSACONF) & TRANS_STATE_ENABLE) == 0, 50))
1735                 DRM_ERROR("Failed to disable PCH transcoder\n");
1736
1737         /* Workaround: clear timing override bit. */
1738         val = I915_READ(_TRANSA_CHICKEN2);
1739         val &= ~TRANS_CHICKEN2_TIMING_OVERRIDE;
1740         I915_WRITE(_TRANSA_CHICKEN2, val);
1741 }
1742
1743 /**
1744  * intel_enable_pipe - enable a pipe, asserting requirements
1745  * @dev_priv: i915 private structure
1746  * @pipe: pipe to enable
1747  * @pch_port: on ILK+, is this pipe driving a PCH port or not
1748  *
1749  * Enable @pipe, making sure that various hardware specific requirements
1750  * are met, if applicable, e.g. PLL enabled, LVDS pairs enabled, etc.
1751  *
1752  * @pipe should be %PIPE_A or %PIPE_B.
1753  *
1754  * Will wait until the pipe is actually running (i.e. first vblank) before
1755  * returning.
1756  */
1757 static void intel_enable_pipe(struct drm_i915_private *dev_priv, enum pipe pipe,
1758                               bool pch_port)
1759 {
1760         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1761                                                                       pipe);
1762         enum transcoder pch_transcoder;
1763         int reg;
1764         u32 val;
1765
1766         if (IS_HASWELL(dev_priv->dev))
1767                 pch_transcoder = TRANSCODER_A;
1768         else
1769                 pch_transcoder = pipe;
1770
1771         /*
1772          * A pipe without a PLL won't actually be able to drive bits from
1773          * a plane.  On ILK+ the pipe PLLs are integrated, so we don't
1774          * need the check.
1775          */
1776         if (!HAS_PCH_SPLIT(dev_priv->dev))
1777                 assert_pll_enabled(dev_priv, pipe);
1778         else {
1779                 if (pch_port) {
1780                         /* if driving the PCH, we need FDI enabled */
1781                         assert_fdi_rx_pll_enabled(dev_priv, pch_transcoder);
1782                         assert_fdi_tx_pll_enabled(dev_priv, cpu_transcoder);
1783                 }
1784                 /* FIXME: assert CPU port conditions for SNB+ */
1785         }
1786
1787         reg = PIPECONF(cpu_transcoder);
1788         val = I915_READ(reg);
1789         if (val & PIPECONF_ENABLE)
1790                 return;
1791
1792         I915_WRITE(reg, val | PIPECONF_ENABLE);
1793         intel_wait_for_vblank(dev_priv->dev, pipe);
1794 }
1795
1796 /**
1797  * intel_disable_pipe - disable a pipe, asserting requirements
1798  * @dev_priv: i915 private structure
1799  * @pipe: pipe to disable
1800  *
1801  * Disable @pipe, making sure that various hardware specific requirements
1802  * are met, if applicable, e.g. plane disabled, panel fitter off, etc.
1803  *
1804  * @pipe should be %PIPE_A or %PIPE_B.
1805  *
1806  * Will wait until the pipe has shut down before returning.
1807  */
1808 static void intel_disable_pipe(struct drm_i915_private *dev_priv,
1809                                enum pipe pipe)
1810 {
1811         enum transcoder cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv,
1812                                                                       pipe);
1813         int reg;
1814         u32 val;
1815
1816         /*
1817          * Make sure planes won't keep trying to pump pixels to us,
1818          * or we might hang the display.
1819          */
1820         assert_planes_disabled(dev_priv, pipe);
1821
1822         /* Don't disable pipe A or pipe A PLLs if needed */
1823         if (pipe == PIPE_A && (dev_priv->quirks & QUIRK_PIPEA_FORCE))
1824                 return;
1825
1826         reg = PIPECONF(cpu_transcoder);
1827         val = I915_READ(reg);
1828         if ((val & PIPECONF_ENABLE) == 0)
1829                 return;
1830
1831         I915_WRITE(reg, val & ~PIPECONF_ENABLE);
1832         intel_wait_for_pipe_off(dev_priv->dev, pipe);
1833 }
1834
1835 /*
1836  * Plane regs are double buffered, going from enabled->disabled needs a
1837  * trigger in order to latch.  The display address reg provides this.
1838  */
1839 void intel_flush_display_plane(struct drm_i915_private *dev_priv,
1840                                       enum plane plane)
1841 {
1842         if (dev_priv->info->gen >= 4)
1843                 I915_WRITE(DSPSURF(plane), I915_READ(DSPSURF(plane)));
1844         else
1845                 I915_WRITE(DSPADDR(plane), I915_READ(DSPADDR(plane)));
1846 }
1847
1848 /**
1849  * intel_enable_plane - enable a display plane on a given pipe
1850  * @dev_priv: i915 private structure
1851  * @plane: plane to enable
1852  * @pipe: pipe being fed
1853  *
1854  * Enable @plane on @pipe, making sure that @pipe is running first.
1855  */
1856 static void intel_enable_plane(struct drm_i915_private *dev_priv,
1857                                enum plane plane, enum pipe pipe)
1858 {
1859         int reg;
1860         u32 val;
1861
1862         /* If the pipe isn't enabled, we can't pump pixels and may hang */
1863         assert_pipe_enabled(dev_priv, pipe);
1864
1865         reg = DSPCNTR(plane);
1866         val = I915_READ(reg);
1867         if (val & DISPLAY_PLANE_ENABLE)
1868                 return;
1869
1870         I915_WRITE(reg, val | DISPLAY_PLANE_ENABLE);
1871         intel_flush_display_plane(dev_priv, plane);
1872         intel_wait_for_vblank(dev_priv->dev, pipe);
1873 }
1874
1875 /**
1876  * intel_disable_plane - disable a display plane
1877  * @dev_priv: i915 private structure
1878  * @plane: plane to disable
1879  * @pipe: pipe consuming the data
1880  *
1881  * Disable @plane; should be an independent operation.
1882  */
1883 static void intel_disable_plane(struct drm_i915_private *dev_priv,
1884                                 enum plane plane, enum pipe pipe)
1885 {
1886         int reg;
1887         u32 val;
1888
1889         reg = DSPCNTR(plane);
1890         val = I915_READ(reg);
1891         if ((val & DISPLAY_PLANE_ENABLE) == 0)
1892                 return;
1893
1894         I915_WRITE(reg, val & ~DISPLAY_PLANE_ENABLE);
1895         intel_flush_display_plane(dev_priv, plane);
1896         intel_wait_for_vblank(dev_priv->dev, pipe);
1897 }
1898
1899 int
1900 intel_pin_and_fence_fb_obj(struct drm_device *dev,
1901                            struct drm_i915_gem_object *obj,
1902                            struct intel_ring_buffer *pipelined)
1903 {
1904         struct drm_i915_private *dev_priv = dev->dev_private;
1905         u32 alignment;
1906         int ret;
1907
1908         switch (obj->tiling_mode) {
1909         case I915_TILING_NONE:
1910                 if (IS_BROADWATER(dev) || IS_CRESTLINE(dev))
1911                         alignment = 128 * 1024;
1912                 else if (INTEL_INFO(dev)->gen >= 4)
1913                         alignment = 4 * 1024;
1914                 else
1915                         alignment = 64 * 1024;
1916                 break;
1917         case I915_TILING_X:
1918                 /* pin() will align the object as required by fence */
1919                 alignment = 0;
1920                 break;
1921         case I915_TILING_Y:
1922                 /* FIXME: Is this true? */
1923                 DRM_ERROR("Y tiled not allowed for scan out buffers\n");
1924                 return -EINVAL;
1925         default:
1926                 BUG();
1927         }
1928
1929         dev_priv->mm.interruptible = false;
1930         ret = i915_gem_object_pin_to_display_plane(obj, alignment, pipelined);
1931         if (ret)
1932                 goto err_interruptible;
1933
1934         /* Install a fence for tiled scan-out. Pre-i965 always needs a
1935          * fence, whereas 965+ only requires a fence if using
1936          * framebuffer compression.  For simplicity, we always install
1937          * a fence as the cost is not that onerous.
1938          */
1939         ret = i915_gem_object_get_fence(obj);
1940         if (ret)
1941                 goto err_unpin;
1942
1943         i915_gem_object_pin_fence(obj);
1944
1945         dev_priv->mm.interruptible = true;
1946         return 0;
1947
1948 err_unpin:
1949         i915_gem_object_unpin(obj);
1950 err_interruptible:
1951         dev_priv->mm.interruptible = true;
1952         return ret;
1953 }
1954
1955 void intel_unpin_fb_obj(struct drm_i915_gem_object *obj)
1956 {
1957         i915_gem_object_unpin_fence(obj);
1958         i915_gem_object_unpin(obj);
1959 }
1960
1961 /* Computes the linear offset to the base tile and adjusts x, y. bytes per pixel
1962  * is assumed to be a power-of-two. */
1963 unsigned long intel_gen4_compute_offset_xtiled(int *x, int *y,
1964                                                unsigned int bpp,
1965                                                unsigned int pitch)
1966 {
1967         int tile_rows, tiles;
1968
1969         tile_rows = *y / 8;
1970         *y %= 8;
1971         tiles = *x / (512/bpp);
1972         *x %= 512/bpp;
1973
1974         return tile_rows * pitch * 8 + tiles * 4096;
1975 }
1976
1977 static int i9xx_update_plane(struct drm_crtc *crtc, struct drm_framebuffer *fb,
1978                              int x, int y)
1979 {
1980         struct drm_device *dev = crtc->dev;
1981         struct drm_i915_private *dev_priv = dev->dev_private;
1982         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1983         struct intel_framebuffer *intel_fb;
1984         struct drm_i915_gem_object *obj;
1985         int plane = intel_crtc->plane;
1986         unsigned long linear_offset;
1987         u32 dspcntr;
1988         u32 reg;
1989
1990         switch (plane) {
1991         case 0:
1992         case 1:
1993                 break;
1994         default:
1995                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
1996                 return -EINVAL;
1997         }
1998
1999         intel_fb = to_intel_framebuffer(fb);
2000         obj = intel_fb->obj;
2001
2002         reg = DSPCNTR(plane);
2003         dspcntr = I915_READ(reg);
2004         /* Mask out pixel format bits in case we change it */
2005         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2006         switch (fb->pixel_format) {
2007         case DRM_FORMAT_C8:
2008                 dspcntr |= DISPPLANE_8BPP;
2009                 break;
2010         case DRM_FORMAT_XRGB1555:
2011         case DRM_FORMAT_ARGB1555:
2012                 dspcntr |= DISPPLANE_BGRX555;
2013                 break;
2014         case DRM_FORMAT_RGB565:
2015                 dspcntr |= DISPPLANE_BGRX565;
2016                 break;
2017         case DRM_FORMAT_XRGB8888:
2018         case DRM_FORMAT_ARGB8888:
2019                 dspcntr |= DISPPLANE_BGRX888;
2020                 break;
2021         case DRM_FORMAT_XBGR8888:
2022         case DRM_FORMAT_ABGR8888:
2023                 dspcntr |= DISPPLANE_RGBX888;
2024                 break;
2025         case DRM_FORMAT_XRGB2101010:
2026         case DRM_FORMAT_ARGB2101010:
2027                 dspcntr |= DISPPLANE_BGRX101010;
2028                 break;
2029         case DRM_FORMAT_XBGR2101010:
2030         case DRM_FORMAT_ABGR2101010:
2031                 dspcntr |= DISPPLANE_RGBX101010;
2032                 break;
2033         default:
2034                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2035                 return -EINVAL;
2036         }
2037
2038         if (INTEL_INFO(dev)->gen >= 4) {
2039                 if (obj->tiling_mode != I915_TILING_NONE)
2040                         dspcntr |= DISPPLANE_TILED;
2041                 else
2042                         dspcntr &= ~DISPPLANE_TILED;
2043         }
2044
2045         I915_WRITE(reg, dspcntr);
2046
2047         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2048
2049         if (INTEL_INFO(dev)->gen >= 4) {
2050                 intel_crtc->dspaddr_offset =
2051                         intel_gen4_compute_offset_xtiled(&x, &y,
2052                                                          fb->bits_per_pixel / 8,
2053                                                          fb->pitches[0]);
2054                 linear_offset -= intel_crtc->dspaddr_offset;
2055         } else {
2056                 intel_crtc->dspaddr_offset = linear_offset;
2057         }
2058
2059         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2060                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2061         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2062         if (INTEL_INFO(dev)->gen >= 4) {
2063                 I915_MODIFY_DISPBASE(DSPSURF(plane),
2064                                      obj->gtt_offset + intel_crtc->dspaddr_offset);
2065                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2066                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2067         } else
2068                 I915_WRITE(DSPADDR(plane), obj->gtt_offset + linear_offset);
2069         POSTING_READ(reg);
2070
2071         return 0;
2072 }
2073
2074 static int ironlake_update_plane(struct drm_crtc *crtc,
2075                                  struct drm_framebuffer *fb, int x, int y)
2076 {
2077         struct drm_device *dev = crtc->dev;
2078         struct drm_i915_private *dev_priv = dev->dev_private;
2079         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2080         struct intel_framebuffer *intel_fb;
2081         struct drm_i915_gem_object *obj;
2082         int plane = intel_crtc->plane;
2083         unsigned long linear_offset;
2084         u32 dspcntr;
2085         u32 reg;
2086
2087         switch (plane) {
2088         case 0:
2089         case 1:
2090         case 2:
2091                 break;
2092         default:
2093                 DRM_ERROR("Can't update plane %d in SAREA\n", plane);
2094                 return -EINVAL;
2095         }
2096
2097         intel_fb = to_intel_framebuffer(fb);
2098         obj = intel_fb->obj;
2099
2100         reg = DSPCNTR(plane);
2101         dspcntr = I915_READ(reg);
2102         /* Mask out pixel format bits in case we change it */
2103         dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
2104         switch (fb->pixel_format) {
2105         case DRM_FORMAT_C8:
2106                 dspcntr |= DISPPLANE_8BPP;
2107                 break;
2108         case DRM_FORMAT_RGB565:
2109                 dspcntr |= DISPPLANE_BGRX565;
2110                 break;
2111         case DRM_FORMAT_XRGB8888:
2112         case DRM_FORMAT_ARGB8888:
2113                 dspcntr |= DISPPLANE_BGRX888;
2114                 break;
2115         case DRM_FORMAT_XBGR8888:
2116         case DRM_FORMAT_ABGR8888:
2117                 dspcntr |= DISPPLANE_RGBX888;
2118                 break;
2119         case DRM_FORMAT_XRGB2101010:
2120         case DRM_FORMAT_ARGB2101010:
2121                 dspcntr |= DISPPLANE_BGRX101010;
2122                 break;
2123         case DRM_FORMAT_XBGR2101010:
2124         case DRM_FORMAT_ABGR2101010:
2125                 dspcntr |= DISPPLANE_RGBX101010;
2126                 break;
2127         default:
2128                 DRM_ERROR("Unknown pixel format 0x%08x\n", fb->pixel_format);
2129                 return -EINVAL;
2130         }
2131
2132         if (obj->tiling_mode != I915_TILING_NONE)
2133                 dspcntr |= DISPPLANE_TILED;
2134         else
2135                 dspcntr &= ~DISPPLANE_TILED;
2136
2137         /* must disable */
2138         dspcntr |= DISPPLANE_TRICKLE_FEED_DISABLE;
2139
2140         I915_WRITE(reg, dspcntr);
2141
2142         linear_offset = y * fb->pitches[0] + x * (fb->bits_per_pixel / 8);
2143         intel_crtc->dspaddr_offset =
2144                 intel_gen4_compute_offset_xtiled(&x, &y,
2145                                                  fb->bits_per_pixel / 8,
2146                                                  fb->pitches[0]);
2147         linear_offset -= intel_crtc->dspaddr_offset;
2148
2149         DRM_DEBUG_KMS("Writing base %08X %08lX %d %d %d\n",
2150                       obj->gtt_offset, linear_offset, x, y, fb->pitches[0]);
2151         I915_WRITE(DSPSTRIDE(plane), fb->pitches[0]);
2152         I915_MODIFY_DISPBASE(DSPSURF(plane),
2153                              obj->gtt_offset + intel_crtc->dspaddr_offset);
2154         if (IS_HASWELL(dev)) {
2155                 I915_WRITE(DSPOFFSET(plane), (y << 16) | x);
2156         } else {
2157                 I915_WRITE(DSPTILEOFF(plane), (y << 16) | x);
2158                 I915_WRITE(DSPLINOFF(plane), linear_offset);
2159         }
2160         POSTING_READ(reg);
2161
2162         return 0;
2163 }
2164
2165 /* Assume fb object is pinned & idle & fenced and just update base pointers */
2166 static int
2167 intel_pipe_set_base_atomic(struct drm_crtc *crtc, struct drm_framebuffer *fb,
2168                            int x, int y, enum mode_set_atomic state)
2169 {
2170         struct drm_device *dev = crtc->dev;
2171         struct drm_i915_private *dev_priv = dev->dev_private;
2172
2173         if (dev_priv->display.disable_fbc)
2174                 dev_priv->display.disable_fbc(dev);
2175         intel_increase_pllclock(crtc);
2176
2177         return dev_priv->display.update_plane(crtc, fb, x, y);
2178 }
2179
2180 static int
2181 intel_finish_fb(struct drm_framebuffer *old_fb)
2182 {
2183         struct drm_i915_gem_object *obj = to_intel_framebuffer(old_fb)->obj;
2184         struct drm_i915_private *dev_priv = obj->base.dev->dev_private;
2185         bool was_interruptible = dev_priv->mm.interruptible;
2186         int ret;
2187
2188         wait_event(dev_priv->pending_flip_queue,
2189                    atomic_read(&dev_priv->mm.wedged) ||
2190                    atomic_read(&obj->pending_flip) == 0);
2191
2192         /* Big Hammer, we also need to ensure that any pending
2193          * MI_WAIT_FOR_EVENT inside a user batch buffer on the
2194          * current scanout is retired before unpinning the old
2195          * framebuffer.
2196          *
2197          * This should only fail upon a hung GPU, in which case we
2198          * can safely continue.
2199          */
2200         dev_priv->mm.interruptible = false;
2201         ret = i915_gem_object_finish_gpu(obj);
2202         dev_priv->mm.interruptible = was_interruptible;
2203
2204         return ret;
2205 }
2206
2207 static void intel_crtc_update_sarea_pos(struct drm_crtc *crtc, int x, int y)
2208 {
2209         struct drm_device *dev = crtc->dev;
2210         struct drm_i915_master_private *master_priv;
2211         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2212
2213         if (!dev->primary->master)
2214                 return;
2215
2216         master_priv = dev->primary->master->driver_priv;
2217         if (!master_priv->sarea_priv)
2218                 return;
2219
2220         switch (intel_crtc->pipe) {
2221         case 0:
2222                 master_priv->sarea_priv->pipeA_x = x;
2223                 master_priv->sarea_priv->pipeA_y = y;
2224                 break;
2225         case 1:
2226                 master_priv->sarea_priv->pipeB_x = x;
2227                 master_priv->sarea_priv->pipeB_y = y;
2228                 break;
2229         default:
2230                 break;
2231         }
2232 }
2233
2234 static int
2235 intel_pipe_set_base(struct drm_crtc *crtc, int x, int y,
2236                     struct drm_framebuffer *fb)
2237 {
2238         struct drm_device *dev = crtc->dev;
2239         struct drm_i915_private *dev_priv = dev->dev_private;
2240         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2241         struct drm_framebuffer *old_fb;
2242         int ret;
2243
2244         /* no fb bound */
2245         if (!fb) {
2246                 DRM_ERROR("No FB bound\n");
2247                 return 0;
2248         }
2249
2250         if(intel_crtc->plane > dev_priv->num_pipe) {
2251                 DRM_ERROR("no plane for crtc: plane %d, num_pipes %d\n",
2252                                 intel_crtc->plane,
2253                                 dev_priv->num_pipe);
2254                 return -EINVAL;
2255         }
2256
2257         mutex_lock(&dev->struct_mutex);
2258         ret = intel_pin_and_fence_fb_obj(dev,
2259                                          to_intel_framebuffer(fb)->obj,
2260                                          NULL);
2261         if (ret != 0) {
2262                 mutex_unlock(&dev->struct_mutex);
2263                 DRM_ERROR("pin & fence failed\n");
2264                 return ret;
2265         }
2266
2267         if (crtc->fb)
2268                 intel_finish_fb(crtc->fb);
2269
2270         ret = dev_priv->display.update_plane(crtc, fb, x, y);
2271         if (ret) {
2272                 intel_unpin_fb_obj(to_intel_framebuffer(fb)->obj);
2273                 mutex_unlock(&dev->struct_mutex);
2274                 DRM_ERROR("failed to update base address\n");
2275                 return ret;
2276         }
2277
2278         old_fb = crtc->fb;
2279         crtc->fb = fb;
2280         crtc->x = x;
2281         crtc->y = y;
2282
2283         if (old_fb) {
2284                 intel_wait_for_vblank(dev, intel_crtc->pipe);
2285                 intel_unpin_fb_obj(to_intel_framebuffer(old_fb)->obj);
2286         }
2287
2288         intel_update_fbc(dev);
2289         mutex_unlock(&dev->struct_mutex);
2290
2291         intel_crtc_update_sarea_pos(crtc, x, y);
2292
2293         return 0;
2294 }
2295
2296 static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock)
2297 {
2298         struct drm_device *dev = crtc->dev;
2299         struct drm_i915_private *dev_priv = dev->dev_private;
2300         u32 dpa_ctl;
2301
2302         DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock);
2303         dpa_ctl = I915_READ(DP_A);
2304         dpa_ctl &= ~DP_PLL_FREQ_MASK;
2305
2306         if (clock < 200000) {
2307                 u32 temp;
2308                 dpa_ctl |= DP_PLL_FREQ_160MHZ;
2309                 /* workaround for 160Mhz:
2310                    1) program 0x4600c bits 15:0 = 0x8124
2311                    2) program 0x46010 bit 0 = 1
2312                    3) program 0x46034 bit 24 = 1
2313                    4) program 0x64000 bit 14 = 1
2314                    */
2315                 temp = I915_READ(0x4600c);
2316                 temp &= 0xffff0000;
2317                 I915_WRITE(0x4600c, temp | 0x8124);
2318
2319                 temp = I915_READ(0x46010);
2320                 I915_WRITE(0x46010, temp | 1);
2321
2322                 temp = I915_READ(0x46034);
2323                 I915_WRITE(0x46034, temp | (1 << 24));
2324         } else {
2325                 dpa_ctl |= DP_PLL_FREQ_270MHZ;
2326         }
2327         I915_WRITE(DP_A, dpa_ctl);
2328
2329         POSTING_READ(DP_A);
2330         udelay(500);
2331 }
2332
2333 static void intel_fdi_normal_train(struct drm_crtc *crtc)
2334 {
2335         struct drm_device *dev = crtc->dev;
2336         struct drm_i915_private *dev_priv = dev->dev_private;
2337         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2338         int pipe = intel_crtc->pipe;
2339         u32 reg, temp;
2340
2341         /* enable normal train */
2342         reg = FDI_TX_CTL(pipe);
2343         temp = I915_READ(reg);
2344         if (IS_IVYBRIDGE(dev)) {
2345                 temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2346                 temp |= FDI_LINK_TRAIN_NONE_IVB | FDI_TX_ENHANCE_FRAME_ENABLE;
2347         } else {
2348                 temp &= ~FDI_LINK_TRAIN_NONE;
2349                 temp |= FDI_LINK_TRAIN_NONE | FDI_TX_ENHANCE_FRAME_ENABLE;
2350         }
2351         I915_WRITE(reg, temp);
2352
2353         reg = FDI_RX_CTL(pipe);
2354         temp = I915_READ(reg);
2355         if (HAS_PCH_CPT(dev)) {
2356                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2357                 temp |= FDI_LINK_TRAIN_NORMAL_CPT;
2358         } else {
2359                 temp &= ~FDI_LINK_TRAIN_NONE;
2360                 temp |= FDI_LINK_TRAIN_NONE;
2361         }
2362         I915_WRITE(reg, temp | FDI_RX_ENHANCE_FRAME_ENABLE);
2363
2364         /* wait one idle pattern time */
2365         POSTING_READ(reg);
2366         udelay(1000);
2367
2368         /* IVB wants error correction enabled */
2369         if (IS_IVYBRIDGE(dev))
2370                 I915_WRITE(reg, I915_READ(reg) | FDI_FS_ERRC_ENABLE |
2371                            FDI_FE_ERRC_ENABLE);
2372 }
2373
2374 static void cpt_phase_pointer_enable(struct drm_device *dev, int pipe)
2375 {
2376         struct drm_i915_private *dev_priv = dev->dev_private;
2377         u32 flags = I915_READ(SOUTH_CHICKEN1);
2378
2379         flags |= FDI_PHASE_SYNC_OVR(pipe);
2380         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to unlock... */
2381         flags |= FDI_PHASE_SYNC_EN(pipe);
2382         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to enable */
2383         POSTING_READ(SOUTH_CHICKEN1);
2384 }
2385
2386 static void ivb_modeset_global_resources(struct drm_device *dev)
2387 {
2388         struct drm_i915_private *dev_priv = dev->dev_private;
2389         struct intel_crtc *pipe_B_crtc =
2390                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
2391         struct intel_crtc *pipe_C_crtc =
2392                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_C]);
2393         uint32_t temp;
2394
2395         /* When everything is off disable fdi C so that we could enable fdi B
2396          * with all lanes. XXX: This misses the case where a pipe is not using
2397          * any pch resources and so doesn't need any fdi lanes. */
2398         if (!pipe_B_crtc->base.enabled && !pipe_C_crtc->base.enabled) {
2399                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
2400                 WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
2401
2402                 temp = I915_READ(SOUTH_CHICKEN1);
2403                 temp &= ~FDI_BC_BIFURCATION_SELECT;
2404                 DRM_DEBUG_KMS("disabling fdi C rx\n");
2405                 I915_WRITE(SOUTH_CHICKEN1, temp);
2406         }
2407 }
2408
2409 /* The FDI link training functions for ILK/Ibexpeak. */
2410 static void ironlake_fdi_link_train(struct drm_crtc *crtc)
2411 {
2412         struct drm_device *dev = crtc->dev;
2413         struct drm_i915_private *dev_priv = dev->dev_private;
2414         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2415         int pipe = intel_crtc->pipe;
2416         int plane = intel_crtc->plane;
2417         u32 reg, temp, tries;
2418
2419         /* FDI needs bits from pipe & plane first */
2420         assert_pipe_enabled(dev_priv, pipe);
2421         assert_plane_enabled(dev_priv, plane);
2422
2423         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2424            for train result */
2425         reg = FDI_RX_IMR(pipe);
2426         temp = I915_READ(reg);
2427         temp &= ~FDI_RX_SYMBOL_LOCK;
2428         temp &= ~FDI_RX_BIT_LOCK;
2429         I915_WRITE(reg, temp);
2430         I915_READ(reg);
2431         udelay(150);
2432
2433         /* enable CPU FDI TX and PCH FDI RX */
2434         reg = FDI_TX_CTL(pipe);
2435         temp = I915_READ(reg);
2436         temp &= ~(7 << 19);
2437         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2438         temp &= ~FDI_LINK_TRAIN_NONE;
2439         temp |= FDI_LINK_TRAIN_PATTERN_1;
2440         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2441
2442         reg = FDI_RX_CTL(pipe);
2443         temp = I915_READ(reg);
2444         temp &= ~FDI_LINK_TRAIN_NONE;
2445         temp |= FDI_LINK_TRAIN_PATTERN_1;
2446         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2447
2448         POSTING_READ(reg);
2449         udelay(150);
2450
2451         /* Ironlake workaround, enable clock pointer after FDI enable*/
2452         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2453         I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR |
2454                    FDI_RX_PHASE_SYNC_POINTER_EN);
2455
2456         reg = FDI_RX_IIR(pipe);
2457         for (tries = 0; tries < 5; tries++) {
2458                 temp = I915_READ(reg);
2459                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2460
2461                 if ((temp & FDI_RX_BIT_LOCK)) {
2462                         DRM_DEBUG_KMS("FDI train 1 done.\n");
2463                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2464                         break;
2465                 }
2466         }
2467         if (tries == 5)
2468                 DRM_ERROR("FDI train 1 fail!\n");
2469
2470         /* Train 2 */
2471         reg = FDI_TX_CTL(pipe);
2472         temp = I915_READ(reg);
2473         temp &= ~FDI_LINK_TRAIN_NONE;
2474         temp |= FDI_LINK_TRAIN_PATTERN_2;
2475         I915_WRITE(reg, temp);
2476
2477         reg = FDI_RX_CTL(pipe);
2478         temp = I915_READ(reg);
2479         temp &= ~FDI_LINK_TRAIN_NONE;
2480         temp |= FDI_LINK_TRAIN_PATTERN_2;
2481         I915_WRITE(reg, temp);
2482
2483         POSTING_READ(reg);
2484         udelay(150);
2485
2486         reg = FDI_RX_IIR(pipe);
2487         for (tries = 0; tries < 5; tries++) {
2488                 temp = I915_READ(reg);
2489                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2490
2491                 if (temp & FDI_RX_SYMBOL_LOCK) {
2492                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2493                         DRM_DEBUG_KMS("FDI train 2 done.\n");
2494                         break;
2495                 }
2496         }
2497         if (tries == 5)
2498                 DRM_ERROR("FDI train 2 fail!\n");
2499
2500         DRM_DEBUG_KMS("FDI train done\n");
2501
2502 }
2503
2504 static const int snb_b_fdi_train_param[] = {
2505         FDI_LINK_TRAIN_400MV_0DB_SNB_B,
2506         FDI_LINK_TRAIN_400MV_6DB_SNB_B,
2507         FDI_LINK_TRAIN_600MV_3_5DB_SNB_B,
2508         FDI_LINK_TRAIN_800MV_0DB_SNB_B,
2509 };
2510
2511 /* The FDI link training functions for SNB/Cougarpoint. */
2512 static void gen6_fdi_link_train(struct drm_crtc *crtc)
2513 {
2514         struct drm_device *dev = crtc->dev;
2515         struct drm_i915_private *dev_priv = dev->dev_private;
2516         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2517         int pipe = intel_crtc->pipe;
2518         u32 reg, temp, i, retry;
2519
2520         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2521            for train result */
2522         reg = FDI_RX_IMR(pipe);
2523         temp = I915_READ(reg);
2524         temp &= ~FDI_RX_SYMBOL_LOCK;
2525         temp &= ~FDI_RX_BIT_LOCK;
2526         I915_WRITE(reg, temp);
2527
2528         POSTING_READ(reg);
2529         udelay(150);
2530
2531         /* enable CPU FDI TX and PCH FDI RX */
2532         reg = FDI_TX_CTL(pipe);
2533         temp = I915_READ(reg);
2534         temp &= ~(7 << 19);
2535         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2536         temp &= ~FDI_LINK_TRAIN_NONE;
2537         temp |= FDI_LINK_TRAIN_PATTERN_1;
2538         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2539         /* SNB-B */
2540         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2541         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2542
2543         I915_WRITE(FDI_RX_MISC(pipe),
2544                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2545
2546         reg = FDI_RX_CTL(pipe);
2547         temp = I915_READ(reg);
2548         if (HAS_PCH_CPT(dev)) {
2549                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2550                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2551         } else {
2552                 temp &= ~FDI_LINK_TRAIN_NONE;
2553                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2554         }
2555         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2556
2557         POSTING_READ(reg);
2558         udelay(150);
2559
2560         cpt_phase_pointer_enable(dev, pipe);
2561
2562         for (i = 0; i < 4; i++) {
2563                 reg = FDI_TX_CTL(pipe);
2564                 temp = I915_READ(reg);
2565                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2566                 temp |= snb_b_fdi_train_param[i];
2567                 I915_WRITE(reg, temp);
2568
2569                 POSTING_READ(reg);
2570                 udelay(500);
2571
2572                 for (retry = 0; retry < 5; retry++) {
2573                         reg = FDI_RX_IIR(pipe);
2574                         temp = I915_READ(reg);
2575                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2576                         if (temp & FDI_RX_BIT_LOCK) {
2577                                 I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2578                                 DRM_DEBUG_KMS("FDI train 1 done.\n");
2579                                 break;
2580                         }
2581                         udelay(50);
2582                 }
2583                 if (retry < 5)
2584                         break;
2585         }
2586         if (i == 4)
2587                 DRM_ERROR("FDI train 1 fail!\n");
2588
2589         /* Train 2 */
2590         reg = FDI_TX_CTL(pipe);
2591         temp = I915_READ(reg);
2592         temp &= ~FDI_LINK_TRAIN_NONE;
2593         temp |= FDI_LINK_TRAIN_PATTERN_2;
2594         if (IS_GEN6(dev)) {
2595                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2596                 /* SNB-B */
2597                 temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2598         }
2599         I915_WRITE(reg, temp);
2600
2601         reg = FDI_RX_CTL(pipe);
2602         temp = I915_READ(reg);
2603         if (HAS_PCH_CPT(dev)) {
2604                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2605                 temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2606         } else {
2607                 temp &= ~FDI_LINK_TRAIN_NONE;
2608                 temp |= FDI_LINK_TRAIN_PATTERN_2;
2609         }
2610         I915_WRITE(reg, temp);
2611
2612         POSTING_READ(reg);
2613         udelay(150);
2614
2615         for (i = 0; i < 4; i++) {
2616                 reg = FDI_TX_CTL(pipe);
2617                 temp = I915_READ(reg);
2618                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2619                 temp |= snb_b_fdi_train_param[i];
2620                 I915_WRITE(reg, temp);
2621
2622                 POSTING_READ(reg);
2623                 udelay(500);
2624
2625                 for (retry = 0; retry < 5; retry++) {
2626                         reg = FDI_RX_IIR(pipe);
2627                         temp = I915_READ(reg);
2628                         DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2629                         if (temp & FDI_RX_SYMBOL_LOCK) {
2630                                 I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2631                                 DRM_DEBUG_KMS("FDI train 2 done.\n");
2632                                 break;
2633                         }
2634                         udelay(50);
2635                 }
2636                 if (retry < 5)
2637                         break;
2638         }
2639         if (i == 4)
2640                 DRM_ERROR("FDI train 2 fail!\n");
2641
2642         DRM_DEBUG_KMS("FDI train done.\n");
2643 }
2644
2645 /* Manual link training for Ivy Bridge A0 parts */
2646 static void ivb_manual_fdi_link_train(struct drm_crtc *crtc)
2647 {
2648         struct drm_device *dev = crtc->dev;
2649         struct drm_i915_private *dev_priv = dev->dev_private;
2650         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2651         int pipe = intel_crtc->pipe;
2652         u32 reg, temp, i;
2653
2654         /* Train 1: umask FDI RX Interrupt symbol_lock and bit_lock bit
2655            for train result */
2656         reg = FDI_RX_IMR(pipe);
2657         temp = I915_READ(reg);
2658         temp &= ~FDI_RX_SYMBOL_LOCK;
2659         temp &= ~FDI_RX_BIT_LOCK;
2660         I915_WRITE(reg, temp);
2661
2662         POSTING_READ(reg);
2663         udelay(150);
2664
2665         DRM_DEBUG_KMS("FDI_RX_IIR before link train 0x%x\n",
2666                       I915_READ(FDI_RX_IIR(pipe)));
2667
2668         /* enable CPU FDI TX and PCH FDI RX */
2669         reg = FDI_TX_CTL(pipe);
2670         temp = I915_READ(reg);
2671         temp &= ~(7 << 19);
2672         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2673         temp &= ~(FDI_LINK_TRAIN_AUTO | FDI_LINK_TRAIN_NONE_IVB);
2674         temp |= FDI_LINK_TRAIN_PATTERN_1_IVB;
2675         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2676         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2677         temp |= FDI_COMPOSITE_SYNC;
2678         I915_WRITE(reg, temp | FDI_TX_ENABLE);
2679
2680         I915_WRITE(FDI_RX_MISC(pipe),
2681                    FDI_RX_TP1_TO_TP2_48 | FDI_RX_FDI_DELAY_90);
2682
2683         reg = FDI_RX_CTL(pipe);
2684         temp = I915_READ(reg);
2685         temp &= ~FDI_LINK_TRAIN_AUTO;
2686         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2687         temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2688         temp |= FDI_COMPOSITE_SYNC;
2689         I915_WRITE(reg, temp | FDI_RX_ENABLE);
2690
2691         POSTING_READ(reg);
2692         udelay(150);
2693
2694         cpt_phase_pointer_enable(dev, pipe);
2695
2696         for (i = 0; i < 4; i++) {
2697                 reg = FDI_TX_CTL(pipe);
2698                 temp = I915_READ(reg);
2699                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2700                 temp |= snb_b_fdi_train_param[i];
2701                 I915_WRITE(reg, temp);
2702
2703                 POSTING_READ(reg);
2704                 udelay(500);
2705
2706                 reg = FDI_RX_IIR(pipe);
2707                 temp = I915_READ(reg);
2708                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2709
2710                 if (temp & FDI_RX_BIT_LOCK ||
2711                     (I915_READ(reg) & FDI_RX_BIT_LOCK)) {
2712                         I915_WRITE(reg, temp | FDI_RX_BIT_LOCK);
2713                         DRM_DEBUG_KMS("FDI train 1 done, level %i.\n", i);
2714                         break;
2715                 }
2716         }
2717         if (i == 4)
2718                 DRM_ERROR("FDI train 1 fail!\n");
2719
2720         /* Train 2 */
2721         reg = FDI_TX_CTL(pipe);
2722         temp = I915_READ(reg);
2723         temp &= ~FDI_LINK_TRAIN_NONE_IVB;
2724         temp |= FDI_LINK_TRAIN_PATTERN_2_IVB;
2725         temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2726         temp |= FDI_LINK_TRAIN_400MV_0DB_SNB_B;
2727         I915_WRITE(reg, temp);
2728
2729         reg = FDI_RX_CTL(pipe);
2730         temp = I915_READ(reg);
2731         temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2732         temp |= FDI_LINK_TRAIN_PATTERN_2_CPT;
2733         I915_WRITE(reg, temp);
2734
2735         POSTING_READ(reg);
2736         udelay(150);
2737
2738         for (i = 0; i < 4; i++) {
2739                 reg = FDI_TX_CTL(pipe);
2740                 temp = I915_READ(reg);
2741                 temp &= ~FDI_LINK_TRAIN_VOL_EMP_MASK;
2742                 temp |= snb_b_fdi_train_param[i];
2743                 I915_WRITE(reg, temp);
2744
2745                 POSTING_READ(reg);
2746                 udelay(500);
2747
2748                 reg = FDI_RX_IIR(pipe);
2749                 temp = I915_READ(reg);
2750                 DRM_DEBUG_KMS("FDI_RX_IIR 0x%x\n", temp);
2751
2752                 if (temp & FDI_RX_SYMBOL_LOCK) {
2753                         I915_WRITE(reg, temp | FDI_RX_SYMBOL_LOCK);
2754                         DRM_DEBUG_KMS("FDI train 2 done, level %i.\n", i);
2755                         break;
2756                 }
2757         }
2758         if (i == 4)
2759                 DRM_ERROR("FDI train 2 fail!\n");
2760
2761         DRM_DEBUG_KMS("FDI train done.\n");
2762 }
2763
2764 static void ironlake_fdi_pll_enable(struct intel_crtc *intel_crtc)
2765 {
2766         struct drm_device *dev = intel_crtc->base.dev;
2767         struct drm_i915_private *dev_priv = dev->dev_private;
2768         int pipe = intel_crtc->pipe;
2769         u32 reg, temp;
2770
2771
2772         /* enable PCH FDI RX PLL, wait warmup plus DMI latency */
2773         reg = FDI_RX_CTL(pipe);
2774         temp = I915_READ(reg);
2775         temp &= ~((0x7 << 19) | (0x7 << 16));
2776         temp |= (intel_crtc->fdi_lanes - 1) << 19;
2777         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2778         I915_WRITE(reg, temp | FDI_RX_PLL_ENABLE);
2779
2780         POSTING_READ(reg);
2781         udelay(200);
2782
2783         /* Switch from Rawclk to PCDclk */
2784         temp = I915_READ(reg);
2785         I915_WRITE(reg, temp | FDI_PCDCLK);
2786
2787         POSTING_READ(reg);
2788         udelay(200);
2789
2790         /* On Haswell, the PLL configuration for ports and pipes is handled
2791          * separately, as part of DDI setup */
2792         if (!IS_HASWELL(dev)) {
2793                 /* Enable CPU FDI TX PLL, always on for Ironlake */
2794                 reg = FDI_TX_CTL(pipe);
2795                 temp = I915_READ(reg);
2796                 if ((temp & FDI_TX_PLL_ENABLE) == 0) {
2797                         I915_WRITE(reg, temp | FDI_TX_PLL_ENABLE);
2798
2799                         POSTING_READ(reg);
2800                         udelay(100);
2801                 }
2802         }
2803 }
2804
2805 static void ironlake_fdi_pll_disable(struct intel_crtc *intel_crtc)
2806 {
2807         struct drm_device *dev = intel_crtc->base.dev;
2808         struct drm_i915_private *dev_priv = dev->dev_private;
2809         int pipe = intel_crtc->pipe;
2810         u32 reg, temp;
2811
2812         /* Switch from PCDclk to Rawclk */
2813         reg = FDI_RX_CTL(pipe);
2814         temp = I915_READ(reg);
2815         I915_WRITE(reg, temp & ~FDI_PCDCLK);
2816
2817         /* Disable CPU FDI TX PLL */
2818         reg = FDI_TX_CTL(pipe);
2819         temp = I915_READ(reg);
2820         I915_WRITE(reg, temp & ~FDI_TX_PLL_ENABLE);
2821
2822         POSTING_READ(reg);
2823         udelay(100);
2824
2825         reg = FDI_RX_CTL(pipe);
2826         temp = I915_READ(reg);
2827         I915_WRITE(reg, temp & ~FDI_RX_PLL_ENABLE);
2828
2829         /* Wait for the clocks to turn off. */
2830         POSTING_READ(reg);
2831         udelay(100);
2832 }
2833
2834 static void cpt_phase_pointer_disable(struct drm_device *dev, int pipe)
2835 {
2836         struct drm_i915_private *dev_priv = dev->dev_private;
2837         u32 flags = I915_READ(SOUTH_CHICKEN1);
2838
2839         flags &= ~(FDI_PHASE_SYNC_EN(pipe));
2840         I915_WRITE(SOUTH_CHICKEN1, flags); /* once to disable... */
2841         flags &= ~(FDI_PHASE_SYNC_OVR(pipe));
2842         I915_WRITE(SOUTH_CHICKEN1, flags); /* then again to lock */
2843         POSTING_READ(SOUTH_CHICKEN1);
2844 }
2845 static void ironlake_fdi_disable(struct drm_crtc *crtc)
2846 {
2847         struct drm_device *dev = crtc->dev;
2848         struct drm_i915_private *dev_priv = dev->dev_private;
2849         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2850         int pipe = intel_crtc->pipe;
2851         u32 reg, temp;
2852
2853         /* disable CPU FDI tx and PCH FDI rx */
2854         reg = FDI_TX_CTL(pipe);
2855         temp = I915_READ(reg);
2856         I915_WRITE(reg, temp & ~FDI_TX_ENABLE);
2857         POSTING_READ(reg);
2858
2859         reg = FDI_RX_CTL(pipe);
2860         temp = I915_READ(reg);
2861         temp &= ~(0x7 << 16);
2862         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2863         I915_WRITE(reg, temp & ~FDI_RX_ENABLE);
2864
2865         POSTING_READ(reg);
2866         udelay(100);
2867
2868         /* Ironlake workaround, disable clock pointer after downing FDI */
2869         if (HAS_PCH_IBX(dev)) {
2870                 I915_WRITE(FDI_RX_CHICKEN(pipe), FDI_RX_PHASE_SYNC_POINTER_OVR);
2871         } else if (HAS_PCH_CPT(dev)) {
2872                 cpt_phase_pointer_disable(dev, pipe);
2873         }
2874
2875         /* still set train pattern 1 */
2876         reg = FDI_TX_CTL(pipe);
2877         temp = I915_READ(reg);
2878         temp &= ~FDI_LINK_TRAIN_NONE;
2879         temp |= FDI_LINK_TRAIN_PATTERN_1;
2880         I915_WRITE(reg, temp);
2881
2882         reg = FDI_RX_CTL(pipe);
2883         temp = I915_READ(reg);
2884         if (HAS_PCH_CPT(dev)) {
2885                 temp &= ~FDI_LINK_TRAIN_PATTERN_MASK_CPT;
2886                 temp |= FDI_LINK_TRAIN_PATTERN_1_CPT;
2887         } else {
2888                 temp &= ~FDI_LINK_TRAIN_NONE;
2889                 temp |= FDI_LINK_TRAIN_PATTERN_1;
2890         }
2891         /* BPC in FDI rx is consistent with that in PIPECONF */
2892         temp &= ~(0x07 << 16);
2893         temp |= (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) << 11;
2894         I915_WRITE(reg, temp);
2895
2896         POSTING_READ(reg);
2897         udelay(100);
2898 }
2899
2900 static bool intel_crtc_has_pending_flip(struct drm_crtc *crtc)
2901 {
2902         struct drm_device *dev = crtc->dev;
2903         struct drm_i915_private *dev_priv = dev->dev_private;
2904         unsigned long flags;
2905         bool pending;
2906
2907         if (atomic_read(&dev_priv->mm.wedged))
2908                 return false;
2909
2910         spin_lock_irqsave(&dev->event_lock, flags);
2911         pending = to_intel_crtc(crtc)->unpin_work != NULL;
2912         spin_unlock_irqrestore(&dev->event_lock, flags);
2913
2914         return pending;
2915 }
2916
2917 static void intel_crtc_wait_for_pending_flips(struct drm_crtc *crtc)
2918 {
2919         struct drm_device *dev = crtc->dev;
2920         struct drm_i915_private *dev_priv = dev->dev_private;
2921
2922         if (crtc->fb == NULL)
2923                 return;
2924
2925         wait_event(dev_priv->pending_flip_queue,
2926                    !intel_crtc_has_pending_flip(crtc));
2927
2928         mutex_lock(&dev->struct_mutex);
2929         intel_finish_fb(crtc->fb);
2930         mutex_unlock(&dev->struct_mutex);
2931 }
2932
2933 static bool ironlake_crtc_driving_pch(struct drm_crtc *crtc)
2934 {
2935         struct drm_device *dev = crtc->dev;
2936         struct intel_encoder *intel_encoder;
2937
2938         /*
2939          * If there's a non-PCH eDP on this crtc, it must be DP_A, and that
2940          * must be driven by its own crtc; no sharing is possible.
2941          */
2942         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
2943                 switch (intel_encoder->type) {
2944                 case INTEL_OUTPUT_EDP:
2945                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
2946                                 return false;
2947                         continue;
2948                 }
2949         }
2950
2951         return true;
2952 }
2953
2954 static bool haswell_crtc_driving_pch(struct drm_crtc *crtc)
2955 {
2956         return intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG);
2957 }
2958
2959 /* Program iCLKIP clock to the desired frequency */
2960 static void lpt_program_iclkip(struct drm_crtc *crtc)
2961 {
2962         struct drm_device *dev = crtc->dev;
2963         struct drm_i915_private *dev_priv = dev->dev_private;
2964         u32 divsel, phaseinc, auxdiv, phasedir = 0;
2965         u32 temp;
2966
2967         /* It is necessary to ungate the pixclk gate prior to programming
2968          * the divisors, and gate it back when it is done.
2969          */
2970         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_GATE);
2971
2972         /* Disable SSCCTL */
2973         intel_sbi_write(dev_priv, SBI_SSCCTL6,
2974                                 intel_sbi_read(dev_priv, SBI_SSCCTL6) |
2975                                         SBI_SSCCTL_DISABLE);
2976
2977         /* 20MHz is a corner case which is out of range for the 7-bit divisor */
2978         if (crtc->mode.clock == 20000) {
2979                 auxdiv = 1;
2980                 divsel = 0x41;
2981                 phaseinc = 0x20;
2982         } else {
2983                 /* The iCLK virtual clock root frequency is in MHz,
2984                  * but the crtc->mode.clock in in KHz. To get the divisors,
2985                  * it is necessary to divide one by another, so we
2986                  * convert the virtual clock precision to KHz here for higher
2987                  * precision.
2988                  */
2989                 u32 iclk_virtual_root_freq = 172800 * 1000;
2990                 u32 iclk_pi_range = 64;
2991                 u32 desired_divisor, msb_divisor_value, pi_value;
2992
2993                 desired_divisor = (iclk_virtual_root_freq / crtc->mode.clock);
2994                 msb_divisor_value = desired_divisor / iclk_pi_range;
2995                 pi_value = desired_divisor % iclk_pi_range;
2996
2997                 auxdiv = 0;
2998                 divsel = msb_divisor_value - 2;
2999                 phaseinc = pi_value;
3000         }
3001
3002         /* This should not happen with any sane values */
3003         WARN_ON(SBI_SSCDIVINTPHASE_DIVSEL(divsel) &
3004                 ~SBI_SSCDIVINTPHASE_DIVSEL_MASK);
3005         WARN_ON(SBI_SSCDIVINTPHASE_DIR(phasedir) &
3006                 ~SBI_SSCDIVINTPHASE_INCVAL_MASK);
3007
3008         DRM_DEBUG_KMS("iCLKIP clock: found settings for %dKHz refresh rate: auxdiv=%x, divsel=%x, phasedir=%x, phaseinc=%x\n",
3009                         crtc->mode.clock,
3010                         auxdiv,
3011                         divsel,
3012                         phasedir,
3013                         phaseinc);
3014
3015         /* Program SSCDIVINTPHASE6 */
3016         temp = intel_sbi_read(dev_priv, SBI_SSCDIVINTPHASE6);
3017         temp &= ~SBI_SSCDIVINTPHASE_DIVSEL_MASK;
3018         temp |= SBI_SSCDIVINTPHASE_DIVSEL(divsel);
3019         temp &= ~SBI_SSCDIVINTPHASE_INCVAL_MASK;
3020         temp |= SBI_SSCDIVINTPHASE_INCVAL(phaseinc);
3021         temp |= SBI_SSCDIVINTPHASE_DIR(phasedir);
3022         temp |= SBI_SSCDIVINTPHASE_PROPAGATE;
3023
3024         intel_sbi_write(dev_priv,
3025                         SBI_SSCDIVINTPHASE6,
3026                         temp);
3027
3028         /* Program SSCAUXDIV */
3029         temp = intel_sbi_read(dev_priv, SBI_SSCAUXDIV6);
3030         temp &= ~SBI_SSCAUXDIV_FINALDIV2SEL(1);
3031         temp |= SBI_SSCAUXDIV_FINALDIV2SEL(auxdiv);
3032         intel_sbi_write(dev_priv,
3033                         SBI_SSCAUXDIV6,
3034                         temp);
3035
3036
3037         /* Enable modulator and associated divider */
3038         temp = intel_sbi_read(dev_priv, SBI_SSCCTL6);
3039         temp &= ~SBI_SSCCTL_DISABLE;
3040         intel_sbi_write(dev_priv,
3041                         SBI_SSCCTL6,
3042                         temp);
3043
3044         /* Wait for initialization time */
3045         udelay(24);
3046
3047         I915_WRITE(PIXCLK_GATE, PIXCLK_GATE_UNGATE);
3048 }
3049
3050 /*
3051  * Enable PCH resources required for PCH ports:
3052  *   - PCH PLLs
3053  *   - FDI training & RX/TX
3054  *   - update transcoder timings
3055  *   - DP transcoding bits
3056  *   - transcoder
3057  */
3058 static void ironlake_pch_enable(struct drm_crtc *crtc)
3059 {
3060         struct drm_device *dev = crtc->dev;
3061         struct drm_i915_private *dev_priv = dev->dev_private;
3062         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3063         int pipe = intel_crtc->pipe;
3064         u32 reg, temp;
3065
3066         assert_transcoder_disabled(dev_priv, pipe);
3067
3068         /* Write the TU size bits before fdi link training, so that error
3069          * detection works. */
3070         I915_WRITE(FDI_RX_TUSIZE1(pipe),
3071                    I915_READ(PIPE_DATA_M1(pipe)) & TU_SIZE_MASK);
3072
3073         /* For PCH output, training FDI link */
3074         dev_priv->display.fdi_link_train(crtc);
3075
3076         /* XXX: pch pll's can be enabled any time before we enable the PCH
3077          * transcoder, and we actually should do this to not upset any PCH
3078          * transcoder that already use the clock when we share it.
3079          *
3080          * Note that enable_pch_pll tries to do the right thing, but get_pch_pll
3081          * unconditionally resets the pll - we need that to have the right LVDS
3082          * enable sequence. */
3083         ironlake_enable_pch_pll(intel_crtc);
3084
3085         if (HAS_PCH_CPT(dev)) {
3086                 u32 sel;
3087
3088                 temp = I915_READ(PCH_DPLL_SEL);
3089                 switch (pipe) {
3090                 default:
3091                 case 0:
3092                         temp |= TRANSA_DPLL_ENABLE;
3093                         sel = TRANSA_DPLLB_SEL;
3094                         break;
3095                 case 1:
3096                         temp |= TRANSB_DPLL_ENABLE;
3097                         sel = TRANSB_DPLLB_SEL;
3098                         break;
3099                 case 2:
3100                         temp |= TRANSC_DPLL_ENABLE;
3101                         sel = TRANSC_DPLLB_SEL;
3102                         break;
3103                 }
3104                 if (intel_crtc->pch_pll->pll_reg == _PCH_DPLL_B)
3105                         temp |= sel;
3106                 else
3107                         temp &= ~sel;
3108                 I915_WRITE(PCH_DPLL_SEL, temp);
3109         }
3110
3111         /* set transcoder timing, panel must allow it */
3112         assert_panel_unlocked(dev_priv, pipe);
3113         I915_WRITE(TRANS_HTOTAL(pipe), I915_READ(HTOTAL(pipe)));
3114         I915_WRITE(TRANS_HBLANK(pipe), I915_READ(HBLANK(pipe)));
3115         I915_WRITE(TRANS_HSYNC(pipe),  I915_READ(HSYNC(pipe)));
3116
3117         I915_WRITE(TRANS_VTOTAL(pipe), I915_READ(VTOTAL(pipe)));
3118         I915_WRITE(TRANS_VBLANK(pipe), I915_READ(VBLANK(pipe)));
3119         I915_WRITE(TRANS_VSYNC(pipe),  I915_READ(VSYNC(pipe)));
3120         I915_WRITE(TRANS_VSYNCSHIFT(pipe),  I915_READ(VSYNCSHIFT(pipe)));
3121
3122         intel_fdi_normal_train(crtc);
3123
3124         /* For PCH DP, enable TRANS_DP_CTL */
3125         if (HAS_PCH_CPT(dev) &&
3126             (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT) ||
3127              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3128                 u32 bpc = (I915_READ(PIPECONF(pipe)) & PIPE_BPC_MASK) >> 5;
3129                 reg = TRANS_DP_CTL(pipe);
3130                 temp = I915_READ(reg);
3131                 temp &= ~(TRANS_DP_PORT_SEL_MASK |
3132                           TRANS_DP_SYNC_MASK |
3133                           TRANS_DP_BPC_MASK);
3134                 temp |= (TRANS_DP_OUTPUT_ENABLE |
3135                          TRANS_DP_ENH_FRAMING);
3136                 temp |= bpc << 9; /* same format but at 11:9 */
3137
3138                 if (crtc->mode.flags & DRM_MODE_FLAG_PHSYNC)
3139                         temp |= TRANS_DP_HSYNC_ACTIVE_HIGH;
3140                 if (crtc->mode.flags & DRM_MODE_FLAG_PVSYNC)
3141                         temp |= TRANS_DP_VSYNC_ACTIVE_HIGH;
3142
3143                 switch (intel_trans_dp_port_sel(crtc)) {
3144                 case PCH_DP_B:
3145                         temp |= TRANS_DP_PORT_SEL_B;
3146                         break;
3147                 case PCH_DP_C:
3148                         temp |= TRANS_DP_PORT_SEL_C;
3149                         break;
3150                 case PCH_DP_D:
3151                         temp |= TRANS_DP_PORT_SEL_D;
3152                         break;
3153                 default:
3154                         BUG();
3155                 }
3156
3157                 I915_WRITE(reg, temp);
3158         }
3159
3160         ironlake_enable_pch_transcoder(dev_priv, pipe);
3161 }
3162
3163 static void lpt_pch_enable(struct drm_crtc *crtc)
3164 {
3165         struct drm_device *dev = crtc->dev;
3166         struct drm_i915_private *dev_priv = dev->dev_private;
3167         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3168         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3169
3170         assert_transcoder_disabled(dev_priv, TRANSCODER_A);
3171
3172         lpt_program_iclkip(crtc);
3173
3174         /* Set transcoder timing. */
3175         I915_WRITE(_TRANS_HTOTAL_A, I915_READ(HTOTAL(cpu_transcoder)));
3176         I915_WRITE(_TRANS_HBLANK_A, I915_READ(HBLANK(cpu_transcoder)));
3177         I915_WRITE(_TRANS_HSYNC_A,  I915_READ(HSYNC(cpu_transcoder)));
3178
3179         I915_WRITE(_TRANS_VTOTAL_A, I915_READ(VTOTAL(cpu_transcoder)));
3180         I915_WRITE(_TRANS_VBLANK_A, I915_READ(VBLANK(cpu_transcoder)));
3181         I915_WRITE(_TRANS_VSYNC_A,  I915_READ(VSYNC(cpu_transcoder)));
3182         I915_WRITE(_TRANS_VSYNCSHIFT_A, I915_READ(VSYNCSHIFT(cpu_transcoder)));
3183
3184         lpt_enable_pch_transcoder(dev_priv, cpu_transcoder);
3185 }
3186
3187 static void intel_put_pch_pll(struct intel_crtc *intel_crtc)
3188 {
3189         struct intel_pch_pll *pll = intel_crtc->pch_pll;
3190
3191         if (pll == NULL)
3192                 return;
3193
3194         if (pll->refcount == 0) {
3195                 WARN(1, "bad PCH PLL refcount\n");
3196                 return;
3197         }
3198
3199         --pll->refcount;
3200         intel_crtc->pch_pll = NULL;
3201 }
3202
3203 static struct intel_pch_pll *intel_get_pch_pll(struct intel_crtc *intel_crtc, u32 dpll, u32 fp)
3204 {
3205         struct drm_i915_private *dev_priv = intel_crtc->base.dev->dev_private;
3206         struct intel_pch_pll *pll;
3207         int i;
3208
3209         pll = intel_crtc->pch_pll;
3210         if (pll) {
3211                 DRM_DEBUG_KMS("CRTC:%d reusing existing PCH PLL %x\n",
3212                               intel_crtc->base.base.id, pll->pll_reg);
3213                 goto prepare;
3214         }
3215
3216         if (HAS_PCH_IBX(dev_priv->dev)) {
3217                 /* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
3218                 i = intel_crtc->pipe;
3219                 pll = &dev_priv->pch_plls[i];
3220
3221                 DRM_DEBUG_KMS("CRTC:%d using pre-allocated PCH PLL %x\n",
3222                               intel_crtc->base.base.id, pll->pll_reg);
3223
3224                 goto found;
3225         }
3226
3227         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3228                 pll = &dev_priv->pch_plls[i];
3229
3230                 /* Only want to check enabled timings first */
3231                 if (pll->refcount == 0)
3232                         continue;
3233
3234                 if (dpll == (I915_READ(pll->pll_reg) & 0x7fffffff) &&
3235                     fp == I915_READ(pll->fp0_reg)) {
3236                         DRM_DEBUG_KMS("CRTC:%d sharing existing PCH PLL %x (refcount %d, ative %d)\n",
3237                                       intel_crtc->base.base.id,
3238                                       pll->pll_reg, pll->refcount, pll->active);
3239
3240                         goto found;
3241                 }
3242         }
3243
3244         /* Ok no matching timings, maybe there's a free one? */
3245         for (i = 0; i < dev_priv->num_pch_pll; i++) {
3246                 pll = &dev_priv->pch_plls[i];
3247                 if (pll->refcount == 0) {
3248                         DRM_DEBUG_KMS("CRTC:%d allocated PCH PLL %x\n",
3249                                       intel_crtc->base.base.id, pll->pll_reg);
3250                         goto found;
3251                 }
3252         }
3253
3254         return NULL;
3255
3256 found:
3257         intel_crtc->pch_pll = pll;
3258         pll->refcount++;
3259         DRM_DEBUG_DRIVER("using pll %d for pipe %d\n", i, intel_crtc->pipe);
3260 prepare: /* separate function? */
3261         DRM_DEBUG_DRIVER("switching PLL %x off\n", pll->pll_reg);
3262
3263         /* Wait for the clocks to stabilize before rewriting the regs */
3264         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3265         POSTING_READ(pll->pll_reg);
3266         udelay(150);
3267
3268         I915_WRITE(pll->fp0_reg, fp);
3269         I915_WRITE(pll->pll_reg, dpll & ~DPLL_VCO_ENABLE);
3270         pll->on = false;
3271         return pll;
3272 }
3273
3274 void intel_cpt_verify_modeset(struct drm_device *dev, int pipe)
3275 {
3276         struct drm_i915_private *dev_priv = dev->dev_private;
3277         int dslreg = PIPEDSL(pipe);
3278         u32 temp;
3279
3280         temp = I915_READ(dslreg);
3281         udelay(500);
3282         if (wait_for(I915_READ(dslreg) != temp, 5)) {
3283                 if (wait_for(I915_READ(dslreg) != temp, 5))
3284                         DRM_ERROR("mode set failed: pipe %d stuck\n", pipe);
3285         }
3286 }
3287
3288 static void ironlake_crtc_enable(struct drm_crtc *crtc)
3289 {
3290         struct drm_device *dev = crtc->dev;
3291         struct drm_i915_private *dev_priv = dev->dev_private;
3292         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3293         struct intel_encoder *encoder;
3294         int pipe = intel_crtc->pipe;
3295         int plane = intel_crtc->plane;
3296         u32 temp;
3297         bool is_pch_port;
3298
3299         WARN_ON(!crtc->enabled);
3300
3301         if (intel_crtc->active)
3302                 return;
3303
3304         intel_crtc->active = true;
3305         intel_update_watermarks(dev);
3306
3307         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
3308                 temp = I915_READ(PCH_LVDS);
3309                 if ((temp & LVDS_PORT_EN) == 0)
3310                         I915_WRITE(PCH_LVDS, temp | LVDS_PORT_EN);
3311         }
3312
3313         is_pch_port = ironlake_crtc_driving_pch(crtc);
3314
3315         if (is_pch_port) {
3316                 /* Note: FDI PLL enabling _must_ be done before we enable the
3317                  * cpu pipes, hence this is separate from all the other fdi/pch
3318                  * enabling. */
3319                 ironlake_fdi_pll_enable(intel_crtc);
3320         } else {
3321                 assert_fdi_tx_disabled(dev_priv, pipe);
3322                 assert_fdi_rx_disabled(dev_priv, pipe);
3323         }
3324
3325         for_each_encoder_on_crtc(dev, crtc, encoder)
3326                 if (encoder->pre_enable)
3327                         encoder->pre_enable(encoder);
3328
3329         /* Enable panel fitting for LVDS */
3330         if (dev_priv->pch_pf_size &&
3331             (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) ||
3332              intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP))) {
3333                 /* Force use of hard-coded filter coefficients
3334                  * as some pre-programmed values are broken,
3335                  * e.g. x201.
3336                  */
3337                 if (IS_IVYBRIDGE(dev))
3338                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3339                                                  PF_PIPE_SEL_IVB(pipe));
3340                 else
3341                         I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3);
3342                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3343                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3344         }
3345
3346         /*
3347          * On ILK+ LUT must be loaded before the pipe is running but with
3348          * clocks enabled
3349          */
3350         intel_crtc_load_lut(crtc);
3351
3352         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3353         intel_enable_plane(dev_priv, plane, pipe);
3354
3355         if (is_pch_port)
3356                 ironlake_pch_enable(crtc);
3357
3358         mutex_lock(&dev->struct_mutex);
3359         intel_update_fbc(dev);
3360         mutex_unlock(&dev->struct_mutex);
3361
3362         intel_crtc_update_cursor(crtc, true);
3363
3364         for_each_encoder_on_crtc(dev, crtc, encoder)
3365                 encoder->enable(encoder);
3366
3367         if (HAS_PCH_CPT(dev))
3368                 intel_cpt_verify_modeset(dev, intel_crtc->pipe);
3369
3370         /*
3371          * There seems to be a race in PCH platform hw (at least on some
3372          * outputs) where an enabled pipe still completes any pageflip right
3373          * away (as if the pipe is off) instead of waiting for vblank. As soon
3374          * as the first vblank happend, everything works as expected. Hence just
3375          * wait for one vblank before returning to avoid strange things
3376          * happening.
3377          */
3378         intel_wait_for_vblank(dev, intel_crtc->pipe);
3379 }
3380
3381 static void haswell_crtc_enable(struct drm_crtc *crtc)
3382 {
3383         struct drm_device *dev = crtc->dev;
3384         struct drm_i915_private *dev_priv = dev->dev_private;
3385         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3386         struct intel_encoder *encoder;
3387         int pipe = intel_crtc->pipe;
3388         int plane = intel_crtc->plane;
3389         bool is_pch_port;
3390
3391         WARN_ON(!crtc->enabled);
3392
3393         if (intel_crtc->active)
3394                 return;
3395
3396         intel_crtc->active = true;
3397         intel_update_watermarks(dev);
3398
3399         is_pch_port = haswell_crtc_driving_pch(crtc);
3400
3401         if (is_pch_port)
3402                 dev_priv->display.fdi_link_train(crtc);
3403
3404         for_each_encoder_on_crtc(dev, crtc, encoder)
3405                 if (encoder->pre_enable)
3406                         encoder->pre_enable(encoder);
3407
3408         intel_ddi_enable_pipe_clock(intel_crtc);
3409
3410         /* Enable panel fitting for eDP */
3411         if (dev_priv->pch_pf_size &&
3412             intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
3413                 /* Force use of hard-coded filter coefficients
3414                  * as some pre-programmed values are broken,
3415                  * e.g. x201.
3416                  */
3417                 I915_WRITE(PF_CTL(pipe), PF_ENABLE | PF_FILTER_MED_3x3 |
3418                                          PF_PIPE_SEL_IVB(pipe));
3419                 I915_WRITE(PF_WIN_POS(pipe), dev_priv->pch_pf_pos);
3420                 I915_WRITE(PF_WIN_SZ(pipe), dev_priv->pch_pf_size);
3421         }
3422
3423         /*
3424          * On ILK+ LUT must be loaded before the pipe is running but with
3425          * clocks enabled
3426          */
3427         intel_crtc_load_lut(crtc);
3428
3429         intel_ddi_set_pipe_settings(crtc);
3430         intel_ddi_enable_pipe_func(crtc);
3431
3432         intel_enable_pipe(dev_priv, pipe, is_pch_port);
3433         intel_enable_plane(dev_priv, plane, pipe);
3434
3435         if (is_pch_port)
3436                 lpt_pch_enable(crtc);
3437
3438         mutex_lock(&dev->struct_mutex);
3439         intel_update_fbc(dev);
3440         mutex_unlock(&dev->struct_mutex);
3441
3442         intel_crtc_update_cursor(crtc, true);
3443
3444         for_each_encoder_on_crtc(dev, crtc, encoder)
3445                 encoder->enable(encoder);
3446
3447         /*
3448          * There seems to be a race in PCH platform hw (at least on some
3449          * outputs) where an enabled pipe still completes any pageflip right
3450          * away (as if the pipe is off) instead of waiting for vblank. As soon
3451          * as the first vblank happend, everything works as expected. Hence just
3452          * wait for one vblank before returning to avoid strange things
3453          * happening.
3454          */
3455         intel_wait_for_vblank(dev, intel_crtc->pipe);
3456 }
3457
3458 static void ironlake_crtc_disable(struct drm_crtc *crtc)
3459 {
3460         struct drm_device *dev = crtc->dev;
3461         struct drm_i915_private *dev_priv = dev->dev_private;
3462         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3463         struct intel_encoder *encoder;
3464         int pipe = intel_crtc->pipe;
3465         int plane = intel_crtc->plane;
3466         u32 reg, temp;
3467
3468
3469         if (!intel_crtc->active)
3470                 return;
3471
3472         for_each_encoder_on_crtc(dev, crtc, encoder)
3473                 encoder->disable(encoder);
3474
3475         intel_crtc_wait_for_pending_flips(crtc);
3476         drm_vblank_off(dev, pipe);
3477         intel_crtc_update_cursor(crtc, false);
3478
3479         intel_disable_plane(dev_priv, plane, pipe);
3480
3481         if (dev_priv->cfb_plane == plane)
3482                 intel_disable_fbc(dev);
3483
3484         intel_disable_pipe(dev_priv, pipe);
3485
3486         /* Disable PF */
3487         I915_WRITE(PF_CTL(pipe), 0);
3488         I915_WRITE(PF_WIN_SZ(pipe), 0);
3489
3490         for_each_encoder_on_crtc(dev, crtc, encoder)
3491                 if (encoder->post_disable)
3492                         encoder->post_disable(encoder);
3493
3494         ironlake_fdi_disable(crtc);
3495
3496         ironlake_disable_pch_transcoder(dev_priv, pipe);
3497
3498         if (HAS_PCH_CPT(dev)) {
3499                 /* disable TRANS_DP_CTL */
3500                 reg = TRANS_DP_CTL(pipe);
3501                 temp = I915_READ(reg);
3502                 temp &= ~(TRANS_DP_OUTPUT_ENABLE | TRANS_DP_PORT_SEL_MASK);
3503                 temp |= TRANS_DP_PORT_SEL_NONE;
3504                 I915_WRITE(reg, temp);
3505
3506                 /* disable DPLL_SEL */
3507                 temp = I915_READ(PCH_DPLL_SEL);
3508                 switch (pipe) {
3509                 case 0:
3510                         temp &= ~(TRANSA_DPLL_ENABLE | TRANSA_DPLLB_SEL);
3511                         break;
3512                 case 1:
3513                         temp &= ~(TRANSB_DPLL_ENABLE | TRANSB_DPLLB_SEL);
3514                         break;
3515                 case 2:
3516                         /* C shares PLL A or B */
3517                         temp &= ~(TRANSC_DPLL_ENABLE | TRANSC_DPLLB_SEL);
3518                         break;
3519                 default:
3520                         BUG(); /* wtf */
3521                 }
3522                 I915_WRITE(PCH_DPLL_SEL, temp);
3523         }
3524
3525         /* disable PCH DPLL */
3526         intel_disable_pch_pll(intel_crtc);
3527
3528         ironlake_fdi_pll_disable(intel_crtc);
3529
3530         intel_crtc->active = false;
3531         intel_update_watermarks(dev);
3532
3533         mutex_lock(&dev->struct_mutex);
3534         intel_update_fbc(dev);
3535         mutex_unlock(&dev->struct_mutex);
3536 }
3537
3538 static void haswell_crtc_disable(struct drm_crtc *crtc)
3539 {
3540         struct drm_device *dev = crtc->dev;
3541         struct drm_i915_private *dev_priv = dev->dev_private;
3542         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3543         struct intel_encoder *encoder;
3544         int pipe = intel_crtc->pipe;
3545         int plane = intel_crtc->plane;
3546         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
3547         bool is_pch_port;
3548
3549         if (!intel_crtc->active)
3550                 return;
3551
3552         is_pch_port = haswell_crtc_driving_pch(crtc);
3553
3554         for_each_encoder_on_crtc(dev, crtc, encoder)
3555                 encoder->disable(encoder);
3556
3557         intel_crtc_wait_for_pending_flips(crtc);
3558         drm_vblank_off(dev, pipe);
3559         intel_crtc_update_cursor(crtc, false);
3560
3561         intel_disable_plane(dev_priv, plane, pipe);
3562
3563         if (dev_priv->cfb_plane == plane)
3564                 intel_disable_fbc(dev);
3565
3566         intel_disable_pipe(dev_priv, pipe);
3567
3568         intel_ddi_disable_transcoder_func(dev_priv, cpu_transcoder);
3569
3570         /* Disable PF */
3571         I915_WRITE(PF_CTL(pipe), 0);
3572         I915_WRITE(PF_WIN_SZ(pipe), 0);
3573
3574         intel_ddi_disable_pipe_clock(intel_crtc);
3575
3576         for_each_encoder_on_crtc(dev, crtc, encoder)
3577                 if (encoder->post_disable)
3578                         encoder->post_disable(encoder);
3579
3580         if (is_pch_port) {
3581                 lpt_disable_pch_transcoder(dev_priv);
3582                 intel_ddi_fdi_disable(crtc);
3583         }
3584
3585         intel_crtc->active = false;
3586         intel_update_watermarks(dev);
3587
3588         mutex_lock(&dev->struct_mutex);
3589         intel_update_fbc(dev);
3590         mutex_unlock(&dev->struct_mutex);
3591 }
3592
3593 static void ironlake_crtc_off(struct drm_crtc *crtc)
3594 {
3595         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3596         intel_put_pch_pll(intel_crtc);
3597 }
3598
3599 static void haswell_crtc_off(struct drm_crtc *crtc)
3600 {
3601         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3602
3603         /* Stop saying we're using TRANSCODER_EDP because some other CRTC might
3604          * start using it. */
3605         intel_crtc->cpu_transcoder = intel_crtc->pipe;
3606
3607         intel_ddi_put_crtc_pll(crtc);
3608 }
3609
3610 static void intel_crtc_dpms_overlay(struct intel_crtc *intel_crtc, bool enable)
3611 {
3612         if (!enable && intel_crtc->overlay) {
3613                 struct drm_device *dev = intel_crtc->base.dev;
3614                 struct drm_i915_private *dev_priv = dev->dev_private;
3615
3616                 mutex_lock(&dev->struct_mutex);
3617                 dev_priv->mm.interruptible = false;
3618                 (void) intel_overlay_switch_off(intel_crtc->overlay);
3619                 dev_priv->mm.interruptible = true;
3620                 mutex_unlock(&dev->struct_mutex);
3621         }
3622
3623         /* Let userspace switch the overlay on again. In most cases userspace
3624          * has to recompute where to put it anyway.
3625          */
3626 }
3627
3628 static void i9xx_crtc_enable(struct drm_crtc *crtc)
3629 {
3630         struct drm_device *dev = crtc->dev;
3631         struct drm_i915_private *dev_priv = dev->dev_private;
3632         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3633         struct intel_encoder *encoder;
3634         int pipe = intel_crtc->pipe;
3635         int plane = intel_crtc->plane;
3636
3637         WARN_ON(!crtc->enabled);
3638
3639         if (intel_crtc->active)
3640                 return;
3641
3642         intel_crtc->active = true;
3643         intel_update_watermarks(dev);
3644
3645         intel_enable_pll(dev_priv, pipe);
3646         intel_enable_pipe(dev_priv, pipe, false);
3647         intel_enable_plane(dev_priv, plane, pipe);
3648
3649         intel_crtc_load_lut(crtc);
3650         intel_update_fbc(dev);
3651
3652         /* Give the overlay scaler a chance to enable if it's on this pipe */
3653         intel_crtc_dpms_overlay(intel_crtc, true);
3654         intel_crtc_update_cursor(crtc, true);
3655
3656         for_each_encoder_on_crtc(dev, crtc, encoder)
3657                 encoder->enable(encoder);
3658 }
3659
3660 static void i9xx_crtc_disable(struct drm_crtc *crtc)
3661 {
3662         struct drm_device *dev = crtc->dev;
3663         struct drm_i915_private *dev_priv = dev->dev_private;
3664         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3665         struct intel_encoder *encoder;
3666         int pipe = intel_crtc->pipe;
3667         int plane = intel_crtc->plane;
3668
3669
3670         if (!intel_crtc->active)
3671                 return;
3672
3673         for_each_encoder_on_crtc(dev, crtc, encoder)
3674                 encoder->disable(encoder);
3675
3676         /* Give the overlay scaler a chance to disable if it's on this pipe */
3677         intel_crtc_wait_for_pending_flips(crtc);
3678         drm_vblank_off(dev, pipe);
3679         intel_crtc_dpms_overlay(intel_crtc, false);
3680         intel_crtc_update_cursor(crtc, false);
3681
3682         if (dev_priv->cfb_plane == plane)
3683                 intel_disable_fbc(dev);
3684
3685         intel_disable_plane(dev_priv, plane, pipe);
3686         intel_disable_pipe(dev_priv, pipe);
3687         intel_disable_pll(dev_priv, pipe);
3688
3689         intel_crtc->active = false;
3690         intel_update_fbc(dev);
3691         intel_update_watermarks(dev);
3692 }
3693
3694 static void i9xx_crtc_off(struct drm_crtc *crtc)
3695 {
3696 }
3697
3698 static void intel_crtc_update_sarea(struct drm_crtc *crtc,
3699                                     bool enabled)
3700 {
3701         struct drm_device *dev = crtc->dev;
3702         struct drm_i915_master_private *master_priv;
3703         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3704         int pipe = intel_crtc->pipe;
3705
3706         if (!dev->primary->master)
3707                 return;
3708
3709         master_priv = dev->primary->master->driver_priv;
3710         if (!master_priv->sarea_priv)
3711                 return;
3712
3713         switch (pipe) {
3714         case 0:
3715                 master_priv->sarea_priv->pipeA_w = enabled ? crtc->mode.hdisplay : 0;
3716                 master_priv->sarea_priv->pipeA_h = enabled ? crtc->mode.vdisplay : 0;
3717                 break;
3718         case 1:
3719                 master_priv->sarea_priv->pipeB_w = enabled ? crtc->mode.hdisplay : 0;
3720                 master_priv->sarea_priv->pipeB_h = enabled ? crtc->mode.vdisplay : 0;
3721                 break;
3722         default:
3723                 DRM_ERROR("Can't update pipe %c in SAREA\n", pipe_name(pipe));
3724                 break;
3725         }
3726 }
3727
3728 /**
3729  * Sets the power management mode of the pipe and plane.
3730  */
3731 void intel_crtc_update_dpms(struct drm_crtc *crtc)
3732 {
3733         struct drm_device *dev = crtc->dev;
3734         struct drm_i915_private *dev_priv = dev->dev_private;
3735         struct intel_encoder *intel_encoder;
3736         bool enable = false;
3737
3738         for_each_encoder_on_crtc(dev, crtc, intel_encoder)
3739                 enable |= intel_encoder->connectors_active;
3740
3741         if (enable)
3742                 dev_priv->display.crtc_enable(crtc);
3743         else
3744                 dev_priv->display.crtc_disable(crtc);
3745
3746         intel_crtc_update_sarea(crtc, enable);
3747 }
3748
3749 static void intel_crtc_noop(struct drm_crtc *crtc)
3750 {
3751 }
3752
3753 static void intel_crtc_disable(struct drm_crtc *crtc)
3754 {
3755         struct drm_device *dev = crtc->dev;
3756         struct drm_connector *connector;
3757         struct drm_i915_private *dev_priv = dev->dev_private;
3758
3759         /* crtc should still be enabled when we disable it. */
3760         WARN_ON(!crtc->enabled);
3761
3762         dev_priv->display.crtc_disable(crtc);
3763         intel_crtc_update_sarea(crtc, false);
3764         dev_priv->display.off(crtc);
3765
3766         assert_plane_disabled(dev->dev_private, to_intel_crtc(crtc)->plane);
3767         assert_pipe_disabled(dev->dev_private, to_intel_crtc(crtc)->pipe);
3768
3769         if (crtc->fb) {
3770                 mutex_lock(&dev->struct_mutex);
3771                 intel_unpin_fb_obj(to_intel_framebuffer(crtc->fb)->obj);
3772                 mutex_unlock(&dev->struct_mutex);
3773                 crtc->fb = NULL;
3774         }
3775
3776         /* Update computed state. */
3777         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
3778                 if (!connector->encoder || !connector->encoder->crtc)
3779                         continue;
3780
3781                 if (connector->encoder->crtc != crtc)
3782                         continue;
3783
3784                 connector->dpms = DRM_MODE_DPMS_OFF;
3785                 to_intel_encoder(connector->encoder)->connectors_active = false;
3786         }
3787 }
3788
3789 void intel_modeset_disable(struct drm_device *dev)
3790 {
3791         struct drm_crtc *crtc;
3792
3793         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3794                 if (crtc->enabled)
3795                         intel_crtc_disable(crtc);
3796         }
3797 }
3798
3799 void intel_encoder_noop(struct drm_encoder *encoder)
3800 {
3801 }
3802
3803 void intel_encoder_destroy(struct drm_encoder *encoder)
3804 {
3805         struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
3806
3807         drm_encoder_cleanup(encoder);
3808         kfree(intel_encoder);
3809 }
3810
3811 /* Simple dpms helper for encodres with just one connector, no cloning and only
3812  * one kind of off state. It clamps all !ON modes to fully OFF and changes the
3813  * state of the entire output pipe. */
3814 void intel_encoder_dpms(struct intel_encoder *encoder, int mode)
3815 {
3816         if (mode == DRM_MODE_DPMS_ON) {
3817                 encoder->connectors_active = true;
3818
3819                 intel_crtc_update_dpms(encoder->base.crtc);
3820         } else {
3821                 encoder->connectors_active = false;
3822
3823                 intel_crtc_update_dpms(encoder->base.crtc);
3824         }
3825 }
3826
3827 /* Cross check the actual hw state with our own modeset state tracking (and it's
3828  * internal consistency). */
3829 static void intel_connector_check_state(struct intel_connector *connector)
3830 {
3831         if (connector->get_hw_state(connector)) {
3832                 struct intel_encoder *encoder = connector->encoder;
3833                 struct drm_crtc *crtc;
3834                 bool encoder_enabled;
3835                 enum pipe pipe;
3836
3837                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
3838                               connector->base.base.id,
3839                               drm_get_connector_name(&connector->base));
3840
3841                 WARN(connector->base.dpms == DRM_MODE_DPMS_OFF,
3842                      "wrong connector dpms state\n");
3843                 WARN(connector->base.encoder != &encoder->base,
3844                      "active connector not linked to encoder\n");
3845                 WARN(!encoder->connectors_active,
3846                      "encoder->connectors_active not set\n");
3847
3848                 encoder_enabled = encoder->get_hw_state(encoder, &pipe);
3849                 WARN(!encoder_enabled, "encoder not enabled\n");
3850                 if (WARN_ON(!encoder->base.crtc))
3851                         return;
3852
3853                 crtc = encoder->base.crtc;
3854
3855                 WARN(!crtc->enabled, "crtc not enabled\n");
3856                 WARN(!to_intel_crtc(crtc)->active, "crtc not active\n");
3857                 WARN(pipe != to_intel_crtc(crtc)->pipe,
3858                      "encoder active on the wrong pipe\n");
3859         }
3860 }
3861
3862 /* Even simpler default implementation, if there's really no special case to
3863  * consider. */
3864 void intel_connector_dpms(struct drm_connector *connector, int mode)
3865 {
3866         struct intel_encoder *encoder = intel_attached_encoder(connector);
3867
3868         /* All the simple cases only support two dpms states. */
3869         if (mode != DRM_MODE_DPMS_ON)
3870                 mode = DRM_MODE_DPMS_OFF;
3871
3872         if (mode == connector->dpms)
3873                 return;
3874
3875         connector->dpms = mode;
3876
3877         /* Only need to change hw state when actually enabled */
3878         if (encoder->base.crtc)
3879                 intel_encoder_dpms(encoder, mode);
3880         else
3881                 WARN_ON(encoder->connectors_active != false);
3882
3883         intel_modeset_check_state(connector->dev);
3884 }
3885
3886 /* Simple connector->get_hw_state implementation for encoders that support only
3887  * one connector and no cloning and hence the encoder state determines the state
3888  * of the connector. */
3889 bool intel_connector_get_hw_state(struct intel_connector *connector)
3890 {
3891         enum pipe pipe = 0;
3892         struct intel_encoder *encoder = connector->encoder;
3893
3894         return encoder->get_hw_state(encoder, &pipe);
3895 }
3896
3897 static bool intel_crtc_mode_fixup(struct drm_crtc *crtc,
3898                                   const struct drm_display_mode *mode,
3899                                   struct drm_display_mode *adjusted_mode)
3900 {
3901         struct drm_device *dev = crtc->dev;
3902
3903         if (HAS_PCH_SPLIT(dev)) {
3904                 /* FDI link clock is fixed at 2.7G */
3905                 if (mode->clock * 3 > IRONLAKE_FDI_FREQ * 4)
3906                         return false;
3907         }
3908
3909         /* All interlaced capable intel hw wants timings in frames. Note though
3910          * that intel_lvds_mode_fixup does some funny tricks with the crtc
3911          * timings, so we need to be careful not to clobber these.*/
3912         if (!(adjusted_mode->private_flags & INTEL_MODE_CRTC_TIMINGS_SET))
3913                 drm_mode_set_crtcinfo(adjusted_mode, 0);
3914
3915         /* WaPruneModeWithIncorrectHsyncOffset: Cantiga+ cannot handle modes
3916          * with a hsync front porch of 0.
3917          */
3918         if ((INTEL_INFO(dev)->gen > 4 || IS_G4X(dev)) &&
3919                 adjusted_mode->hsync_start == adjusted_mode->hdisplay)
3920                 return false;
3921
3922         return true;
3923 }
3924
3925 static int valleyview_get_display_clock_speed(struct drm_device *dev)
3926 {
3927         return 400000; /* FIXME */
3928 }
3929
3930 static int i945_get_display_clock_speed(struct drm_device *dev)
3931 {
3932         return 400000;
3933 }
3934
3935 static int i915_get_display_clock_speed(struct drm_device *dev)
3936 {
3937         return 333000;
3938 }
3939
3940 static int i9xx_misc_get_display_clock_speed(struct drm_device *dev)
3941 {
3942         return 200000;
3943 }
3944
3945 static int i915gm_get_display_clock_speed(struct drm_device *dev)
3946 {
3947         u16 gcfgc = 0;
3948
3949         pci_read_config_word(dev->pdev, GCFGC, &gcfgc);
3950
3951         if (gcfgc & GC_LOW_FREQUENCY_ENABLE)
3952                 return 133000;
3953         else {
3954                 switch (gcfgc & GC_DISPLAY_CLOCK_MASK) {
3955                 case GC_DISPLAY_CLOCK_333_MHZ:
3956                         return 333000;
3957                 default:
3958                 case GC_DISPLAY_CLOCK_190_200_MHZ:
3959                         return 190000;
3960                 }
3961         }
3962 }
3963
3964 static int i865_get_display_clock_speed(struct drm_device *dev)
3965 {
3966         return 266000;
3967 }
3968
3969 static int i855_get_display_clock_speed(struct drm_device *dev)
3970 {
3971         u16 hpllcc = 0;
3972         /* Assume that the hardware is in the high speed state.  This
3973          * should be the default.
3974          */
3975         switch (hpllcc & GC_CLOCK_CONTROL_MASK) {
3976         case GC_CLOCK_133_200:
3977         case GC_CLOCK_100_200:
3978                 return 200000;
3979         case GC_CLOCK_166_250:
3980                 return 250000;
3981         case GC_CLOCK_100_133:
3982                 return 133000;
3983         }
3984
3985         /* Shouldn't happen */
3986         return 0;
3987 }
3988
3989 static int i830_get_display_clock_speed(struct drm_device *dev)
3990 {
3991         return 133000;
3992 }
3993
3994 struct fdi_m_n {
3995         u32        tu;
3996         u32        gmch_m;
3997         u32        gmch_n;
3998         u32        link_m;
3999         u32        link_n;
4000 };
4001
4002 static void
4003 fdi_reduce_ratio(u32 *num, u32 *den)
4004 {
4005         while (*num > 0xffffff || *den > 0xffffff) {
4006                 *num >>= 1;
4007                 *den >>= 1;
4008         }
4009 }
4010
4011 static void
4012 ironlake_compute_m_n(int bits_per_pixel, int nlanes, int pixel_clock,
4013                      int link_clock, struct fdi_m_n *m_n)
4014 {
4015         m_n->tu = 64; /* default size */
4016
4017         /* BUG_ON(pixel_clock > INT_MAX / 36); */
4018         m_n->gmch_m = bits_per_pixel * pixel_clock;
4019         m_n->gmch_n = link_clock * nlanes * 8;
4020         fdi_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n);
4021
4022         m_n->link_m = pixel_clock;
4023         m_n->link_n = link_clock;
4024         fdi_reduce_ratio(&m_n->link_m, &m_n->link_n);
4025 }
4026
4027 static inline bool intel_panel_use_ssc(struct drm_i915_private *dev_priv)
4028 {
4029         if (i915_panel_use_ssc >= 0)
4030                 return i915_panel_use_ssc != 0;
4031         return dev_priv->lvds_use_ssc
4032                 && !(dev_priv->quirks & QUIRK_LVDS_SSC_DISABLE);
4033 }
4034
4035 /**
4036  * intel_choose_pipe_bpp_dither - figure out what color depth the pipe should send
4037  * @crtc: CRTC structure
4038  * @mode: requested mode
4039  *
4040  * A pipe may be connected to one or more outputs.  Based on the depth of the
4041  * attached framebuffer, choose a good color depth to use on the pipe.
4042  *
4043  * If possible, match the pipe depth to the fb depth.  In some cases, this
4044  * isn't ideal, because the connected output supports a lesser or restricted
4045  * set of depths.  Resolve that here:
4046  *    LVDS typically supports only 6bpc, so clamp down in that case
4047  *    HDMI supports only 8bpc or 12bpc, so clamp to 8bpc with dither for 10bpc
4048  *    Displays may support a restricted set as well, check EDID and clamp as
4049  *      appropriate.
4050  *    DP may want to dither down to 6bpc to fit larger modes
4051  *
4052  * RETURNS:
4053  * Dithering requirement (i.e. false if display bpc and pipe bpc match,
4054  * true if they don't match).
4055  */
4056 static bool intel_choose_pipe_bpp_dither(struct drm_crtc *crtc,
4057                                          struct drm_framebuffer *fb,
4058                                          unsigned int *pipe_bpp,
4059                                          struct drm_display_mode *mode)
4060 {
4061         struct drm_device *dev = crtc->dev;
4062         struct drm_i915_private *dev_priv = dev->dev_private;
4063         struct drm_connector *connector;
4064         struct intel_encoder *intel_encoder;
4065         unsigned int display_bpc = UINT_MAX, bpc;
4066
4067         /* Walk the encoders & connectors on this crtc, get min bpc */
4068         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4069
4070                 if (intel_encoder->type == INTEL_OUTPUT_LVDS) {
4071                         unsigned int lvds_bpc;
4072
4073                         if ((I915_READ(PCH_LVDS) & LVDS_A3_POWER_MASK) ==
4074                             LVDS_A3_POWER_UP)
4075                                 lvds_bpc = 8;
4076                         else
4077                                 lvds_bpc = 6;
4078
4079                         if (lvds_bpc < display_bpc) {
4080                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to LVDS (%d)\n", display_bpc, lvds_bpc);
4081                                 display_bpc = lvds_bpc;
4082                         }
4083                         continue;
4084                 }
4085
4086                 /* Not one of the known troublemakers, check the EDID */
4087                 list_for_each_entry(connector, &dev->mode_config.connector_list,
4088                                     head) {
4089                         if (connector->encoder != &intel_encoder->base)
4090                                 continue;
4091
4092                         /* Don't use an invalid EDID bpc value */
4093                         if (connector->display_info.bpc &&
4094                             connector->display_info.bpc < display_bpc) {
4095                                 DRM_DEBUG_KMS("clamping display bpc (was %d) to EDID reported max of %d\n", display_bpc, connector->display_info.bpc);
4096                                 display_bpc = connector->display_info.bpc;
4097                         }
4098                 }
4099
4100                 /*
4101                  * HDMI is either 12 or 8, so if the display lets 10bpc sneak
4102                  * through, clamp it down.  (Note: >12bpc will be caught below.)
4103                  */
4104                 if (intel_encoder->type == INTEL_OUTPUT_HDMI) {
4105                         if (display_bpc > 8 && display_bpc < 12) {
4106                                 DRM_DEBUG_KMS("forcing bpc to 12 for HDMI\n");
4107                                 display_bpc = 12;
4108                         } else {
4109                                 DRM_DEBUG_KMS("forcing bpc to 8 for HDMI\n");
4110                                 display_bpc = 8;
4111                         }
4112                 }
4113         }
4114
4115         if (mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4116                 DRM_DEBUG_KMS("Dithering DP to 6bpc\n");
4117                 display_bpc = 6;
4118         }
4119
4120         /*
4121          * We could just drive the pipe at the highest bpc all the time and
4122          * enable dithering as needed, but that costs bandwidth.  So choose
4123          * the minimum value that expresses the full color range of the fb but
4124          * also stays within the max display bpc discovered above.
4125          */
4126
4127         switch (fb->depth) {
4128         case 8:
4129                 bpc = 8; /* since we go through a colormap */
4130                 break;
4131         case 15:
4132         case 16:
4133                 bpc = 6; /* min is 18bpp */
4134                 break;
4135         case 24:
4136                 bpc = 8;
4137                 break;
4138         case 30:
4139                 bpc = 10;
4140                 break;
4141         case 48:
4142                 bpc = 12;
4143                 break;
4144         default:
4145                 DRM_DEBUG("unsupported depth, assuming 24 bits\n");
4146                 bpc = min((unsigned int)8, display_bpc);
4147                 break;
4148         }
4149
4150         display_bpc = min(display_bpc, bpc);
4151
4152         DRM_DEBUG_KMS("setting pipe bpc to %d (max display bpc %d)\n",
4153                       bpc, display_bpc);
4154
4155         *pipe_bpp = display_bpc * 3;
4156
4157         return display_bpc != bpc;
4158 }
4159
4160 static int vlv_get_refclk(struct drm_crtc *crtc)
4161 {
4162         struct drm_device *dev = crtc->dev;
4163         struct drm_i915_private *dev_priv = dev->dev_private;
4164         int refclk = 27000; /* for DP & HDMI */
4165
4166         return 100000; /* only one validated so far */
4167
4168         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_ANALOG)) {
4169                 refclk = 96000;
4170         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4171                 if (intel_panel_use_ssc(dev_priv))
4172                         refclk = 100000;
4173                 else
4174                         refclk = 96000;
4175         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4176                 refclk = 100000;
4177         }
4178
4179         return refclk;
4180 }
4181
4182 static int i9xx_get_refclk(struct drm_crtc *crtc, int num_connectors)
4183 {
4184         struct drm_device *dev = crtc->dev;
4185         struct drm_i915_private *dev_priv = dev->dev_private;
4186         int refclk;
4187
4188         if (IS_VALLEYVIEW(dev)) {
4189                 refclk = vlv_get_refclk(crtc);
4190         } else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4191             intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4192                 refclk = dev_priv->lvds_ssc_freq * 1000;
4193                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4194                               refclk / 1000);
4195         } else if (!IS_GEN2(dev)) {
4196                 refclk = 96000;
4197         } else {
4198                 refclk = 48000;
4199         }
4200
4201         return refclk;
4202 }
4203
4204 static void i9xx_adjust_sdvo_tv_clock(struct drm_display_mode *adjusted_mode,
4205                                       intel_clock_t *clock)
4206 {
4207         /* SDVO TV has fixed PLL values depend on its clock range,
4208            this mirrors vbios setting. */
4209         if (adjusted_mode->clock >= 100000
4210             && adjusted_mode->clock < 140500) {
4211                 clock->p1 = 2;
4212                 clock->p2 = 10;
4213                 clock->n = 3;
4214                 clock->m1 = 16;
4215                 clock->m2 = 8;
4216         } else if (adjusted_mode->clock >= 140500
4217                    && adjusted_mode->clock <= 200000) {
4218                 clock->p1 = 1;
4219                 clock->p2 = 10;
4220                 clock->n = 6;
4221                 clock->m1 = 12;
4222                 clock->m2 = 8;
4223         }
4224 }
4225
4226 static void i9xx_update_pll_dividers(struct drm_crtc *crtc,
4227                                      intel_clock_t *clock,
4228                                      intel_clock_t *reduced_clock)
4229 {
4230         struct drm_device *dev = crtc->dev;
4231         struct drm_i915_private *dev_priv = dev->dev_private;
4232         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4233         int pipe = intel_crtc->pipe;
4234         u32 fp, fp2 = 0;
4235
4236         if (IS_PINEVIEW(dev)) {
4237                 fp = (1 << clock->n) << 16 | clock->m1 << 8 | clock->m2;
4238                 if (reduced_clock)
4239                         fp2 = (1 << reduced_clock->n) << 16 |
4240                                 reduced_clock->m1 << 8 | reduced_clock->m2;
4241         } else {
4242                 fp = clock->n << 16 | clock->m1 << 8 | clock->m2;
4243                 if (reduced_clock)
4244                         fp2 = reduced_clock->n << 16 | reduced_clock->m1 << 8 |
4245                                 reduced_clock->m2;
4246         }
4247
4248         I915_WRITE(FP0(pipe), fp);
4249
4250         intel_crtc->lowfreq_avail = false;
4251         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4252             reduced_clock && i915_powersave) {
4253                 I915_WRITE(FP1(pipe), fp2);
4254                 intel_crtc->lowfreq_avail = true;
4255         } else {
4256                 I915_WRITE(FP1(pipe), fp);
4257         }
4258 }
4259
4260 static void vlv_update_pll(struct drm_crtc *crtc,
4261                            struct drm_display_mode *mode,
4262                            struct drm_display_mode *adjusted_mode,
4263                            intel_clock_t *clock, intel_clock_t *reduced_clock,
4264                            int num_connectors)
4265 {
4266         struct drm_device *dev = crtc->dev;
4267         struct drm_i915_private *dev_priv = dev->dev_private;
4268         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4269         int pipe = intel_crtc->pipe;
4270         u32 dpll, mdiv, pdiv;
4271         u32 bestn, bestm1, bestm2, bestp1, bestp2;
4272         bool is_sdvo;
4273         u32 temp;
4274
4275         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4276                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4277
4278         dpll = DPLL_VGA_MODE_DIS;
4279         dpll |= DPLL_EXT_BUFFER_ENABLE_VLV;
4280         dpll |= DPLL_REFA_CLK_ENABLE_VLV;
4281         dpll |= DPLL_INTEGRATED_CLOCK_VLV;
4282
4283         I915_WRITE(DPLL(pipe), dpll);
4284         POSTING_READ(DPLL(pipe));
4285
4286         bestn = clock->n;
4287         bestm1 = clock->m1;
4288         bestm2 = clock->m2;
4289         bestp1 = clock->p1;
4290         bestp2 = clock->p2;
4291
4292         /*
4293          * In Valleyview PLL and program lane counter registers are exposed
4294          * through DPIO interface
4295          */
4296         mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK));
4297         mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT));
4298         mdiv |= ((bestn << DPIO_N_SHIFT));
4299         mdiv |= (1 << DPIO_POST_DIV_SHIFT);
4300         mdiv |= (1 << DPIO_K_SHIFT);
4301         mdiv |= DPIO_ENABLE_CALIBRATION;
4302         intel_dpio_write(dev_priv, DPIO_DIV(pipe), mdiv);
4303
4304         intel_dpio_write(dev_priv, DPIO_CORE_CLK(pipe), 0x01000000);
4305
4306         pdiv = (1 << DPIO_REFSEL_OVERRIDE) | (5 << DPIO_PLL_MODESEL_SHIFT) |
4307                 (3 << DPIO_BIAS_CURRENT_CTL_SHIFT) | (1<<20) |
4308                 (7 << DPIO_PLL_REFCLK_SEL_SHIFT) | (8 << DPIO_DRIVER_CTL_SHIFT) |
4309                 (5 << DPIO_CLK_BIAS_CTL_SHIFT);
4310         intel_dpio_write(dev_priv, DPIO_REFSFR(pipe), pdiv);
4311
4312         intel_dpio_write(dev_priv, DPIO_LFP_COEFF(pipe), 0x005f003b);
4313
4314         dpll |= DPLL_VCO_ENABLE;
4315         I915_WRITE(DPLL(pipe), dpll);
4316         POSTING_READ(DPLL(pipe));
4317         if (wait_for(((I915_READ(DPLL(pipe)) & DPLL_LOCK_VLV) == DPLL_LOCK_VLV), 1))
4318                 DRM_ERROR("DPLL %d failed to lock\n", pipe);
4319
4320         intel_dpio_write(dev_priv, DPIO_FASTCLK_DISABLE, 0x620);
4321
4322         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4323                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4324
4325         I915_WRITE(DPLL(pipe), dpll);
4326
4327         /* Wait for the clocks to stabilize. */
4328         POSTING_READ(DPLL(pipe));
4329         udelay(150);
4330
4331         temp = 0;
4332         if (is_sdvo) {
4333                 temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4334                 if (temp > 1)
4335                         temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4336                 else
4337                         temp = 0;
4338         }
4339         I915_WRITE(DPLL_MD(pipe), temp);
4340         POSTING_READ(DPLL_MD(pipe));
4341
4342         /* Now program lane control registers */
4343         if(intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)
4344                         || intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI))
4345         {
4346                 temp = 0x1000C4;
4347                 if(pipe == 1)
4348                         temp |= (1 << 21);
4349                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL1, temp);
4350         }
4351         if(intel_pipe_has_type(crtc,INTEL_OUTPUT_EDP))
4352         {
4353                 temp = 0x1000C4;
4354                 if(pipe == 1)
4355                         temp |= (1 << 21);
4356                 intel_dpio_write(dev_priv, DPIO_DATA_CHANNEL2, temp);
4357         }
4358 }
4359
4360 static void i9xx_update_pll(struct drm_crtc *crtc,
4361                             struct drm_display_mode *mode,
4362                             struct drm_display_mode *adjusted_mode,
4363                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4364                             int num_connectors)
4365 {
4366         struct drm_device *dev = crtc->dev;
4367         struct drm_i915_private *dev_priv = dev->dev_private;
4368         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4369         struct intel_encoder *encoder;
4370         int pipe = intel_crtc->pipe;
4371         u32 dpll;
4372         bool is_sdvo;
4373
4374         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4375
4376         is_sdvo = intel_pipe_has_type(crtc, INTEL_OUTPUT_SDVO) ||
4377                 intel_pipe_has_type(crtc, INTEL_OUTPUT_HDMI);
4378
4379         dpll = DPLL_VGA_MODE_DIS;
4380
4381         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS))
4382                 dpll |= DPLLB_MODE_LVDS;
4383         else
4384                 dpll |= DPLLB_MODE_DAC_SERIAL;
4385         if (is_sdvo) {
4386                 int pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
4387                 if (pixel_multiplier > 1) {
4388                         if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev))
4389                                 dpll |= (pixel_multiplier - 1) << SDVO_MULTIPLIER_SHIFT_HIRES;
4390                 }
4391                 dpll |= DPLL_DVO_HIGH_SPEED;
4392         }
4393         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4394                 dpll |= DPLL_DVO_HIGH_SPEED;
4395
4396         /* compute bitmask from p1 value */
4397         if (IS_PINEVIEW(dev))
4398                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW;
4399         else {
4400                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4401                 if (IS_G4X(dev) && reduced_clock)
4402                         dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
4403         }
4404         switch (clock->p2) {
4405         case 5:
4406                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
4407                 break;
4408         case 7:
4409                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
4410                 break;
4411         case 10:
4412                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
4413                 break;
4414         case 14:
4415                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
4416                 break;
4417         }
4418         if (INTEL_INFO(dev)->gen >= 4)
4419                 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT);
4420
4421         if (is_sdvo && intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4422                 dpll |= PLL_REF_INPUT_TVCLKINBC;
4423         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4424                 /* XXX: just matching BIOS for now */
4425                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4426                 dpll |= 3;
4427         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4428                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4429                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4430         else
4431                 dpll |= PLL_REF_INPUT_DREFCLK;
4432
4433         dpll |= DPLL_VCO_ENABLE;
4434         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4435         POSTING_READ(DPLL(pipe));
4436         udelay(150);
4437
4438         for_each_encoder_on_crtc(dev, crtc, encoder)
4439                 if (encoder->pre_pll_enable)
4440                         encoder->pre_pll_enable(encoder);
4441
4442         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT))
4443                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
4444
4445         I915_WRITE(DPLL(pipe), dpll);
4446
4447         /* Wait for the clocks to stabilize. */
4448         POSTING_READ(DPLL(pipe));
4449         udelay(150);
4450
4451         if (INTEL_INFO(dev)->gen >= 4) {
4452                 u32 temp = 0;
4453                 if (is_sdvo) {
4454                         temp = intel_mode_get_pixel_multiplier(adjusted_mode);
4455                         if (temp > 1)
4456                                 temp = (temp - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT;
4457                         else
4458                                 temp = 0;
4459                 }
4460                 I915_WRITE(DPLL_MD(pipe), temp);
4461         } else {
4462                 /* The pixel multiplier can only be updated once the
4463                  * DPLL is enabled and the clocks are stable.
4464                  *
4465                  * So write it again.
4466                  */
4467                 I915_WRITE(DPLL(pipe), dpll);
4468         }
4469 }
4470
4471 static void i8xx_update_pll(struct drm_crtc *crtc,
4472                             struct drm_display_mode *adjusted_mode,
4473                             intel_clock_t *clock, intel_clock_t *reduced_clock,
4474                             int num_connectors)
4475 {
4476         struct drm_device *dev = crtc->dev;
4477         struct drm_i915_private *dev_priv = dev->dev_private;
4478         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4479         struct intel_encoder *encoder;
4480         int pipe = intel_crtc->pipe;
4481         u32 dpll;
4482
4483         i9xx_update_pll_dividers(crtc, clock, reduced_clock);
4484
4485         dpll = DPLL_VGA_MODE_DIS;
4486
4487         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS)) {
4488                 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4489         } else {
4490                 if (clock->p1 == 2)
4491                         dpll |= PLL_P1_DIVIDE_BY_TWO;
4492                 else
4493                         dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT;
4494                 if (clock->p2 == 4)
4495                         dpll |= PLL_P2_DIVIDE_BY_4;
4496         }
4497
4498         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_TVOUT))
4499                 /* XXX: just matching BIOS for now */
4500                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
4501                 dpll |= 3;
4502         else if (intel_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
4503                  intel_panel_use_ssc(dev_priv) && num_connectors < 2)
4504                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
4505         else
4506                 dpll |= PLL_REF_INPUT_DREFCLK;
4507
4508         dpll |= DPLL_VCO_ENABLE;
4509         I915_WRITE(DPLL(pipe), dpll & ~DPLL_VCO_ENABLE);
4510         POSTING_READ(DPLL(pipe));
4511         udelay(150);
4512
4513         for_each_encoder_on_crtc(dev, crtc, encoder)
4514                 if (encoder->pre_pll_enable)
4515                         encoder->pre_pll_enable(encoder);
4516
4517         I915_WRITE(DPLL(pipe), dpll);
4518
4519         /* Wait for the clocks to stabilize. */
4520         POSTING_READ(DPLL(pipe));
4521         udelay(150);
4522
4523         /* The pixel multiplier can only be updated once the
4524          * DPLL is enabled and the clocks are stable.
4525          *
4526          * So write it again.
4527          */
4528         I915_WRITE(DPLL(pipe), dpll);
4529 }
4530
4531 static void intel_set_pipe_timings(struct intel_crtc *intel_crtc,
4532                                    struct drm_display_mode *mode,
4533                                    struct drm_display_mode *adjusted_mode)
4534 {
4535         struct drm_device *dev = intel_crtc->base.dev;
4536         struct drm_i915_private *dev_priv = dev->dev_private;
4537         enum pipe pipe = intel_crtc->pipe;
4538         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4539         uint32_t vsyncshift;
4540
4541         if (!IS_GEN2(dev) && adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) {
4542                 /* the chip adds 2 halflines automatically */
4543                 adjusted_mode->crtc_vtotal -= 1;
4544                 adjusted_mode->crtc_vblank_end -= 1;
4545                 vsyncshift = adjusted_mode->crtc_hsync_start
4546                              - adjusted_mode->crtc_htotal / 2;
4547         } else {
4548                 vsyncshift = 0;
4549         }
4550
4551         if (INTEL_INFO(dev)->gen > 3)
4552                 I915_WRITE(VSYNCSHIFT(cpu_transcoder), vsyncshift);
4553
4554         I915_WRITE(HTOTAL(cpu_transcoder),
4555                    (adjusted_mode->crtc_hdisplay - 1) |
4556                    ((adjusted_mode->crtc_htotal - 1) << 16));
4557         I915_WRITE(HBLANK(cpu_transcoder),
4558                    (adjusted_mode->crtc_hblank_start - 1) |
4559                    ((adjusted_mode->crtc_hblank_end - 1) << 16));
4560         I915_WRITE(HSYNC(cpu_transcoder),
4561                    (adjusted_mode->crtc_hsync_start - 1) |
4562                    ((adjusted_mode->crtc_hsync_end - 1) << 16));
4563
4564         I915_WRITE(VTOTAL(cpu_transcoder),
4565                    (adjusted_mode->crtc_vdisplay - 1) |
4566                    ((adjusted_mode->crtc_vtotal - 1) << 16));
4567         I915_WRITE(VBLANK(cpu_transcoder),
4568                    (adjusted_mode->crtc_vblank_start - 1) |
4569                    ((adjusted_mode->crtc_vblank_end - 1) << 16));
4570         I915_WRITE(VSYNC(cpu_transcoder),
4571                    (adjusted_mode->crtc_vsync_start - 1) |
4572                    ((adjusted_mode->crtc_vsync_end - 1) << 16));
4573
4574         /* Workaround: when the EDP input selection is B, the VTOTAL_B must be
4575          * programmed with the VTOTAL_EDP value. Same for VTOTAL_C. This is
4576          * documented on the DDI_FUNC_CTL register description, EDP Input Select
4577          * bits. */
4578         if (IS_HASWELL(dev) && cpu_transcoder == TRANSCODER_EDP &&
4579             (pipe == PIPE_B || pipe == PIPE_C))
4580                 I915_WRITE(VTOTAL(pipe), I915_READ(VTOTAL(cpu_transcoder)));
4581
4582         /* pipesrc controls the size that is scaled from, which should
4583          * always be the user's requested size.
4584          */
4585         I915_WRITE(PIPESRC(pipe),
4586                    ((mode->hdisplay - 1) << 16) | (mode->vdisplay - 1));
4587 }
4588
4589 static int i9xx_crtc_mode_set(struct drm_crtc *crtc,
4590                               struct drm_display_mode *mode,
4591                               struct drm_display_mode *adjusted_mode,
4592                               int x, int y,
4593                               struct drm_framebuffer *fb)
4594 {
4595         struct drm_device *dev = crtc->dev;
4596         struct drm_i915_private *dev_priv = dev->dev_private;
4597         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4598         int pipe = intel_crtc->pipe;
4599         int plane = intel_crtc->plane;
4600         int refclk, num_connectors = 0;
4601         intel_clock_t clock, reduced_clock;
4602         u32 dspcntr, pipeconf;
4603         bool ok, has_reduced_clock = false, is_sdvo = false;
4604         bool is_lvds = false, is_tv = false, is_dp = false;
4605         struct intel_encoder *encoder;
4606         const intel_limit_t *limit;
4607         int ret;
4608
4609         for_each_encoder_on_crtc(dev, crtc, encoder) {
4610                 switch (encoder->type) {
4611                 case INTEL_OUTPUT_LVDS:
4612                         is_lvds = true;
4613                         break;
4614                 case INTEL_OUTPUT_SDVO:
4615                 case INTEL_OUTPUT_HDMI:
4616                         is_sdvo = true;
4617                         if (encoder->needs_tv_clock)
4618                                 is_tv = true;
4619                         break;
4620                 case INTEL_OUTPUT_TVOUT:
4621                         is_tv = true;
4622                         break;
4623                 case INTEL_OUTPUT_DISPLAYPORT:
4624                         is_dp = true;
4625                         break;
4626                 }
4627
4628                 num_connectors++;
4629         }
4630
4631         refclk = i9xx_get_refclk(crtc, num_connectors);
4632
4633         /*
4634          * Returns a set of divisors for the desired target clock with the given
4635          * refclk, or FALSE.  The returned values represent the clock equation:
4636          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
4637          */
4638         limit = intel_limit(crtc, refclk);
4639         ok = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
4640                              &clock);
4641         if (!ok) {
4642                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
4643                 return -EINVAL;
4644         }
4645
4646         /* Ensure that the cursor is valid for the new mode before changing... */
4647         intel_crtc_update_cursor(crtc, true);
4648
4649         if (is_lvds && dev_priv->lvds_downclock_avail) {
4650                 /*
4651                  * Ensure we match the reduced clock's P to the target clock.
4652                  * If the clocks don't match, we can't switch the display clock
4653                  * by using the FP0/FP1. In such case we will disable the LVDS
4654                  * downclock feature.
4655                 */
4656                 has_reduced_clock = limit->find_pll(limit, crtc,
4657                                                     dev_priv->lvds_downclock,
4658                                                     refclk,
4659                                                     &clock,
4660                                                     &reduced_clock);
4661         }
4662
4663         if (is_sdvo && is_tv)
4664                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, &clock);
4665
4666         if (IS_GEN2(dev))
4667                 i8xx_update_pll(crtc, adjusted_mode, &clock,
4668                                 has_reduced_clock ? &reduced_clock : NULL,
4669                                 num_connectors);
4670         else if (IS_VALLEYVIEW(dev))
4671                 vlv_update_pll(crtc, mode, adjusted_mode, &clock,
4672                                 has_reduced_clock ? &reduced_clock : NULL,
4673                                 num_connectors);
4674         else
4675                 i9xx_update_pll(crtc, mode, adjusted_mode, &clock,
4676                                 has_reduced_clock ? &reduced_clock : NULL,
4677                                 num_connectors);
4678
4679         /* setup pipeconf */
4680         pipeconf = I915_READ(PIPECONF(pipe));
4681
4682         /* Set up the display plane register */
4683         dspcntr = DISPPLANE_GAMMA_ENABLE;
4684
4685         if (pipe == 0)
4686                 dspcntr &= ~DISPPLANE_SEL_PIPE_MASK;
4687         else
4688                 dspcntr |= DISPPLANE_SEL_PIPE_B;
4689
4690         if (pipe == 0 && INTEL_INFO(dev)->gen < 4) {
4691                 /* Enable pixel doubling when the dot clock is > 90% of the (display)
4692                  * core speed.
4693                  *
4694                  * XXX: No double-wide on 915GM pipe B. Is that the only reason for the
4695                  * pipe == 0 check?
4696                  */
4697                 if (mode->clock >
4698                     dev_priv->display.get_display_clock_speed(dev) * 9 / 10)
4699                         pipeconf |= PIPECONF_DOUBLE_WIDE;
4700                 else
4701                         pipeconf &= ~PIPECONF_DOUBLE_WIDE;
4702         }
4703
4704         /* default to 8bpc */
4705         pipeconf &= ~(PIPECONF_BPP_MASK | PIPECONF_DITHER_EN);
4706         if (is_dp) {
4707                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4708                         pipeconf |= PIPECONF_BPP_6 |
4709                                     PIPECONF_DITHER_EN |
4710                                     PIPECONF_DITHER_TYPE_SP;
4711                 }
4712         }
4713
4714         if (IS_VALLEYVIEW(dev) && intel_pipe_has_type(crtc, INTEL_OUTPUT_EDP)) {
4715                 if (adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC) {
4716                         pipeconf |= PIPECONF_BPP_6 |
4717                                         PIPECONF_ENABLE |
4718                                         I965_PIPECONF_ACTIVE;
4719                 }
4720         }
4721
4722         DRM_DEBUG_KMS("Mode for pipe %c:\n", pipe == 0 ? 'A' : 'B');
4723         drm_mode_debug_printmodeline(mode);
4724
4725         if (HAS_PIPE_CXSR(dev)) {
4726                 if (intel_crtc->lowfreq_avail) {
4727                         DRM_DEBUG_KMS("enabling CxSR downclocking\n");
4728                         pipeconf |= PIPECONF_CXSR_DOWNCLOCK;
4729                 } else {
4730                         DRM_DEBUG_KMS("disabling CxSR downclocking\n");
4731                         pipeconf &= ~PIPECONF_CXSR_DOWNCLOCK;
4732                 }
4733         }
4734
4735         pipeconf &= ~PIPECONF_INTERLACE_MASK;
4736         if (!IS_GEN2(dev) &&
4737             adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4738                 pipeconf |= PIPECONF_INTERLACE_W_FIELD_INDICATION;
4739         else
4740                 pipeconf |= PIPECONF_PROGRESSIVE;
4741
4742         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
4743
4744         /* pipesrc and dspsize control the size that is scaled from,
4745          * which should always be the user's requested size.
4746          */
4747         I915_WRITE(DSPSIZE(plane),
4748                    ((mode->vdisplay - 1) << 16) |
4749                    (mode->hdisplay - 1));
4750         I915_WRITE(DSPPOS(plane), 0);
4751
4752         I915_WRITE(PIPECONF(pipe), pipeconf);
4753         POSTING_READ(PIPECONF(pipe));
4754         intel_enable_pipe(dev_priv, pipe, false);
4755
4756         intel_wait_for_vblank(dev, pipe);
4757
4758         I915_WRITE(DSPCNTR(plane), dspcntr);
4759         POSTING_READ(DSPCNTR(plane));
4760
4761         ret = intel_pipe_set_base(crtc, x, y, fb);
4762
4763         intel_update_watermarks(dev);
4764
4765         return ret;
4766 }
4767
4768 /*
4769  * Initialize reference clocks when the driver loads
4770  */
4771 void ironlake_init_pch_refclk(struct drm_device *dev)
4772 {
4773         struct drm_i915_private *dev_priv = dev->dev_private;
4774         struct drm_mode_config *mode_config = &dev->mode_config;
4775         struct intel_encoder *encoder;
4776         u32 temp;
4777         bool has_lvds = false;
4778         bool has_cpu_edp = false;
4779         bool has_pch_edp = false;
4780         bool has_panel = false;
4781         bool has_ck505 = false;
4782         bool can_ssc = false;
4783
4784         /* We need to take the global config into account */
4785         list_for_each_entry(encoder, &mode_config->encoder_list,
4786                             base.head) {
4787                 switch (encoder->type) {
4788                 case INTEL_OUTPUT_LVDS:
4789                         has_panel = true;
4790                         has_lvds = true;
4791                         break;
4792                 case INTEL_OUTPUT_EDP:
4793                         has_panel = true;
4794                         if (intel_encoder_is_pch_edp(&encoder->base))
4795                                 has_pch_edp = true;
4796                         else
4797                                 has_cpu_edp = true;
4798                         break;
4799                 }
4800         }
4801
4802         if (HAS_PCH_IBX(dev)) {
4803                 has_ck505 = dev_priv->display_clock_mode;
4804                 can_ssc = has_ck505;
4805         } else {
4806                 has_ck505 = false;
4807                 can_ssc = true;
4808         }
4809
4810         DRM_DEBUG_KMS("has_panel %d has_lvds %d has_pch_edp %d has_cpu_edp %d has_ck505 %d\n",
4811                       has_panel, has_lvds, has_pch_edp, has_cpu_edp,
4812                       has_ck505);
4813
4814         /* Ironlake: try to setup display ref clock before DPLL
4815          * enabling. This is only under driver's control after
4816          * PCH B stepping, previous chipset stepping should be
4817          * ignoring this setting.
4818          */
4819         temp = I915_READ(PCH_DREF_CONTROL);
4820         /* Always enable nonspread source */
4821         temp &= ~DREF_NONSPREAD_SOURCE_MASK;
4822
4823         if (has_ck505)
4824                 temp |= DREF_NONSPREAD_CK505_ENABLE;
4825         else
4826                 temp |= DREF_NONSPREAD_SOURCE_ENABLE;
4827
4828         if (has_panel) {
4829                 temp &= ~DREF_SSC_SOURCE_MASK;
4830                 temp |= DREF_SSC_SOURCE_ENABLE;
4831
4832                 /* SSC must be turned on before enabling the CPU output  */
4833                 if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4834                         DRM_DEBUG_KMS("Using SSC on panel\n");
4835                         temp |= DREF_SSC1_ENABLE;
4836                 } else
4837                         temp &= ~DREF_SSC1_ENABLE;
4838
4839                 /* Get SSC going before enabling the outputs */
4840                 I915_WRITE(PCH_DREF_CONTROL, temp);
4841                 POSTING_READ(PCH_DREF_CONTROL);
4842                 udelay(200);
4843
4844                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4845
4846                 /* Enable CPU source on CPU attached eDP */
4847                 if (has_cpu_edp) {
4848                         if (intel_panel_use_ssc(dev_priv) && can_ssc) {
4849                                 DRM_DEBUG_KMS("Using SSC on eDP\n");
4850                                 temp |= DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD;
4851                         }
4852                         else
4853                                 temp |= DREF_CPU_SOURCE_OUTPUT_NONSPREAD;
4854                 } else
4855                         temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4856
4857                 I915_WRITE(PCH_DREF_CONTROL, temp);
4858                 POSTING_READ(PCH_DREF_CONTROL);
4859                 udelay(200);
4860         } else {
4861                 DRM_DEBUG_KMS("Disabling SSC entirely\n");
4862
4863                 temp &= ~DREF_CPU_SOURCE_OUTPUT_MASK;
4864
4865                 /* Turn off CPU output */
4866                 temp |= DREF_CPU_SOURCE_OUTPUT_DISABLE;
4867
4868                 I915_WRITE(PCH_DREF_CONTROL, temp);
4869                 POSTING_READ(PCH_DREF_CONTROL);
4870                 udelay(200);
4871
4872                 /* Turn off the SSC source */
4873                 temp &= ~DREF_SSC_SOURCE_MASK;
4874                 temp |= DREF_SSC_SOURCE_DISABLE;
4875
4876                 /* Turn off SSC1 */
4877                 temp &= ~ DREF_SSC1_ENABLE;
4878
4879                 I915_WRITE(PCH_DREF_CONTROL, temp);
4880                 POSTING_READ(PCH_DREF_CONTROL);
4881                 udelay(200);
4882         }
4883 }
4884
4885 static int ironlake_get_refclk(struct drm_crtc *crtc)
4886 {
4887         struct drm_device *dev = crtc->dev;
4888         struct drm_i915_private *dev_priv = dev->dev_private;
4889         struct intel_encoder *encoder;
4890         struct intel_encoder *edp_encoder = NULL;
4891         int num_connectors = 0;
4892         bool is_lvds = false;
4893
4894         for_each_encoder_on_crtc(dev, crtc, encoder) {
4895                 switch (encoder->type) {
4896                 case INTEL_OUTPUT_LVDS:
4897                         is_lvds = true;
4898                         break;
4899                 case INTEL_OUTPUT_EDP:
4900                         edp_encoder = encoder;
4901                         break;
4902                 }
4903                 num_connectors++;
4904         }
4905
4906         if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2) {
4907                 DRM_DEBUG_KMS("using SSC reference clock of %d MHz\n",
4908                               dev_priv->lvds_ssc_freq);
4909                 return dev_priv->lvds_ssc_freq * 1000;
4910         }
4911
4912         return 120000;
4913 }
4914
4915 static void ironlake_set_pipeconf(struct drm_crtc *crtc,
4916                                   struct drm_display_mode *adjusted_mode,
4917                                   bool dither)
4918 {
4919         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4920         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4921         int pipe = intel_crtc->pipe;
4922         uint32_t val;
4923
4924         val = I915_READ(PIPECONF(pipe));
4925
4926         val &= ~PIPE_BPC_MASK;
4927         switch (intel_crtc->bpp) {
4928         case 18:
4929                 val |= PIPE_6BPC;
4930                 break;
4931         case 24:
4932                 val |= PIPE_8BPC;
4933                 break;
4934         case 30:
4935                 val |= PIPE_10BPC;
4936                 break;
4937         case 36:
4938                 val |= PIPE_12BPC;
4939                 break;
4940         default:
4941                 /* Case prevented by intel_choose_pipe_bpp_dither. */
4942                 BUG();
4943         }
4944
4945         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4946         if (dither)
4947                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4948
4949         val &= ~PIPECONF_INTERLACE_MASK;
4950         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4951                 val |= PIPECONF_INTERLACED_ILK;
4952         else
4953                 val |= PIPECONF_PROGRESSIVE;
4954
4955         I915_WRITE(PIPECONF(pipe), val);
4956         POSTING_READ(PIPECONF(pipe));
4957 }
4958
4959 static void haswell_set_pipeconf(struct drm_crtc *crtc,
4960                                  struct drm_display_mode *adjusted_mode,
4961                                  bool dither)
4962 {
4963         struct drm_i915_private *dev_priv = crtc->dev->dev_private;
4964         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4965         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
4966         uint32_t val;
4967
4968         val = I915_READ(PIPECONF(cpu_transcoder));
4969
4970         val &= ~(PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_MASK);
4971         if (dither)
4972                 val |= (PIPECONF_DITHER_EN | PIPECONF_DITHER_TYPE_SP);
4973
4974         val &= ~PIPECONF_INTERLACE_MASK_HSW;
4975         if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
4976                 val |= PIPECONF_INTERLACED_ILK;
4977         else
4978                 val |= PIPECONF_PROGRESSIVE;
4979
4980         I915_WRITE(PIPECONF(cpu_transcoder), val);
4981         POSTING_READ(PIPECONF(cpu_transcoder));
4982 }
4983
4984 static bool ironlake_compute_clocks(struct drm_crtc *crtc,
4985                                     struct drm_display_mode *adjusted_mode,
4986                                     intel_clock_t *clock,
4987                                     bool *has_reduced_clock,
4988                                     intel_clock_t *reduced_clock)
4989 {
4990         struct drm_device *dev = crtc->dev;
4991         struct drm_i915_private *dev_priv = dev->dev_private;
4992         struct intel_encoder *intel_encoder;
4993         int refclk;
4994         const intel_limit_t *limit;
4995         bool ret, is_sdvo = false, is_tv = false, is_lvds = false;
4996
4997         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
4998                 switch (intel_encoder->type) {
4999                 case INTEL_OUTPUT_LVDS:
5000                         is_lvds = true;
5001                         break;
5002                 case INTEL_OUTPUT_SDVO:
5003                 case INTEL_OUTPUT_HDMI:
5004                         is_sdvo = true;
5005                         if (intel_encoder->needs_tv_clock)
5006                                 is_tv = true;
5007                         break;
5008                 case INTEL_OUTPUT_TVOUT:
5009                         is_tv = true;
5010                         break;
5011                 }
5012         }
5013
5014         refclk = ironlake_get_refclk(crtc);
5015
5016         /*
5017          * Returns a set of divisors for the desired target clock with the given
5018          * refclk, or FALSE.  The returned values represent the clock equation:
5019          * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2.
5020          */
5021         limit = intel_limit(crtc, refclk);
5022         ret = limit->find_pll(limit, crtc, adjusted_mode->clock, refclk, NULL,
5023                               clock);
5024         if (!ret)
5025                 return false;
5026
5027         if (is_lvds && dev_priv->lvds_downclock_avail) {
5028                 /*
5029                  * Ensure we match the reduced clock's P to the target clock.
5030                  * If the clocks don't match, we can't switch the display clock
5031                  * by using the FP0/FP1. In such case we will disable the LVDS
5032                  * downclock feature.
5033                 */
5034                 *has_reduced_clock = limit->find_pll(limit, crtc,
5035                                                      dev_priv->lvds_downclock,
5036                                                      refclk,
5037                                                      clock,
5038                                                      reduced_clock);
5039         }
5040
5041         if (is_sdvo && is_tv)
5042                 i9xx_adjust_sdvo_tv_clock(adjusted_mode, clock);
5043
5044         return true;
5045 }
5046
5047 static void cpt_enable_fdi_bc_bifurcation(struct drm_device *dev)
5048 {
5049         struct drm_i915_private *dev_priv = dev->dev_private;
5050         uint32_t temp;
5051
5052         temp = I915_READ(SOUTH_CHICKEN1);
5053         if (temp & FDI_BC_BIFURCATION_SELECT)
5054                 return;
5055
5056         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_B)) & FDI_RX_ENABLE);
5057         WARN_ON(I915_READ(FDI_RX_CTL(PIPE_C)) & FDI_RX_ENABLE);
5058
5059         temp |= FDI_BC_BIFURCATION_SELECT;
5060         DRM_DEBUG_KMS("enabling fdi C rx\n");
5061         I915_WRITE(SOUTH_CHICKEN1, temp);
5062         POSTING_READ(SOUTH_CHICKEN1);
5063 }
5064
5065 static bool ironlake_check_fdi_lanes(struct intel_crtc *intel_crtc)
5066 {
5067         struct drm_device *dev = intel_crtc->base.dev;
5068         struct drm_i915_private *dev_priv = dev->dev_private;
5069         struct intel_crtc *pipe_B_crtc =
5070                 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[PIPE_B]);
5071
5072         DRM_DEBUG_KMS("checking fdi config on pipe %i, lanes %i\n",
5073                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5074         if (intel_crtc->fdi_lanes > 4) {
5075                 DRM_DEBUG_KMS("invalid fdi lane config on pipe %i: %i lanes\n",
5076                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5077                 /* Clamp lanes to avoid programming the hw with bogus values. */
5078                 intel_crtc->fdi_lanes = 4;
5079
5080                 return false;
5081         }
5082
5083         if (dev_priv->num_pipe == 2)
5084                 return true;
5085
5086         switch (intel_crtc->pipe) {
5087         case PIPE_A:
5088                 return true;
5089         case PIPE_B:
5090                 if (dev_priv->pipe_to_crtc_mapping[PIPE_C]->enabled &&
5091                     intel_crtc->fdi_lanes > 2) {
5092                         DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5093                                       intel_crtc->pipe, intel_crtc->fdi_lanes);
5094                         /* Clamp lanes to avoid programming the hw with bogus values. */
5095                         intel_crtc->fdi_lanes = 2;
5096
5097                         return false;
5098                 }
5099
5100                 if (intel_crtc->fdi_lanes > 2)
5101                         WARN_ON(I915_READ(SOUTH_CHICKEN1) & FDI_BC_BIFURCATION_SELECT);
5102                 else
5103                         cpt_enable_fdi_bc_bifurcation(dev);
5104
5105                 return true;
5106         case PIPE_C:
5107                 if (!pipe_B_crtc->base.enabled || pipe_B_crtc->fdi_lanes <= 2) {
5108                         if (intel_crtc->fdi_lanes > 2) {
5109                                 DRM_DEBUG_KMS("invalid shared fdi lane config on pipe %i: %i lanes\n",
5110                                               intel_crtc->pipe, intel_crtc->fdi_lanes);
5111                                 /* Clamp lanes to avoid programming the hw with bogus values. */
5112                                 intel_crtc->fdi_lanes = 2;
5113
5114                                 return false;
5115                         }
5116                 } else {
5117                         DRM_DEBUG_KMS("fdi link B uses too many lanes to enable link C\n");
5118                         return false;
5119                 }
5120
5121                 cpt_enable_fdi_bc_bifurcation(dev);
5122
5123                 return true;
5124         default:
5125                 BUG();
5126         }
5127 }
5128
5129 static void ironlake_set_m_n(struct drm_crtc *crtc,
5130                              struct drm_display_mode *mode,
5131                              struct drm_display_mode *adjusted_mode)
5132 {
5133         struct drm_device *dev = crtc->dev;
5134         struct drm_i915_private *dev_priv = dev->dev_private;
5135         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5136         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
5137         struct intel_encoder *intel_encoder, *edp_encoder = NULL;
5138         struct fdi_m_n m_n = {0};
5139         int target_clock, pixel_multiplier, lane, link_bw;
5140         bool is_dp = false, is_cpu_edp = false;
5141
5142         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5143                 switch (intel_encoder->type) {
5144                 case INTEL_OUTPUT_DISPLAYPORT:
5145                         is_dp = true;
5146                         break;
5147                 case INTEL_OUTPUT_EDP:
5148                         is_dp = true;
5149                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5150                                 is_cpu_edp = true;
5151                         edp_encoder = intel_encoder;
5152                         break;
5153                 }
5154         }
5155
5156         /* FDI link */
5157         pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5158         lane = 0;
5159         /* CPU eDP doesn't require FDI link, so just set DP M/N
5160            according to current link config */
5161         if (is_cpu_edp) {
5162                 intel_edp_link_config(edp_encoder, &lane, &link_bw);
5163         } else {
5164                 /* FDI is a binary signal running at ~2.7GHz, encoding
5165                  * each output octet as 10 bits. The actual frequency
5166                  * is stored as a divider into a 100MHz clock, and the
5167                  * mode pixel clock is stored in units of 1KHz.
5168                  * Hence the bw of each lane in terms of the mode signal
5169                  * is:
5170                  */
5171                 link_bw = intel_fdi_link_freq(dev) * MHz(100)/KHz(1)/10;
5172         }
5173
5174         /* [e]DP over FDI requires target mode clock instead of link clock. */
5175         if (edp_encoder)
5176                 target_clock = intel_edp_target_clock(edp_encoder, mode);
5177         else if (is_dp)
5178                 target_clock = mode->clock;
5179         else
5180                 target_clock = adjusted_mode->clock;
5181
5182         if (!lane) {
5183                 /*
5184                  * Account for spread spectrum to avoid
5185                  * oversubscribing the link. Max center spread
5186                  * is 2.5%; use 5% for safety's sake.
5187                  */
5188                 u32 bps = target_clock * intel_crtc->bpp * 21 / 20;
5189                 lane = bps / (link_bw * 8) + 1;
5190         }
5191
5192         intel_crtc->fdi_lanes = lane;
5193
5194         if (pixel_multiplier > 1)
5195                 link_bw *= pixel_multiplier;
5196         ironlake_compute_m_n(intel_crtc->bpp, lane, target_clock, link_bw,
5197                              &m_n);
5198
5199         I915_WRITE(PIPE_DATA_M1(cpu_transcoder), TU_SIZE(m_n.tu) | m_n.gmch_m);
5200         I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n);
5201         I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m);
5202         I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n);
5203 }
5204
5205 static uint32_t ironlake_compute_dpll(struct intel_crtc *intel_crtc,
5206                                       struct drm_display_mode *adjusted_mode,
5207                                       intel_clock_t *clock, u32 fp)
5208 {
5209         struct drm_crtc *crtc = &intel_crtc->base;
5210         struct drm_device *dev = crtc->dev;
5211         struct drm_i915_private *dev_priv = dev->dev_private;
5212         struct intel_encoder *intel_encoder;
5213         uint32_t dpll;
5214         int factor, pixel_multiplier, num_connectors = 0;
5215         bool is_lvds = false, is_sdvo = false, is_tv = false;
5216         bool is_dp = false, is_cpu_edp = false;
5217
5218         for_each_encoder_on_crtc(dev, crtc, intel_encoder) {
5219                 switch (intel_encoder->type) {
5220                 case INTEL_OUTPUT_LVDS:
5221                         is_lvds = true;
5222                         break;
5223                 case INTEL_OUTPUT_SDVO:
5224                 case INTEL_OUTPUT_HDMI:
5225                         is_sdvo = true;
5226                         if (intel_encoder->needs_tv_clock)
5227                                 is_tv = true;
5228                         break;
5229                 case INTEL_OUTPUT_TVOUT:
5230                         is_tv = true;
5231                         break;
5232                 case INTEL_OUTPUT_DISPLAYPORT:
5233                         is_dp = true;
5234                         break;
5235                 case INTEL_OUTPUT_EDP:
5236                         is_dp = true;
5237                         if (!intel_encoder_is_pch_edp(&intel_encoder->base))
5238                                 is_cpu_edp = true;
5239                         break;
5240                 }
5241
5242                 num_connectors++;
5243         }
5244
5245         /* Enable autotuning of the PLL clock (if permissible) */
5246         factor = 21;
5247         if (is_lvds) {
5248                 if ((intel_panel_use_ssc(dev_priv) &&
5249                      dev_priv->lvds_ssc_freq == 100) ||
5250                     intel_is_dual_link_lvds(dev))
5251                         factor = 25;
5252         } else if (is_sdvo && is_tv)
5253                 factor = 20;
5254
5255         if (clock->m < factor * clock->n)
5256                 fp |= FP_CB_TUNE;
5257
5258         dpll = 0;
5259
5260         if (is_lvds)
5261                 dpll |= DPLLB_MODE_LVDS;
5262         else
5263                 dpll |= DPLLB_MODE_DAC_SERIAL;
5264         if (is_sdvo) {
5265                 pixel_multiplier = intel_mode_get_pixel_multiplier(adjusted_mode);
5266                 if (pixel_multiplier > 1) {
5267                         dpll |= (pixel_multiplier - 1) << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT;
5268                 }
5269                 dpll |= DPLL_DVO_HIGH_SPEED;
5270         }
5271         if (is_dp && !is_cpu_edp)
5272                 dpll |= DPLL_DVO_HIGH_SPEED;
5273
5274         /* compute bitmask from p1 value */
5275         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT;
5276         /* also FPA1 */
5277         dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT;
5278
5279         switch (clock->p2) {
5280         case 5:
5281                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5;
5282                 break;
5283         case 7:
5284                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7;
5285                 break;
5286         case 10:
5287                 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10;
5288                 break;
5289         case 14:
5290                 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14;
5291                 break;
5292         }
5293
5294         if (is_sdvo && is_tv)
5295                 dpll |= PLL_REF_INPUT_TVCLKINBC;
5296         else if (is_tv)
5297                 /* XXX: just matching BIOS for now */
5298                 /*      dpll |= PLL_REF_INPUT_TVCLKINBC; */
5299                 dpll |= 3;
5300         else if (is_lvds && intel_panel_use_ssc(dev_priv) && num_connectors < 2)
5301                 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN;
5302         else
5303                 dpll |= PLL_REF_INPUT_DREFCLK;
5304
5305         return dpll;
5306 }
5307
5308 static int ironlake_crtc_mode_set(struct drm_crtc *crtc,
5309                                   struct drm_display_mode *mode,
5310                                   struct drm_display_mode *adjusted_mode,
5311                                   int x, int y,
5312                                   struct drm_framebuffer *fb)
5313 {
5314         struct drm_device *dev = crtc->dev;
5315         struct drm_i915_private *dev_priv = dev->dev_private;
5316         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5317         int pipe = intel_crtc->pipe;
5318         int plane = intel_crtc->plane;
5319         int num_connectors = 0;
5320         intel_clock_t clock, reduced_clock;
5321         u32 dpll, fp = 0, fp2 = 0;
5322         bool ok, has_reduced_clock = false;
5323         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5324         struct intel_encoder *encoder;
5325         int ret;
5326         bool dither, fdi_config_ok;
5327
5328         for_each_encoder_on_crtc(dev, crtc, encoder) {
5329                 switch (encoder->type) {
5330                 case INTEL_OUTPUT_LVDS:
5331                         is_lvds = true;
5332                         break;
5333                 case INTEL_OUTPUT_DISPLAYPORT:
5334                         is_dp = true;
5335                         break;
5336                 case INTEL_OUTPUT_EDP:
5337                         is_dp = true;
5338                         if (!intel_encoder_is_pch_edp(&encoder->base))
5339                                 is_cpu_edp = true;
5340                         break;
5341                 }
5342
5343                 num_connectors++;
5344         }
5345
5346         WARN(!(HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)),
5347              "Unexpected PCH type %d\n", INTEL_PCH_TYPE(dev));
5348
5349         ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5350                                      &has_reduced_clock, &reduced_clock);
5351         if (!ok) {
5352                 DRM_ERROR("Couldn't find PLL settings for mode!\n");
5353                 return -EINVAL;
5354         }
5355
5356         /* Ensure that the cursor is valid for the new mode before changing... */
5357         intel_crtc_update_cursor(crtc, true);
5358
5359         /* determine panel color depth */
5360         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5361                                               adjusted_mode);
5362         if (is_lvds && dev_priv->lvds_dither)
5363                 dither = true;
5364
5365         fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5366         if (has_reduced_clock)
5367                 fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5368                         reduced_clock.m2;
5369
5370         dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock, fp);
5371
5372         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5373         drm_mode_debug_printmodeline(mode);
5374
5375         /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */
5376         if (!is_cpu_edp) {
5377                 struct intel_pch_pll *pll;
5378
5379                 pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5380                 if (pll == NULL) {
5381                         DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5382                                          pipe);
5383                         return -EINVAL;
5384                 }
5385         } else
5386                 intel_put_pch_pll(intel_crtc);
5387
5388         if (is_dp && !is_cpu_edp) {
5389                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5390         } else {
5391                 /* For non-DP output, clear any trans DP clock recovery setting.*/
5392                 I915_WRITE(TRANSDATA_M1(pipe), 0);
5393                 I915_WRITE(TRANSDATA_N1(pipe), 0);
5394                 I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5395                 I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5396         }
5397
5398         for_each_encoder_on_crtc(dev, crtc, encoder)
5399                 if (encoder->pre_pll_enable)
5400                         encoder->pre_pll_enable(encoder);
5401
5402         if (intel_crtc->pch_pll) {
5403                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5404
5405                 /* Wait for the clocks to stabilize. */
5406                 POSTING_READ(intel_crtc->pch_pll->pll_reg);
5407                 udelay(150);
5408
5409                 /* The pixel multiplier can only be updated once the
5410                  * DPLL is enabled and the clocks are stable.
5411                  *
5412                  * So write it again.
5413                  */
5414                 I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5415         }
5416
5417         intel_crtc->lowfreq_avail = false;
5418         if (intel_crtc->pch_pll) {
5419                 if (is_lvds && has_reduced_clock && i915_powersave) {
5420                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5421                         intel_crtc->lowfreq_avail = true;
5422                 } else {
5423                         I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5424                 }
5425         }
5426
5427         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5428
5429         /* Note, this also computes intel_crtc->fdi_lanes which is used below in
5430          * ironlake_check_fdi_lanes. */
5431         ironlake_set_m_n(crtc, mode, adjusted_mode);
5432
5433         fdi_config_ok = ironlake_check_fdi_lanes(intel_crtc);
5434
5435         if (is_cpu_edp)
5436                 ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5437
5438         ironlake_set_pipeconf(crtc, adjusted_mode, dither);
5439
5440         intel_wait_for_vblank(dev, pipe);
5441
5442         /* Set up the display plane register */
5443         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5444         POSTING_READ(DSPCNTR(plane));
5445
5446         ret = intel_pipe_set_base(crtc, x, y, fb);
5447
5448         intel_update_watermarks(dev);
5449
5450         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5451
5452         return fdi_config_ok ? ret : -EINVAL;
5453 }
5454
5455 static int haswell_crtc_mode_set(struct drm_crtc *crtc,
5456                                  struct drm_display_mode *mode,
5457                                  struct drm_display_mode *adjusted_mode,
5458                                  int x, int y,
5459                                  struct drm_framebuffer *fb)
5460 {
5461         struct drm_device *dev = crtc->dev;
5462         struct drm_i915_private *dev_priv = dev->dev_private;
5463         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5464         int pipe = intel_crtc->pipe;
5465         int plane = intel_crtc->plane;
5466         int num_connectors = 0;
5467         intel_clock_t clock, reduced_clock;
5468         u32 dpll = 0, fp = 0, fp2 = 0;
5469         bool ok, has_reduced_clock = false;
5470         bool is_lvds = false, is_dp = false, is_cpu_edp = false;
5471         struct intel_encoder *encoder;
5472         u32 temp;
5473         int ret;
5474         bool dither;
5475
5476         for_each_encoder_on_crtc(dev, crtc, encoder) {
5477                 switch (encoder->type) {
5478                 case INTEL_OUTPUT_LVDS:
5479                         is_lvds = true;
5480                         break;
5481                 case INTEL_OUTPUT_DISPLAYPORT:
5482                         is_dp = true;
5483                         break;
5484                 case INTEL_OUTPUT_EDP:
5485                         is_dp = true;
5486                         if (!intel_encoder_is_pch_edp(&encoder->base))
5487                                 is_cpu_edp = true;
5488                         break;
5489                 }
5490
5491                 num_connectors++;
5492         }
5493
5494         if (is_cpu_edp)
5495                 intel_crtc->cpu_transcoder = TRANSCODER_EDP;
5496         else
5497                 intel_crtc->cpu_transcoder = pipe;
5498
5499         /* We are not sure yet this won't happen. */
5500         WARN(!HAS_PCH_LPT(dev), "Unexpected PCH type %d\n",
5501              INTEL_PCH_TYPE(dev));
5502
5503         WARN(num_connectors != 1, "%d connectors attached to pipe %c\n",
5504              num_connectors, pipe_name(pipe));
5505
5506         WARN_ON(I915_READ(PIPECONF(intel_crtc->cpu_transcoder)) &
5507                 (PIPECONF_ENABLE | I965_PIPECONF_ACTIVE));
5508
5509         WARN_ON(I915_READ(DSPCNTR(plane)) & DISPLAY_PLANE_ENABLE);
5510
5511         if (!intel_ddi_pll_mode_set(crtc, adjusted_mode->clock))
5512                 return -EINVAL;
5513
5514         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5515                 ok = ironlake_compute_clocks(crtc, adjusted_mode, &clock,
5516                                              &has_reduced_clock,
5517                                              &reduced_clock);
5518                 if (!ok) {
5519                         DRM_ERROR("Couldn't find PLL settings for mode!\n");
5520                         return -EINVAL;
5521                 }
5522         }
5523
5524         /* Ensure that the cursor is valid for the new mode before changing... */
5525         intel_crtc_update_cursor(crtc, true);
5526
5527         /* determine panel color depth */
5528         dither = intel_choose_pipe_bpp_dither(crtc, fb, &intel_crtc->bpp,
5529                                               adjusted_mode);
5530         if (is_lvds && dev_priv->lvds_dither)
5531                 dither = true;
5532
5533         DRM_DEBUG_KMS("Mode for pipe %d:\n", pipe);
5534         drm_mode_debug_printmodeline(mode);
5535
5536         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5537                 fp = clock.n << 16 | clock.m1 << 8 | clock.m2;
5538                 if (has_reduced_clock)
5539                         fp2 = reduced_clock.n << 16 | reduced_clock.m1 << 8 |
5540                               reduced_clock.m2;
5541
5542                 dpll = ironlake_compute_dpll(intel_crtc, adjusted_mode, &clock,
5543                                              fp);
5544
5545                 /* CPU eDP is the only output that doesn't need a PCH PLL of its
5546                  * own on pre-Haswell/LPT generation */
5547                 if (!is_cpu_edp) {
5548                         struct intel_pch_pll *pll;
5549
5550                         pll = intel_get_pch_pll(intel_crtc, dpll, fp);
5551                         if (pll == NULL) {
5552                                 DRM_DEBUG_DRIVER("failed to find PLL for pipe %d\n",
5553                                                  pipe);
5554                                 return -EINVAL;
5555                         }
5556                 } else
5557                         intel_put_pch_pll(intel_crtc);
5558
5559                 /* The LVDS pin pair needs to be on before the DPLLs are
5560                  * enabled.  This is an exception to the general rule that
5561                  * mode_set doesn't turn things on.
5562                  */
5563                 if (is_lvds) {
5564                         temp = I915_READ(PCH_LVDS);
5565                         temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
5566                         if (HAS_PCH_CPT(dev)) {
5567                                 temp &= ~PORT_TRANS_SEL_MASK;
5568                                 temp |= PORT_TRANS_SEL_CPT(pipe);
5569                         } else {
5570                                 if (pipe == 1)
5571                                         temp |= LVDS_PIPEB_SELECT;
5572                                 else
5573                                         temp &= ~LVDS_PIPEB_SELECT;
5574                         }
5575
5576                         /* set the corresponsding LVDS_BORDER bit */
5577                         temp |= dev_priv->lvds_border_bits;
5578                         /* Set the B0-B3 data pairs corresponding to whether
5579                          * we're going to set the DPLLs for dual-channel mode or
5580                          * not.
5581                          */
5582                         if (clock.p2 == 7)
5583                                 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
5584                         else
5585                                 temp &= ~(LVDS_B0B3_POWER_UP |
5586                                           LVDS_CLKB_POWER_UP);
5587
5588                         /* It would be nice to set 24 vs 18-bit mode
5589                          * (LVDS_A3_POWER_UP) appropriately here, but we need to
5590                          * look more thoroughly into how panels behave in the
5591                          * two modes.
5592                          */
5593                         temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
5594                         if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
5595                                 temp |= LVDS_HSYNC_POLARITY;
5596                         if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
5597                                 temp |= LVDS_VSYNC_POLARITY;
5598                         I915_WRITE(PCH_LVDS, temp);
5599                 }
5600         }
5601
5602         if (is_dp && !is_cpu_edp) {
5603                 intel_dp_set_m_n(crtc, mode, adjusted_mode);
5604         } else {
5605                 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5606                         /* For non-DP output, clear any trans DP clock recovery
5607                          * setting.*/
5608                         I915_WRITE(TRANSDATA_M1(pipe), 0);
5609                         I915_WRITE(TRANSDATA_N1(pipe), 0);
5610                         I915_WRITE(TRANSDPLINK_M1(pipe), 0);
5611                         I915_WRITE(TRANSDPLINK_N1(pipe), 0);
5612                 }
5613         }
5614
5615         intel_crtc->lowfreq_avail = false;
5616         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) {
5617                 if (intel_crtc->pch_pll) {
5618                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5619
5620                         /* Wait for the clocks to stabilize. */
5621                         POSTING_READ(intel_crtc->pch_pll->pll_reg);
5622                         udelay(150);
5623
5624                         /* The pixel multiplier can only be updated once the
5625                          * DPLL is enabled and the clocks are stable.
5626                          *
5627                          * So write it again.
5628                          */
5629                         I915_WRITE(intel_crtc->pch_pll->pll_reg, dpll);
5630                 }
5631
5632                 if (intel_crtc->pch_pll) {
5633                         if (is_lvds && has_reduced_clock && i915_powersave) {
5634                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp2);
5635                                 intel_crtc->lowfreq_avail = true;
5636                         } else {
5637                                 I915_WRITE(intel_crtc->pch_pll->fp1_reg, fp);
5638                         }
5639                 }
5640         }
5641
5642         intel_set_pipe_timings(intel_crtc, mode, adjusted_mode);
5643
5644         if (!is_dp || is_cpu_edp)
5645                 ironlake_set_m_n(crtc, mode, adjusted_mode);
5646
5647         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
5648                 if (is_cpu_edp)
5649                         ironlake_set_pll_edp(crtc, adjusted_mode->clock);
5650
5651         haswell_set_pipeconf(crtc, adjusted_mode, dither);
5652
5653         /* Set up the display plane register */
5654         I915_WRITE(DSPCNTR(plane), DISPPLANE_GAMMA_ENABLE);
5655         POSTING_READ(DSPCNTR(plane));
5656
5657         ret = intel_pipe_set_base(crtc, x, y, fb);
5658
5659         intel_update_watermarks(dev);
5660
5661         intel_update_linetime_watermarks(dev, pipe, adjusted_mode);
5662
5663         return ret;
5664 }
5665
5666 static int intel_crtc_mode_set(struct drm_crtc *crtc,
5667                                struct drm_display_mode *mode,
5668                                struct drm_display_mode *adjusted_mode,
5669                                int x, int y,
5670                                struct drm_framebuffer *fb)
5671 {
5672         struct drm_device *dev = crtc->dev;
5673         struct drm_i915_private *dev_priv = dev->dev_private;
5674         struct drm_encoder_helper_funcs *encoder_funcs;
5675         struct intel_encoder *encoder;
5676         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5677         int pipe = intel_crtc->pipe;
5678         int ret;
5679
5680         drm_vblank_pre_modeset(dev, pipe);
5681
5682         ret = dev_priv->display.crtc_mode_set(crtc, mode, adjusted_mode,
5683                                               x, y, fb);
5684         drm_vblank_post_modeset(dev, pipe);
5685
5686         if (ret != 0)
5687                 return ret;
5688
5689         for_each_encoder_on_crtc(dev, crtc, encoder) {
5690                 DRM_DEBUG_KMS("[ENCODER:%d:%s] set [MODE:%d:%s]\n",
5691                         encoder->base.base.id,
5692                         drm_get_encoder_name(&encoder->base),
5693                         mode->base.id, mode->name);
5694                 encoder_funcs = encoder->base.helper_private;
5695                 encoder_funcs->mode_set(&encoder->base, mode, adjusted_mode);
5696         }
5697
5698         return 0;
5699 }
5700
5701 static bool intel_eld_uptodate(struct drm_connector *connector,
5702                                int reg_eldv, uint32_t bits_eldv,
5703                                int reg_elda, uint32_t bits_elda,
5704                                int reg_edid)
5705 {
5706         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5707         uint8_t *eld = connector->eld;
5708         uint32_t i;
5709
5710         i = I915_READ(reg_eldv);
5711         i &= bits_eldv;
5712
5713         if (!eld[0])
5714                 return !i;
5715
5716         if (!i)
5717                 return false;
5718
5719         i = I915_READ(reg_elda);
5720         i &= ~bits_elda;
5721         I915_WRITE(reg_elda, i);
5722
5723         for (i = 0; i < eld[2]; i++)
5724                 if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
5725                         return false;
5726
5727         return true;
5728 }
5729
5730 static void g4x_write_eld(struct drm_connector *connector,
5731                           struct drm_crtc *crtc)
5732 {
5733         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5734         uint8_t *eld = connector->eld;
5735         uint32_t eldv;
5736         uint32_t len;
5737         uint32_t i;
5738
5739         i = I915_READ(G4X_AUD_VID_DID);
5740
5741         if (i == INTEL_AUDIO_DEVBLC || i == INTEL_AUDIO_DEVCL)
5742                 eldv = G4X_ELDV_DEVCL_DEVBLC;
5743         else
5744                 eldv = G4X_ELDV_DEVCTG;
5745
5746         if (intel_eld_uptodate(connector,
5747                                G4X_AUD_CNTL_ST, eldv,
5748                                G4X_AUD_CNTL_ST, G4X_ELD_ADDR,
5749                                G4X_HDMIW_HDMIEDID))
5750                 return;
5751
5752         i = I915_READ(G4X_AUD_CNTL_ST);
5753         i &= ~(eldv | G4X_ELD_ADDR);
5754         len = (i >> 9) & 0x1f;          /* ELD buffer size */
5755         I915_WRITE(G4X_AUD_CNTL_ST, i);
5756
5757         if (!eld[0])
5758                 return;
5759
5760         len = min_t(uint8_t, eld[2], len);
5761         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5762         for (i = 0; i < len; i++)
5763                 I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
5764
5765         i = I915_READ(G4X_AUD_CNTL_ST);
5766         i |= eldv;
5767         I915_WRITE(G4X_AUD_CNTL_ST, i);
5768 }
5769
5770 static void haswell_write_eld(struct drm_connector *connector,
5771                                      struct drm_crtc *crtc)
5772 {
5773         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5774         uint8_t *eld = connector->eld;
5775         struct drm_device *dev = crtc->dev;
5776         uint32_t eldv;
5777         uint32_t i;
5778         int len;
5779         int pipe = to_intel_crtc(crtc)->pipe;
5780         int tmp;
5781
5782         int hdmiw_hdmiedid = HSW_AUD_EDID_DATA(pipe);
5783         int aud_cntl_st = HSW_AUD_DIP_ELD_CTRL(pipe);
5784         int aud_config = HSW_AUD_CFG(pipe);
5785         int aud_cntrl_st2 = HSW_AUD_PIN_ELD_CP_VLD;
5786
5787
5788         DRM_DEBUG_DRIVER("HDMI: Haswell Audio initialize....\n");
5789
5790         /* Audio output enable */
5791         DRM_DEBUG_DRIVER("HDMI audio: enable codec\n");
5792         tmp = I915_READ(aud_cntrl_st2);
5793         tmp |= (AUDIO_OUTPUT_ENABLE_A << (pipe * 4));
5794         I915_WRITE(aud_cntrl_st2, tmp);
5795
5796         /* Wait for 1 vertical blank */
5797         intel_wait_for_vblank(dev, pipe);
5798
5799         /* Set ELD valid state */
5800         tmp = I915_READ(aud_cntrl_st2);
5801         DRM_DEBUG_DRIVER("HDMI audio: pin eld vld status=0x%8x\n", tmp);
5802         tmp |= (AUDIO_ELD_VALID_A << (pipe * 4));
5803         I915_WRITE(aud_cntrl_st2, tmp);
5804         tmp = I915_READ(aud_cntrl_st2);
5805         DRM_DEBUG_DRIVER("HDMI audio: eld vld status=0x%8x\n", tmp);
5806
5807         /* Enable HDMI mode */
5808         tmp = I915_READ(aud_config);
5809         DRM_DEBUG_DRIVER("HDMI audio: audio conf: 0x%8x\n", tmp);
5810         /* clear N_programing_enable and N_value_index */
5811         tmp &= ~(AUD_CONFIG_N_VALUE_INDEX | AUD_CONFIG_N_PROG_ENABLE);
5812         I915_WRITE(aud_config, tmp);
5813
5814         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5815
5816         eldv = AUDIO_ELD_VALID_A << (pipe * 4);
5817
5818         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5819                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5820                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5821                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5822         } else
5823                 I915_WRITE(aud_config, 0);
5824
5825         if (intel_eld_uptodate(connector,
5826                                aud_cntrl_st2, eldv,
5827                                aud_cntl_st, IBX_ELD_ADDRESS,
5828                                hdmiw_hdmiedid))
5829                 return;
5830
5831         i = I915_READ(aud_cntrl_st2);
5832         i &= ~eldv;
5833         I915_WRITE(aud_cntrl_st2, i);
5834
5835         if (!eld[0])
5836                 return;
5837
5838         i = I915_READ(aud_cntl_st);
5839         i &= ~IBX_ELD_ADDRESS;
5840         I915_WRITE(aud_cntl_st, i);
5841         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5842         DRM_DEBUG_DRIVER("port num:%d\n", i);
5843
5844         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5845         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5846         for (i = 0; i < len; i++)
5847                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5848
5849         i = I915_READ(aud_cntrl_st2);
5850         i |= eldv;
5851         I915_WRITE(aud_cntrl_st2, i);
5852
5853 }
5854
5855 static void ironlake_write_eld(struct drm_connector *connector,
5856                                      struct drm_crtc *crtc)
5857 {
5858         struct drm_i915_private *dev_priv = connector->dev->dev_private;
5859         uint8_t *eld = connector->eld;
5860         uint32_t eldv;
5861         uint32_t i;
5862         int len;
5863         int hdmiw_hdmiedid;
5864         int aud_config;
5865         int aud_cntl_st;
5866         int aud_cntrl_st2;
5867         int pipe = to_intel_crtc(crtc)->pipe;
5868
5869         if (HAS_PCH_IBX(connector->dev)) {
5870                 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe);
5871                 aud_config = IBX_AUD_CFG(pipe);
5872                 aud_cntl_st = IBX_AUD_CNTL_ST(pipe);
5873                 aud_cntrl_st2 = IBX_AUD_CNTL_ST2;
5874         } else {
5875                 hdmiw_hdmiedid = CPT_HDMIW_HDMIEDID(pipe);
5876                 aud_config = CPT_AUD_CFG(pipe);
5877                 aud_cntl_st = CPT_AUD_CNTL_ST(pipe);
5878                 aud_cntrl_st2 = CPT_AUD_CNTRL_ST2;
5879         }
5880
5881         DRM_DEBUG_DRIVER("ELD on pipe %c\n", pipe_name(pipe));
5882
5883         i = I915_READ(aud_cntl_st);
5884         i = (i >> 29) & DIP_PORT_SEL_MASK;              /* DIP_Port_Select, 0x1 = PortB */
5885         if (!i) {
5886                 DRM_DEBUG_DRIVER("Audio directed to unknown port\n");
5887                 /* operate blindly on all ports */
5888                 eldv = IBX_ELD_VALIDB;
5889                 eldv |= IBX_ELD_VALIDB << 4;
5890                 eldv |= IBX_ELD_VALIDB << 8;
5891         } else {
5892                 DRM_DEBUG_DRIVER("ELD on port %c\n", 'A' + i);
5893                 eldv = IBX_ELD_VALIDB << ((i - 1) * 4);
5894         }
5895
5896         if (intel_pipe_has_type(crtc, INTEL_OUTPUT_DISPLAYPORT)) {
5897                 DRM_DEBUG_DRIVER("ELD: DisplayPort detected\n");
5898                 eld[5] |= (1 << 2);     /* Conn_Type, 0x1 = DisplayPort */
5899                 I915_WRITE(aud_config, AUD_CONFIG_N_VALUE_INDEX); /* 0x1 = DP */
5900         } else
5901                 I915_WRITE(aud_config, 0);
5902
5903         if (intel_eld_uptodate(connector,
5904                                aud_cntrl_st2, eldv,
5905                                aud_cntl_st, IBX_ELD_ADDRESS,
5906                                hdmiw_hdmiedid))
5907                 return;
5908
5909         i = I915_READ(aud_cntrl_st2);
5910         i &= ~eldv;
5911         I915_WRITE(aud_cntrl_st2, i);
5912
5913         if (!eld[0])
5914                 return;
5915
5916         i = I915_READ(aud_cntl_st);
5917         i &= ~IBX_ELD_ADDRESS;
5918         I915_WRITE(aud_cntl_st, i);
5919
5920         len = min_t(uint8_t, eld[2], 21);       /* 84 bytes of hw ELD buffer */
5921         DRM_DEBUG_DRIVER("ELD size %d\n", len);
5922         for (i = 0; i < len; i++)
5923                 I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
5924
5925         i = I915_READ(aud_cntrl_st2);
5926         i |= eldv;
5927         I915_WRITE(aud_cntrl_st2, i);
5928 }
5929
5930 void intel_write_eld(struct drm_encoder *encoder,
5931                      struct drm_display_mode *mode)
5932 {
5933         struct drm_crtc *crtc = encoder->crtc;
5934         struct drm_connector *connector;
5935         struct drm_device *dev = encoder->dev;
5936         struct drm_i915_private *dev_priv = dev->dev_private;
5937
5938         connector = drm_select_eld(encoder, mode);
5939         if (!connector)
5940                 return;
5941
5942         DRM_DEBUG_DRIVER("ELD on [CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
5943                          connector->base.id,
5944                          drm_get_connector_name(connector),
5945                          connector->encoder->base.id,
5946                          drm_get_encoder_name(connector->encoder));
5947
5948         connector->eld[6] = drm_av_sync_delay(connector, mode) / 2;
5949
5950         if (dev_priv->display.write_eld)
5951                 dev_priv->display.write_eld(connector, crtc);
5952 }
5953
5954 /** Loads the palette/gamma unit for the CRTC with the prepared values */
5955 void intel_crtc_load_lut(struct drm_crtc *crtc)
5956 {
5957         struct drm_device *dev = crtc->dev;
5958         struct drm_i915_private *dev_priv = dev->dev_private;
5959         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5960         int palreg = PALETTE(intel_crtc->pipe);
5961         int i;
5962
5963         /* The clocks have to be on to load the palette. */
5964         if (!crtc->enabled || !intel_crtc->active)
5965                 return;
5966
5967         /* use legacy palette for Ironlake */
5968         if (HAS_PCH_SPLIT(dev))
5969                 palreg = LGC_PALETTE(intel_crtc->pipe);
5970
5971         for (i = 0; i < 256; i++) {
5972                 I915_WRITE(palreg + 4 * i,
5973                            (intel_crtc->lut_r[i] << 16) |
5974                            (intel_crtc->lut_g[i] << 8) |
5975                            intel_crtc->lut_b[i]);
5976         }
5977 }
5978
5979 static void i845_update_cursor(struct drm_crtc *crtc, u32 base)
5980 {
5981         struct drm_device *dev = crtc->dev;
5982         struct drm_i915_private *dev_priv = dev->dev_private;
5983         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
5984         bool visible = base != 0;
5985         u32 cntl;
5986
5987         if (intel_crtc->cursor_visible == visible)
5988                 return;
5989
5990         cntl = I915_READ(_CURACNTR);
5991         if (visible) {
5992                 /* On these chipsets we can only modify the base whilst
5993                  * the cursor is disabled.
5994                  */
5995                 I915_WRITE(_CURABASE, base);
5996
5997                 cntl &= ~(CURSOR_FORMAT_MASK);
5998                 /* XXX width must be 64, stride 256 => 0x00 << 28 */
5999                 cntl |= CURSOR_ENABLE |
6000                         CURSOR_GAMMA_ENABLE |
6001                         CURSOR_FORMAT_ARGB;
6002         } else
6003                 cntl &= ~(CURSOR_ENABLE | CURSOR_GAMMA_ENABLE);
6004         I915_WRITE(_CURACNTR, cntl);
6005
6006         intel_crtc->cursor_visible = visible;
6007 }
6008
6009 static void i9xx_update_cursor(struct drm_crtc *crtc, u32 base)
6010 {
6011         struct drm_device *dev = crtc->dev;
6012         struct drm_i915_private *dev_priv = dev->dev_private;
6013         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6014         int pipe = intel_crtc->pipe;
6015         bool visible = base != 0;
6016
6017         if (intel_crtc->cursor_visible != visible) {
6018                 uint32_t cntl = I915_READ(CURCNTR(pipe));
6019                 if (base) {
6020                         cntl &= ~(CURSOR_MODE | MCURSOR_PIPE_SELECT);
6021                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6022                         cntl |= pipe << 28; /* Connect to correct pipe */
6023                 } else {
6024                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6025                         cntl |= CURSOR_MODE_DISABLE;
6026                 }
6027                 I915_WRITE(CURCNTR(pipe), cntl);
6028
6029                 intel_crtc->cursor_visible = visible;
6030         }
6031         /* and commit changes on next vblank */
6032         I915_WRITE(CURBASE(pipe), base);
6033 }
6034
6035 static void ivb_update_cursor(struct drm_crtc *crtc, u32 base)
6036 {
6037         struct drm_device *dev = crtc->dev;
6038         struct drm_i915_private *dev_priv = dev->dev_private;
6039         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6040         int pipe = intel_crtc->pipe;
6041         bool visible = base != 0;
6042
6043         if (intel_crtc->cursor_visible != visible) {
6044                 uint32_t cntl = I915_READ(CURCNTR_IVB(pipe));
6045                 if (base) {
6046                         cntl &= ~CURSOR_MODE;
6047                         cntl |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
6048                 } else {
6049                         cntl &= ~(CURSOR_MODE | MCURSOR_GAMMA_ENABLE);
6050                         cntl |= CURSOR_MODE_DISABLE;
6051                 }
6052                 I915_WRITE(CURCNTR_IVB(pipe), cntl);
6053
6054                 intel_crtc->cursor_visible = visible;
6055         }
6056         /* and commit changes on next vblank */
6057         I915_WRITE(CURBASE_IVB(pipe), base);
6058 }
6059
6060 /* If no-part of the cursor is visible on the framebuffer, then the GPU may hang... */
6061 static void intel_crtc_update_cursor(struct drm_crtc *crtc,
6062                                      bool on)
6063 {
6064         struct drm_device *dev = crtc->dev;
6065         struct drm_i915_private *dev_priv = dev->dev_private;
6066         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6067         int pipe = intel_crtc->pipe;
6068         int x = intel_crtc->cursor_x;
6069         int y = intel_crtc->cursor_y;
6070         u32 base, pos;
6071         bool visible;
6072
6073         pos = 0;
6074
6075         if (on && crtc->enabled && crtc->fb) {
6076                 base = intel_crtc->cursor_addr;
6077                 if (x > (int) crtc->fb->width)
6078                         base = 0;
6079
6080                 if (y > (int) crtc->fb->height)
6081                         base = 0;
6082         } else
6083                 base = 0;
6084
6085         if (x < 0) {
6086                 if (x + intel_crtc->cursor_width < 0)
6087                         base = 0;
6088
6089                 pos |= CURSOR_POS_SIGN << CURSOR_X_SHIFT;
6090                 x = -x;
6091         }
6092         pos |= x << CURSOR_X_SHIFT;
6093
6094         if (y < 0) {
6095                 if (y + intel_crtc->cursor_height < 0)
6096                         base = 0;
6097
6098                 pos |= CURSOR_POS_SIGN << CURSOR_Y_SHIFT;
6099                 y = -y;
6100         }
6101         pos |= y << CURSOR_Y_SHIFT;
6102
6103         visible = base != 0;
6104         if (!visible && !intel_crtc->cursor_visible)
6105                 return;
6106
6107         if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
6108                 I915_WRITE(CURPOS_IVB(pipe), pos);
6109                 ivb_update_cursor(crtc, base);
6110         } else {
6111                 I915_WRITE(CURPOS(pipe), pos);
6112                 if (IS_845G(dev) || IS_I865G(dev))
6113                         i845_update_cursor(crtc, base);
6114                 else
6115                         i9xx_update_cursor(crtc, base);
6116         }
6117 }
6118
6119 static int intel_crtc_cursor_set(struct drm_crtc *crtc,
6120                                  struct drm_file *file,
6121                                  uint32_t handle,
6122                                  uint32_t width, uint32_t height)
6123 {
6124         struct drm_device *dev = crtc->dev;
6125         struct drm_i915_private *dev_priv = dev->dev_private;
6126         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6127         struct drm_i915_gem_object *obj;
6128         uint32_t addr;
6129         int ret;
6130
6131         /* if we want to turn off the cursor ignore width and height */
6132         if (!handle) {
6133                 DRM_DEBUG_KMS("cursor off\n");
6134                 addr = 0;
6135                 obj = NULL;
6136                 mutex_lock(&dev->struct_mutex);
6137                 goto finish;
6138         }
6139
6140         /* Currently we only support 64x64 cursors */
6141         if (width != 64 || height != 64) {
6142                 DRM_ERROR("we currently only support 64x64 cursors\n");
6143                 return -EINVAL;
6144         }
6145
6146         obj = to_intel_bo(drm_gem_object_lookup(dev, file, handle));
6147         if (&obj->base == NULL)
6148                 return -ENOENT;
6149
6150         if (obj->base.size < width * height * 4) {
6151                 DRM_ERROR("buffer is to small\n");
6152                 ret = -ENOMEM;
6153                 goto fail;
6154         }
6155
6156         /* we only need to pin inside GTT if cursor is non-phy */
6157         mutex_lock(&dev->struct_mutex);
6158         if (!dev_priv->info->cursor_needs_physical) {
6159                 if (obj->tiling_mode) {
6160                         DRM_ERROR("cursor cannot be tiled\n");
6161                         ret = -EINVAL;
6162                         goto fail_locked;
6163                 }
6164
6165                 ret = i915_gem_object_pin_to_display_plane(obj, 0, NULL);
6166                 if (ret) {
6167                         DRM_ERROR("failed to move cursor bo into the GTT\n");
6168                         goto fail_locked;
6169                 }
6170
6171                 ret = i915_gem_object_put_fence(obj);
6172                 if (ret) {
6173                         DRM_ERROR("failed to release fence for cursor");
6174                         goto fail_unpin;
6175                 }
6176
6177                 addr = obj->gtt_offset;
6178         } else {
6179                 int align = IS_I830(dev) ? 16 * 1024 : 256;
6180                 ret = i915_gem_attach_phys_object(dev, obj,
6181                                                   (intel_crtc->pipe == 0) ? I915_GEM_PHYS_CURSOR_0 : I915_GEM_PHYS_CURSOR_1,
6182                                                   align);
6183                 if (ret) {
6184                         DRM_ERROR("failed to attach phys object\n");
6185                         goto fail_locked;
6186                 }
6187                 addr = obj->phys_obj->handle->busaddr;
6188         }
6189
6190         if (IS_GEN2(dev))
6191                 I915_WRITE(CURSIZE, (height << 12) | width);
6192
6193  finish:
6194         if (intel_crtc->cursor_bo) {
6195                 if (dev_priv->info->cursor_needs_physical) {
6196                         if (intel_crtc->cursor_bo != obj)
6197                                 i915_gem_detach_phys_object(dev, intel_crtc->cursor_bo);
6198                 } else
6199                         i915_gem_object_unpin(intel_crtc->cursor_bo);
6200                 drm_gem_object_unreference(&intel_crtc->cursor_bo->base);
6201         }
6202
6203         mutex_unlock(&dev->struct_mutex);
6204
6205         intel_crtc->cursor_addr = addr;
6206         intel_crtc->cursor_bo = obj;
6207         intel_crtc->cursor_width = width;
6208         intel_crtc->cursor_height = height;
6209
6210         intel_crtc_update_cursor(crtc, true);
6211
6212         return 0;
6213 fail_unpin:
6214         i915_gem_object_unpin(obj);
6215 fail_locked:
6216         mutex_unlock(&dev->struct_mutex);
6217 fail:
6218         drm_gem_object_unreference_unlocked(&obj->base);
6219         return ret;
6220 }
6221
6222 static int intel_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
6223 {
6224         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6225
6226         intel_crtc->cursor_x = x;
6227         intel_crtc->cursor_y = y;
6228
6229         intel_crtc_update_cursor(crtc, true);
6230
6231         return 0;
6232 }
6233
6234 /** Sets the color ramps on behalf of RandR */
6235 void intel_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
6236                                  u16 blue, int regno)
6237 {
6238         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6239
6240         intel_crtc->lut_r[regno] = red >> 8;
6241         intel_crtc->lut_g[regno] = green >> 8;
6242         intel_crtc->lut_b[regno] = blue >> 8;
6243 }
6244
6245 void intel_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
6246                              u16 *blue, int regno)
6247 {
6248         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6249
6250         *red = intel_crtc->lut_r[regno] << 8;
6251         *green = intel_crtc->lut_g[regno] << 8;
6252         *blue = intel_crtc->lut_b[regno] << 8;
6253 }
6254
6255 static void intel_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green,
6256                                  u16 *blue, uint32_t start, uint32_t size)
6257 {
6258         int end = (start + size > 256) ? 256 : start + size, i;
6259         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6260
6261         for (i = start; i < end; i++) {
6262                 intel_crtc->lut_r[i] = red[i] >> 8;
6263                 intel_crtc->lut_g[i] = green[i] >> 8;
6264                 intel_crtc->lut_b[i] = blue[i] >> 8;
6265         }
6266
6267         intel_crtc_load_lut(crtc);
6268 }
6269
6270 /**
6271  * Get a pipe with a simple mode set on it for doing load-based monitor
6272  * detection.
6273  *
6274  * It will be up to the load-detect code to adjust the pipe as appropriate for
6275  * its requirements.  The pipe will be connected to no other encoders.
6276  *
6277  * Currently this code will only succeed if there is a pipe with no encoders
6278  * configured for it.  In the future, it could choose to temporarily disable
6279  * some outputs to free up a pipe for its use.
6280  *
6281  * \return crtc, or NULL if no pipes are available.
6282  */
6283
6284 /* VESA 640x480x72Hz mode to set on the pipe */
6285 static struct drm_display_mode load_detect_mode = {
6286         DRM_MODE("640x480", DRM_MODE_TYPE_DEFAULT, 31500, 640, 664,
6287                  704, 832, 0, 480, 489, 491, 520, 0, DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC),
6288 };
6289
6290 static struct drm_framebuffer *
6291 intel_framebuffer_create(struct drm_device *dev,
6292                          struct drm_mode_fb_cmd2 *mode_cmd,
6293                          struct drm_i915_gem_object *obj)
6294 {
6295         struct intel_framebuffer *intel_fb;
6296         int ret;
6297
6298         intel_fb = kzalloc(sizeof(*intel_fb), GFP_KERNEL);
6299         if (!intel_fb) {
6300                 drm_gem_object_unreference_unlocked(&obj->base);
6301                 return ERR_PTR(-ENOMEM);
6302         }
6303
6304         ret = intel_framebuffer_init(dev, intel_fb, mode_cmd, obj);
6305         if (ret) {
6306                 drm_gem_object_unreference_unlocked(&obj->base);
6307                 kfree(intel_fb);
6308                 return ERR_PTR(ret);
6309         }
6310
6311         return &intel_fb->base;
6312 }
6313
6314 static u32
6315 intel_framebuffer_pitch_for_width(int width, int bpp)
6316 {
6317         u32 pitch = DIV_ROUND_UP(width * bpp, 8);
6318         return ALIGN(pitch, 64);
6319 }
6320
6321 static u32
6322 intel_framebuffer_size_for_mode(struct drm_display_mode *mode, int bpp)
6323 {
6324         u32 pitch = intel_framebuffer_pitch_for_width(mode->hdisplay, bpp);
6325         return ALIGN(pitch * mode->vdisplay, PAGE_SIZE);
6326 }
6327
6328 static struct drm_framebuffer *
6329 intel_framebuffer_create_for_mode(struct drm_device *dev,
6330                                   struct drm_display_mode *mode,
6331                                   int depth, int bpp)
6332 {
6333         struct drm_i915_gem_object *obj;
6334         struct drm_mode_fb_cmd2 mode_cmd = { 0 };
6335
6336         obj = i915_gem_alloc_object(dev,
6337                                     intel_framebuffer_size_for_mode(mode, bpp));
6338         if (obj == NULL)
6339                 return ERR_PTR(-ENOMEM);
6340
6341         mode_cmd.width = mode->hdisplay;
6342         mode_cmd.height = mode->vdisplay;
6343         mode_cmd.pitches[0] = intel_framebuffer_pitch_for_width(mode_cmd.width,
6344                                                                 bpp);
6345         mode_cmd.pixel_format = drm_mode_legacy_fb_format(bpp, depth);
6346
6347         return intel_framebuffer_create(dev, &mode_cmd, obj);
6348 }
6349
6350 static struct drm_framebuffer *
6351 mode_fits_in_fbdev(struct drm_device *dev,
6352                    struct drm_display_mode *mode)
6353 {
6354         struct drm_i915_private *dev_priv = dev->dev_private;
6355         struct drm_i915_gem_object *obj;
6356         struct drm_framebuffer *fb;
6357
6358         if (dev_priv->fbdev == NULL)
6359                 return NULL;
6360
6361         obj = dev_priv->fbdev->ifb.obj;
6362         if (obj == NULL)
6363                 return NULL;
6364
6365         fb = &dev_priv->fbdev->ifb.base;
6366         if (fb->pitches[0] < intel_framebuffer_pitch_for_width(mode->hdisplay,
6367                                                                fb->bits_per_pixel))
6368                 return NULL;
6369
6370         if (obj->base.size < mode->vdisplay * fb->pitches[0])
6371                 return NULL;
6372
6373         return fb;
6374 }
6375
6376 bool intel_get_load_detect_pipe(struct drm_connector *connector,
6377                                 struct drm_display_mode *mode,
6378                                 struct intel_load_detect_pipe *old)
6379 {
6380         struct intel_crtc *intel_crtc;
6381         struct intel_encoder *intel_encoder =
6382                 intel_attached_encoder(connector);
6383         struct drm_crtc *possible_crtc;
6384         struct drm_encoder *encoder = &intel_encoder->base;
6385         struct drm_crtc *crtc = NULL;
6386         struct drm_device *dev = encoder->dev;
6387         struct drm_framebuffer *fb;
6388         int i = -1;
6389
6390         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6391                       connector->base.id, drm_get_connector_name(connector),
6392                       encoder->base.id, drm_get_encoder_name(encoder));
6393
6394         /*
6395          * Algorithm gets a little messy:
6396          *
6397          *   - if the connector already has an assigned crtc, use it (but make
6398          *     sure it's on first)
6399          *
6400          *   - try to find the first unused crtc that can drive this connector,
6401          *     and use that if we find one
6402          */
6403
6404         /* See if we already have a CRTC for this connector */
6405         if (encoder->crtc) {
6406                 crtc = encoder->crtc;
6407
6408                 old->dpms_mode = connector->dpms;
6409                 old->load_detect_temp = false;
6410
6411                 /* Make sure the crtc and connector are running */
6412                 if (connector->dpms != DRM_MODE_DPMS_ON)
6413                         connector->funcs->dpms(connector, DRM_MODE_DPMS_ON);
6414
6415                 return true;
6416         }
6417
6418         /* Find an unused one (if possible) */
6419         list_for_each_entry(possible_crtc, &dev->mode_config.crtc_list, head) {
6420                 i++;
6421                 if (!(encoder->possible_crtcs & (1 << i)))
6422                         continue;
6423                 if (!possible_crtc->enabled) {
6424                         crtc = possible_crtc;
6425                         break;
6426                 }
6427         }
6428
6429         /*
6430          * If we didn't find an unused CRTC, don't use any.
6431          */
6432         if (!crtc) {
6433                 DRM_DEBUG_KMS("no pipe available for load-detect\n");
6434                 return false;
6435         }
6436
6437         intel_encoder->new_crtc = to_intel_crtc(crtc);
6438         to_intel_connector(connector)->new_encoder = intel_encoder;
6439
6440         intel_crtc = to_intel_crtc(crtc);
6441         old->dpms_mode = connector->dpms;
6442         old->load_detect_temp = true;
6443         old->release_fb = NULL;
6444
6445         if (!mode)
6446                 mode = &load_detect_mode;
6447
6448         /* We need a framebuffer large enough to accommodate all accesses
6449          * that the plane may generate whilst we perform load detection.
6450          * We can not rely on the fbcon either being present (we get called
6451          * during its initialisation to detect all boot displays, or it may
6452          * not even exist) or that it is large enough to satisfy the
6453          * requested mode.
6454          */
6455         fb = mode_fits_in_fbdev(dev, mode);
6456         if (fb == NULL) {
6457                 DRM_DEBUG_KMS("creating tmp fb for load-detection\n");
6458                 fb = intel_framebuffer_create_for_mode(dev, mode, 24, 32);
6459                 old->release_fb = fb;
6460         } else
6461                 DRM_DEBUG_KMS("reusing fbdev for load-detection framebuffer\n");
6462         if (IS_ERR(fb)) {
6463                 DRM_DEBUG_KMS("failed to allocate framebuffer for load-detection\n");
6464                 return false;
6465         }
6466
6467         if (!intel_set_mode(crtc, mode, 0, 0, fb)) {
6468                 DRM_DEBUG_KMS("failed to set mode on load-detect pipe\n");
6469                 if (old->release_fb)
6470                         old->release_fb->funcs->destroy(old->release_fb);
6471                 return false;
6472         }
6473
6474         /* let the connector get through one full cycle before testing */
6475         intel_wait_for_vblank(dev, intel_crtc->pipe);
6476         return true;
6477 }
6478
6479 void intel_release_load_detect_pipe(struct drm_connector *connector,
6480                                     struct intel_load_detect_pipe *old)
6481 {
6482         struct intel_encoder *intel_encoder =
6483                 intel_attached_encoder(connector);
6484         struct drm_encoder *encoder = &intel_encoder->base;
6485
6486         DRM_DEBUG_KMS("[CONNECTOR:%d:%s], [ENCODER:%d:%s]\n",
6487                       connector->base.id, drm_get_connector_name(connector),
6488                       encoder->base.id, drm_get_encoder_name(encoder));
6489
6490         if (old->load_detect_temp) {
6491                 struct drm_crtc *crtc = encoder->crtc;
6492
6493                 to_intel_connector(connector)->new_encoder = NULL;
6494                 intel_encoder->new_crtc = NULL;
6495                 intel_set_mode(crtc, NULL, 0, 0, NULL);
6496
6497                 if (old->release_fb)
6498                         old->release_fb->funcs->destroy(old->release_fb);
6499
6500                 return;
6501         }
6502
6503         /* Switch crtc and encoder back off if necessary */
6504         if (old->dpms_mode != DRM_MODE_DPMS_ON)
6505                 connector->funcs->dpms(connector, old->dpms_mode);
6506 }
6507
6508 /* Returns the clock of the currently programmed mode of the given pipe. */
6509 static int intel_crtc_clock_get(struct drm_device *dev, struct drm_crtc *crtc)
6510 {
6511         struct drm_i915_private *dev_priv = dev->dev_private;
6512         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6513         int pipe = intel_crtc->pipe;
6514         u32 dpll = I915_READ(DPLL(pipe));
6515         u32 fp;
6516         intel_clock_t clock;
6517
6518         if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
6519                 fp = I915_READ(FP0(pipe));
6520         else
6521                 fp = I915_READ(FP1(pipe));
6522
6523         clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
6524         if (IS_PINEVIEW(dev)) {
6525                 clock.n = ffs((fp & FP_N_PINEVIEW_DIV_MASK) >> FP_N_DIV_SHIFT) - 1;
6526                 clock.m2 = (fp & FP_M2_PINEVIEW_DIV_MASK) >> FP_M2_DIV_SHIFT;
6527         } else {
6528                 clock.n = (fp & FP_N_DIV_MASK) >> FP_N_DIV_SHIFT;
6529                 clock.m2 = (fp & FP_M2_DIV_MASK) >> FP_M2_DIV_SHIFT;
6530         }
6531
6532         if (!IS_GEN2(dev)) {
6533                 if (IS_PINEVIEW(dev))
6534                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_PINEVIEW) >>
6535                                 DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW);
6536                 else
6537                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK) >>
6538                                DPLL_FPA01_P1_POST_DIV_SHIFT);
6539
6540                 switch (dpll & DPLL_MODE_MASK) {
6541                 case DPLLB_MODE_DAC_SERIAL:
6542                         clock.p2 = dpll & DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 ?
6543                                 5 : 10;
6544                         break;
6545                 case DPLLB_MODE_LVDS:
6546                         clock.p2 = dpll & DPLLB_LVDS_P2_CLOCK_DIV_7 ?
6547                                 7 : 14;
6548                         break;
6549                 default:
6550                         DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
6551                                   "mode\n", (int)(dpll & DPLL_MODE_MASK));
6552                         return 0;
6553                 }
6554
6555                 /* XXX: Handle the 100Mhz refclk */
6556                 intel_clock(dev, 96000, &clock);
6557         } else {
6558                 bool is_lvds = (pipe == 1) && (I915_READ(LVDS) & LVDS_PORT_EN);
6559
6560                 if (is_lvds) {
6561                         clock.p1 = ffs((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS) >>
6562                                        DPLL_FPA01_P1_POST_DIV_SHIFT);
6563                         clock.p2 = 14;
6564
6565                         if ((dpll & PLL_REF_INPUT_MASK) ==
6566                             PLLB_REF_INPUT_SPREADSPECTRUMIN) {
6567                                 /* XXX: might not be 66MHz */
6568                                 intel_clock(dev, 66000, &clock);
6569                         } else
6570                                 intel_clock(dev, 48000, &clock);
6571                 } else {
6572                         if (dpll & PLL_P1_DIVIDE_BY_TWO)
6573                                 clock.p1 = 2;
6574                         else {
6575                                 clock.p1 = ((dpll & DPLL_FPA01_P1_POST_DIV_MASK_I830) >>
6576                                             DPLL_FPA01_P1_POST_DIV_SHIFT) + 2;
6577                         }
6578                         if (dpll & PLL_P2_DIVIDE_BY_4)
6579                                 clock.p2 = 4;
6580                         else
6581                                 clock.p2 = 2;
6582
6583                         intel_clock(dev, 48000, &clock);
6584                 }
6585         }
6586
6587         /* XXX: It would be nice to validate the clocks, but we can't reuse
6588          * i830PllIsValid() because it relies on the xf86_config connector
6589          * configuration being accurate, which it isn't necessarily.
6590          */
6591
6592         return clock.dot;
6593 }
6594
6595 /** Returns the currently programmed mode of the given pipe. */
6596 struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
6597                                              struct drm_crtc *crtc)
6598 {
6599         struct drm_i915_private *dev_priv = dev->dev_private;
6600         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6601         enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder;
6602         struct drm_display_mode *mode;
6603         int htot = I915_READ(HTOTAL(cpu_transcoder));
6604         int hsync = I915_READ(HSYNC(cpu_transcoder));
6605         int vtot = I915_READ(VTOTAL(cpu_transcoder));
6606         int vsync = I915_READ(VSYNC(cpu_transcoder));
6607
6608         mode = kzalloc(sizeof(*mode), GFP_KERNEL);
6609         if (!mode)
6610                 return NULL;
6611
6612         mode->clock = intel_crtc_clock_get(dev, crtc);
6613         mode->hdisplay = (htot & 0xffff) + 1;
6614         mode->htotal = ((htot & 0xffff0000) >> 16) + 1;
6615         mode->hsync_start = (hsync & 0xffff) + 1;
6616         mode->hsync_end = ((hsync & 0xffff0000) >> 16) + 1;
6617         mode->vdisplay = (vtot & 0xffff) + 1;
6618         mode->vtotal = ((vtot & 0xffff0000) >> 16) + 1;
6619         mode->vsync_start = (vsync & 0xffff) + 1;
6620         mode->vsync_end = ((vsync & 0xffff0000) >> 16) + 1;
6621
6622         drm_mode_set_name(mode);
6623
6624         return mode;
6625 }
6626
6627 static void intel_increase_pllclock(struct drm_crtc *crtc)
6628 {
6629         struct drm_device *dev = crtc->dev;
6630         drm_i915_private_t *dev_priv = dev->dev_private;
6631         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6632         int pipe = intel_crtc->pipe;
6633         int dpll_reg = DPLL(pipe);
6634         int dpll;
6635
6636         if (HAS_PCH_SPLIT(dev))
6637                 return;
6638
6639         if (!dev_priv->lvds_downclock_avail)
6640                 return;
6641
6642         dpll = I915_READ(dpll_reg);
6643         if (!HAS_PIPE_CXSR(dev) && (dpll & DISPLAY_RATE_SELECT_FPA1)) {
6644                 DRM_DEBUG_DRIVER("upclocking LVDS\n");
6645
6646                 assert_panel_unlocked(dev_priv, pipe);
6647
6648                 dpll &= ~DISPLAY_RATE_SELECT_FPA1;
6649                 I915_WRITE(dpll_reg, dpll);
6650                 intel_wait_for_vblank(dev, pipe);
6651
6652                 dpll = I915_READ(dpll_reg);
6653                 if (dpll & DISPLAY_RATE_SELECT_FPA1)
6654                         DRM_DEBUG_DRIVER("failed to upclock LVDS!\n");
6655         }
6656 }
6657
6658 static void intel_decrease_pllclock(struct drm_crtc *crtc)
6659 {
6660         struct drm_device *dev = crtc->dev;
6661         drm_i915_private_t *dev_priv = dev->dev_private;
6662         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6663
6664         if (HAS_PCH_SPLIT(dev))
6665                 return;
6666
6667         if (!dev_priv->lvds_downclock_avail)
6668                 return;
6669
6670         /*
6671          * Since this is called by a timer, we should never get here in
6672          * the manual case.
6673          */
6674         if (!HAS_PIPE_CXSR(dev) && intel_crtc->lowfreq_avail) {
6675                 int pipe = intel_crtc->pipe;
6676                 int dpll_reg = DPLL(pipe);
6677                 int dpll;
6678
6679                 DRM_DEBUG_DRIVER("downclocking LVDS\n");
6680
6681                 assert_panel_unlocked(dev_priv, pipe);
6682
6683                 dpll = I915_READ(dpll_reg);
6684                 dpll |= DISPLAY_RATE_SELECT_FPA1;
6685                 I915_WRITE(dpll_reg, dpll);
6686                 intel_wait_for_vblank(dev, pipe);
6687                 dpll = I915_READ(dpll_reg);
6688                 if (!(dpll & DISPLAY_RATE_SELECT_FPA1))
6689                         DRM_DEBUG_DRIVER("failed to downclock LVDS!\n");
6690         }
6691
6692 }
6693
6694 void intel_mark_busy(struct drm_device *dev)
6695 {
6696         i915_update_gfx_val(dev->dev_private);
6697 }
6698
6699 void intel_mark_idle(struct drm_device *dev)
6700 {
6701 }
6702
6703 void intel_mark_fb_busy(struct drm_i915_gem_object *obj)
6704 {
6705         struct drm_device *dev = obj->base.dev;
6706         struct drm_crtc *crtc;
6707
6708         if (!i915_powersave)
6709                 return;
6710
6711         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6712                 if (!crtc->fb)
6713                         continue;
6714
6715                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6716                         intel_increase_pllclock(crtc);
6717         }
6718 }
6719
6720 void intel_mark_fb_idle(struct drm_i915_gem_object *obj)
6721 {
6722         struct drm_device *dev = obj->base.dev;
6723         struct drm_crtc *crtc;
6724
6725         if (!i915_powersave)
6726                 return;
6727
6728         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
6729                 if (!crtc->fb)
6730                         continue;
6731
6732                 if (to_intel_framebuffer(crtc->fb)->obj == obj)
6733                         intel_decrease_pllclock(crtc);
6734         }
6735 }
6736
6737 static void intel_crtc_destroy(struct drm_crtc *crtc)
6738 {
6739         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6740         struct drm_device *dev = crtc->dev;
6741         struct intel_unpin_work *work;
6742         unsigned long flags;
6743
6744         spin_lock_irqsave(&dev->event_lock, flags);
6745         work = intel_crtc->unpin_work;
6746         intel_crtc->unpin_work = NULL;
6747         spin_unlock_irqrestore(&dev->event_lock, flags);
6748
6749         if (work) {
6750                 cancel_work_sync(&work->work);
6751                 kfree(work);
6752         }
6753
6754         drm_crtc_cleanup(crtc);
6755
6756         kfree(intel_crtc);
6757 }
6758
6759 static void intel_unpin_work_fn(struct work_struct *__work)
6760 {
6761         struct intel_unpin_work *work =
6762                 container_of(__work, struct intel_unpin_work, work);
6763         struct drm_device *dev = work->crtc->dev;
6764
6765         mutex_lock(&dev->struct_mutex);
6766         intel_unpin_fb_obj(work->old_fb_obj);
6767         drm_gem_object_unreference(&work->pending_flip_obj->base);
6768         drm_gem_object_unreference(&work->old_fb_obj->base);
6769
6770         intel_update_fbc(dev);
6771         mutex_unlock(&dev->struct_mutex);
6772
6773         BUG_ON(atomic_read(&to_intel_crtc(work->crtc)->unpin_work_count) == 0);
6774         atomic_dec(&to_intel_crtc(work->crtc)->unpin_work_count);
6775
6776         kfree(work);
6777 }
6778
6779 static void do_intel_finish_page_flip(struct drm_device *dev,
6780                                       struct drm_crtc *crtc)
6781 {
6782         drm_i915_private_t *dev_priv = dev->dev_private;
6783         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6784         struct intel_unpin_work *work;
6785         struct drm_i915_gem_object *obj;
6786         unsigned long flags;
6787
6788         /* Ignore early vblank irqs */
6789         if (intel_crtc == NULL)
6790                 return;
6791
6792         spin_lock_irqsave(&dev->event_lock, flags);
6793         work = intel_crtc->unpin_work;
6794         if (work == NULL || !work->pending) {
6795                 spin_unlock_irqrestore(&dev->event_lock, flags);
6796                 return;
6797         }
6798
6799         intel_crtc->unpin_work = NULL;
6800
6801         if (work->event)
6802                 drm_send_vblank_event(dev, intel_crtc->pipe, work->event);
6803
6804         drm_vblank_put(dev, intel_crtc->pipe);
6805
6806         spin_unlock_irqrestore(&dev->event_lock, flags);
6807
6808         obj = work->old_fb_obj;
6809
6810         wake_up(&dev_priv->pending_flip_queue);
6811
6812         queue_work(dev_priv->wq, &work->work);
6813
6814         trace_i915_flip_complete(intel_crtc->plane, work->pending_flip_obj);
6815 }
6816
6817 void intel_finish_page_flip(struct drm_device *dev, int pipe)
6818 {
6819         drm_i915_private_t *dev_priv = dev->dev_private;
6820         struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
6821
6822         do_intel_finish_page_flip(dev, crtc);
6823 }
6824
6825 void intel_finish_page_flip_plane(struct drm_device *dev, int plane)
6826 {
6827         drm_i915_private_t *dev_priv = dev->dev_private;
6828         struct drm_crtc *crtc = dev_priv->plane_to_crtc_mapping[plane];
6829
6830         do_intel_finish_page_flip(dev, crtc);
6831 }
6832
6833 void intel_prepare_page_flip(struct drm_device *dev, int plane)
6834 {
6835         drm_i915_private_t *dev_priv = dev->dev_private;
6836         struct intel_crtc *intel_crtc =
6837                 to_intel_crtc(dev_priv->plane_to_crtc_mapping[plane]);
6838         unsigned long flags;
6839
6840         spin_lock_irqsave(&dev->event_lock, flags);
6841         if (intel_crtc->unpin_work) {
6842                 if ((++intel_crtc->unpin_work->pending) > 1)
6843                         DRM_ERROR("Prepared flip multiple times\n");
6844         } else {
6845                 DRM_DEBUG_DRIVER("preparing flip with no unpin work?\n");
6846         }
6847         spin_unlock_irqrestore(&dev->event_lock, flags);
6848 }
6849
6850 static int intel_gen2_queue_flip(struct drm_device *dev,
6851                                  struct drm_crtc *crtc,
6852                                  struct drm_framebuffer *fb,
6853                                  struct drm_i915_gem_object *obj)
6854 {
6855         struct drm_i915_private *dev_priv = dev->dev_private;
6856         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6857         u32 flip_mask;
6858         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6859         int ret;
6860
6861         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6862         if (ret)
6863                 goto err;
6864
6865         ret = intel_ring_begin(ring, 6);
6866         if (ret)
6867                 goto err_unpin;
6868
6869         /* Can't queue multiple flips, so wait for the previous
6870          * one to finish before executing the next.
6871          */
6872         if (intel_crtc->plane)
6873                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6874         else
6875                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6876         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6877         intel_ring_emit(ring, MI_NOOP);
6878         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6879                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6880         intel_ring_emit(ring, fb->pitches[0]);
6881         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6882         intel_ring_emit(ring, 0); /* aux display base address, unused */
6883         intel_ring_advance(ring);
6884         return 0;
6885
6886 err_unpin:
6887         intel_unpin_fb_obj(obj);
6888 err:
6889         return ret;
6890 }
6891
6892 static int intel_gen3_queue_flip(struct drm_device *dev,
6893                                  struct drm_crtc *crtc,
6894                                  struct drm_framebuffer *fb,
6895                                  struct drm_i915_gem_object *obj)
6896 {
6897         struct drm_i915_private *dev_priv = dev->dev_private;
6898         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6899         u32 flip_mask;
6900         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6901         int ret;
6902
6903         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6904         if (ret)
6905                 goto err;
6906
6907         ret = intel_ring_begin(ring, 6);
6908         if (ret)
6909                 goto err_unpin;
6910
6911         if (intel_crtc->plane)
6912                 flip_mask = MI_WAIT_FOR_PLANE_B_FLIP;
6913         else
6914                 flip_mask = MI_WAIT_FOR_PLANE_A_FLIP;
6915         intel_ring_emit(ring, MI_WAIT_FOR_EVENT | flip_mask);
6916         intel_ring_emit(ring, MI_NOOP);
6917         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 |
6918                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6919         intel_ring_emit(ring, fb->pitches[0]);
6920         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
6921         intel_ring_emit(ring, MI_NOOP);
6922
6923         intel_ring_advance(ring);
6924         return 0;
6925
6926 err_unpin:
6927         intel_unpin_fb_obj(obj);
6928 err:
6929         return ret;
6930 }
6931
6932 static int intel_gen4_queue_flip(struct drm_device *dev,
6933                                  struct drm_crtc *crtc,
6934                                  struct drm_framebuffer *fb,
6935                                  struct drm_i915_gem_object *obj)
6936 {
6937         struct drm_i915_private *dev_priv = dev->dev_private;
6938         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6939         uint32_t pf, pipesrc;
6940         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6941         int ret;
6942
6943         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6944         if (ret)
6945                 goto err;
6946
6947         ret = intel_ring_begin(ring, 4);
6948         if (ret)
6949                 goto err_unpin;
6950
6951         /* i965+ uses the linear or tiled offsets from the
6952          * Display Registers (which do not change across a page-flip)
6953          * so we need only reprogram the base address.
6954          */
6955         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6956                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6957         intel_ring_emit(ring, fb->pitches[0]);
6958         intel_ring_emit(ring,
6959                         (obj->gtt_offset + intel_crtc->dspaddr_offset) |
6960                         obj->tiling_mode);
6961
6962         /* XXX Enabling the panel-fitter across page-flip is so far
6963          * untested on non-native modes, so ignore it for now.
6964          * pf = I915_READ(pipe == 0 ? PFA_CTL_1 : PFB_CTL_1) & PF_ENABLE;
6965          */
6966         pf = 0;
6967         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
6968         intel_ring_emit(ring, pf | pipesrc);
6969         intel_ring_advance(ring);
6970         return 0;
6971
6972 err_unpin:
6973         intel_unpin_fb_obj(obj);
6974 err:
6975         return ret;
6976 }
6977
6978 static int intel_gen6_queue_flip(struct drm_device *dev,
6979                                  struct drm_crtc *crtc,
6980                                  struct drm_framebuffer *fb,
6981                                  struct drm_i915_gem_object *obj)
6982 {
6983         struct drm_i915_private *dev_priv = dev->dev_private;
6984         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6985         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
6986         uint32_t pf, pipesrc;
6987         int ret;
6988
6989         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
6990         if (ret)
6991                 goto err;
6992
6993         ret = intel_ring_begin(ring, 4);
6994         if (ret)
6995                 goto err_unpin;
6996
6997         intel_ring_emit(ring, MI_DISPLAY_FLIP |
6998                         MI_DISPLAY_FLIP_PLANE(intel_crtc->plane));
6999         intel_ring_emit(ring, fb->pitches[0] | obj->tiling_mode);
7000         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7001
7002         /* Contrary to the suggestions in the documentation,
7003          * "Enable Panel Fitter" does not seem to be required when page
7004          * flipping with a non-native mode, and worse causes a normal
7005          * modeset to fail.
7006          * pf = I915_READ(PF_CTL(intel_crtc->pipe)) & PF_ENABLE;
7007          */
7008         pf = 0;
7009         pipesrc = I915_READ(PIPESRC(intel_crtc->pipe)) & 0x0fff0fff;
7010         intel_ring_emit(ring, pf | pipesrc);
7011         intel_ring_advance(ring);
7012         return 0;
7013
7014 err_unpin:
7015         intel_unpin_fb_obj(obj);
7016 err:
7017         return ret;
7018 }
7019
7020 /*
7021  * On gen7 we currently use the blit ring because (in early silicon at least)
7022  * the render ring doesn't give us interrpts for page flip completion, which
7023  * means clients will hang after the first flip is queued.  Fortunately the
7024  * blit ring generates interrupts properly, so use it instead.
7025  */
7026 static int intel_gen7_queue_flip(struct drm_device *dev,
7027                                  struct drm_crtc *crtc,
7028                                  struct drm_framebuffer *fb,
7029                                  struct drm_i915_gem_object *obj)
7030 {
7031         struct drm_i915_private *dev_priv = dev->dev_private;
7032         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7033         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
7034         uint32_t plane_bit = 0;
7035         int ret;
7036
7037         ret = intel_pin_and_fence_fb_obj(dev, obj, ring);
7038         if (ret)
7039                 goto err;
7040
7041         switch(intel_crtc->plane) {
7042         case PLANE_A:
7043                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_A;
7044                 break;
7045         case PLANE_B:
7046                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_B;
7047                 break;
7048         case PLANE_C:
7049                 plane_bit = MI_DISPLAY_FLIP_IVB_PLANE_C;
7050                 break;
7051         default:
7052                 WARN_ONCE(1, "unknown plane in flip command\n");
7053                 ret = -ENODEV;
7054                 goto err_unpin;
7055         }
7056
7057         ret = intel_ring_begin(ring, 4);
7058         if (ret)
7059                 goto err_unpin;
7060
7061         intel_ring_emit(ring, MI_DISPLAY_FLIP_I915 | plane_bit);
7062         intel_ring_emit(ring, (fb->pitches[0] | obj->tiling_mode));
7063         intel_ring_emit(ring, obj->gtt_offset + intel_crtc->dspaddr_offset);
7064         intel_ring_emit(ring, (MI_NOOP));
7065         intel_ring_advance(ring);
7066         return 0;
7067
7068 err_unpin:
7069         intel_unpin_fb_obj(obj);
7070 err:
7071         return ret;
7072 }
7073
7074 static int intel_default_queue_flip(struct drm_device *dev,
7075                                     struct drm_crtc *crtc,
7076                                     struct drm_framebuffer *fb,
7077                                     struct drm_i915_gem_object *obj)
7078 {
7079         return -ENODEV;
7080 }
7081
7082 static int intel_crtc_page_flip(struct drm_crtc *crtc,
7083                                 struct drm_framebuffer *fb,
7084                                 struct drm_pending_vblank_event *event)
7085 {
7086         struct drm_device *dev = crtc->dev;
7087         struct drm_i915_private *dev_priv = dev->dev_private;
7088         struct intel_framebuffer *intel_fb;
7089         struct drm_i915_gem_object *obj;
7090         struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7091         struct intel_unpin_work *work;
7092         unsigned long flags;
7093         int ret;
7094
7095         /* Can't change pixel format via MI display flips. */
7096         if (fb->pixel_format != crtc->fb->pixel_format)
7097                 return -EINVAL;
7098
7099         /*
7100          * TILEOFF/LINOFF registers can't be changed via MI display flips.
7101          * Note that pitch changes could also affect these register.
7102          */
7103         if (INTEL_INFO(dev)->gen > 3 &&
7104             (fb->offsets[0] != crtc->fb->offsets[0] ||
7105              fb->pitches[0] != crtc->fb->pitches[0]))
7106                 return -EINVAL;
7107
7108         work = kzalloc(sizeof *work, GFP_KERNEL);
7109         if (work == NULL)
7110                 return -ENOMEM;
7111
7112         work->event = event;
7113         work->crtc = crtc;
7114         intel_fb = to_intel_framebuffer(crtc->fb);
7115         work->old_fb_obj = intel_fb->obj;
7116         INIT_WORK(&work->work, intel_unpin_work_fn);
7117
7118         ret = drm_vblank_get(dev, intel_crtc->pipe);
7119         if (ret)
7120                 goto free_work;
7121
7122         /* We borrow the event spin lock for protecting unpin_work */
7123         spin_lock_irqsave(&dev->event_lock, flags);
7124         if (intel_crtc->unpin_work) {
7125                 spin_unlock_irqrestore(&dev->event_lock, flags);
7126                 kfree(work);
7127                 drm_vblank_put(dev, intel_crtc->pipe);
7128
7129                 DRM_DEBUG_DRIVER("flip queue: crtc already busy\n");
7130                 return -EBUSY;
7131         }
7132         intel_crtc->unpin_work = work;
7133         spin_unlock_irqrestore(&dev->event_lock, flags);
7134
7135         intel_fb = to_intel_framebuffer(fb);
7136         obj = intel_fb->obj;
7137
7138         if (atomic_read(&intel_crtc->unpin_work_count) >= 2)
7139                 flush_workqueue(dev_priv->wq);
7140
7141         ret = i915_mutex_lock_interruptible(dev);
7142         if (ret)
7143                 goto cleanup;
7144
7145         /* Reference the objects for the scheduled work. */
7146         drm_gem_object_reference(&work->old_fb_obj->base);
7147         drm_gem_object_reference(&obj->base);
7148
7149         crtc->fb = fb;
7150
7151         work->pending_flip_obj = obj;
7152
7153         work->enable_stall_check = true;
7154
7155         atomic_inc(&intel_crtc->unpin_work_count);
7156
7157         ret = dev_priv->display.queue_flip(dev, crtc, fb, obj);
7158         if (ret)
7159                 goto cleanup_pending;
7160
7161         intel_disable_fbc(dev);
7162         intel_mark_fb_busy(obj);
7163         mutex_unlock(&dev->struct_mutex);
7164
7165         trace_i915_flip_request(intel_crtc->plane, obj);
7166
7167         return 0;
7168
7169 cleanup_pending:
7170         atomic_dec(&intel_crtc->unpin_work_count);
7171         drm_gem_object_unreference(&work->old_fb_obj->base);
7172         drm_gem_object_unreference(&obj->base);
7173         mutex_unlock(&dev->struct_mutex);
7174
7175 cleanup:
7176         spin_lock_irqsave(&dev->event_lock, flags);
7177         intel_crtc->unpin_work = NULL;
7178         spin_unlock_irqrestore(&dev->event_lock, flags);
7179
7180         drm_vblank_put(dev, intel_crtc->pipe);
7181 free_work:
7182         kfree(work);
7183
7184         return ret;
7185 }
7186
7187 static struct drm_crtc_helper_funcs intel_helper_funcs = {
7188         .mode_set_base_atomic = intel_pipe_set_base_atomic,
7189         .load_lut = intel_crtc_load_lut,
7190         .disable = intel_crtc_noop,
7191 };
7192
7193 bool intel_encoder_check_is_cloned(struct intel_encoder *encoder)
7194 {
7195         struct intel_encoder *other_encoder;
7196         struct drm_crtc *crtc = &encoder->new_crtc->base;
7197
7198         if (WARN_ON(!crtc))
7199                 return false;
7200
7201         list_for_each_entry(other_encoder,
7202                             &crtc->dev->mode_config.encoder_list,
7203                             base.head) {
7204
7205                 if (&other_encoder->new_crtc->base != crtc ||
7206                     encoder == other_encoder)
7207                         continue;
7208                 else
7209                         return true;
7210         }
7211
7212         return false;
7213 }
7214
7215 static bool intel_encoder_crtc_ok(struct drm_encoder *encoder,
7216                                   struct drm_crtc *crtc)
7217 {
7218         struct drm_device *dev;
7219         struct drm_crtc *tmp;
7220         int crtc_mask = 1;
7221
7222         WARN(!crtc, "checking null crtc?\n");
7223
7224         dev = crtc->dev;
7225
7226         list_for_each_entry(tmp, &dev->mode_config.crtc_list, head) {
7227                 if (tmp == crtc)
7228                         break;
7229                 crtc_mask <<= 1;
7230         }
7231
7232         if (encoder->possible_crtcs & crtc_mask)
7233                 return true;
7234         return false;
7235 }
7236
7237 /**
7238  * intel_modeset_update_staged_output_state
7239  *
7240  * Updates the staged output configuration state, e.g. after we've read out the
7241  * current hw state.
7242  */
7243 static void intel_modeset_update_staged_output_state(struct drm_device *dev)
7244 {
7245         struct intel_encoder *encoder;
7246         struct intel_connector *connector;
7247
7248         list_for_each_entry(connector, &dev->mode_config.connector_list,
7249                             base.head) {
7250                 connector->new_encoder =
7251                         to_intel_encoder(connector->base.encoder);
7252         }
7253
7254         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7255                             base.head) {
7256                 encoder->new_crtc =
7257                         to_intel_crtc(encoder->base.crtc);
7258         }
7259 }
7260
7261 /**
7262  * intel_modeset_commit_output_state
7263  *
7264  * This function copies the stage display pipe configuration to the real one.
7265  */
7266 static void intel_modeset_commit_output_state(struct drm_device *dev)
7267 {
7268         struct intel_encoder *encoder;
7269         struct intel_connector *connector;
7270
7271         list_for_each_entry(connector, &dev->mode_config.connector_list,
7272                             base.head) {
7273                 connector->base.encoder = &connector->new_encoder->base;
7274         }
7275
7276         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7277                             base.head) {
7278                 encoder->base.crtc = &encoder->new_crtc->base;
7279         }
7280 }
7281
7282 static struct drm_display_mode *
7283 intel_modeset_adjusted_mode(struct drm_crtc *crtc,
7284                             struct drm_display_mode *mode)
7285 {
7286         struct drm_device *dev = crtc->dev;
7287         struct drm_display_mode *adjusted_mode;
7288         struct drm_encoder_helper_funcs *encoder_funcs;
7289         struct intel_encoder *encoder;
7290
7291         adjusted_mode = drm_mode_duplicate(dev, mode);
7292         if (!adjusted_mode)
7293                 return ERR_PTR(-ENOMEM);
7294
7295         /* Pass our mode to the connectors and the CRTC to give them a chance to
7296          * adjust it according to limitations or connector properties, and also
7297          * a chance to reject the mode entirely.
7298          */
7299         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7300                             base.head) {
7301
7302                 if (&encoder->new_crtc->base != crtc)
7303                         continue;
7304                 encoder_funcs = encoder->base.helper_private;
7305                 if (!(encoder_funcs->mode_fixup(&encoder->base, mode,
7306                                                 adjusted_mode))) {
7307                         DRM_DEBUG_KMS("Encoder fixup failed\n");
7308                         goto fail;
7309                 }
7310         }
7311
7312         if (!(intel_crtc_mode_fixup(crtc, mode, adjusted_mode))) {
7313                 DRM_DEBUG_KMS("CRTC fixup failed\n");
7314                 goto fail;
7315         }
7316         DRM_DEBUG_KMS("[CRTC:%d]\n", crtc->base.id);
7317
7318         return adjusted_mode;
7319 fail:
7320         drm_mode_destroy(dev, adjusted_mode);
7321         return ERR_PTR(-EINVAL);
7322 }
7323
7324 /* Computes which crtcs are affected and sets the relevant bits in the mask. For
7325  * simplicity we use the crtc's pipe number (because it's easier to obtain). */
7326 static void
7327 intel_modeset_affected_pipes(struct drm_crtc *crtc, unsigned *modeset_pipes,
7328                              unsigned *prepare_pipes, unsigned *disable_pipes)
7329 {
7330         struct intel_crtc *intel_crtc;
7331         struct drm_device *dev = crtc->dev;
7332         struct intel_encoder *encoder;
7333         struct intel_connector *connector;
7334         struct drm_crtc *tmp_crtc;
7335
7336         *disable_pipes = *modeset_pipes = *prepare_pipes = 0;
7337
7338         /* Check which crtcs have changed outputs connected to them, these need
7339          * to be part of the prepare_pipes mask. We don't (yet) support global
7340          * modeset across multiple crtcs, so modeset_pipes will only have one
7341          * bit set at most. */
7342         list_for_each_entry(connector, &dev->mode_config.connector_list,
7343                             base.head) {
7344                 if (connector->base.encoder == &connector->new_encoder->base)
7345                         continue;
7346
7347                 if (connector->base.encoder) {
7348                         tmp_crtc = connector->base.encoder->crtc;
7349
7350                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7351                 }
7352
7353                 if (connector->new_encoder)
7354                         *prepare_pipes |=
7355                                 1 << connector->new_encoder->new_crtc->pipe;
7356         }
7357
7358         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7359                             base.head) {
7360                 if (encoder->base.crtc == &encoder->new_crtc->base)
7361                         continue;
7362
7363                 if (encoder->base.crtc) {
7364                         tmp_crtc = encoder->base.crtc;
7365
7366                         *prepare_pipes |= 1 << to_intel_crtc(tmp_crtc)->pipe;
7367                 }
7368
7369                 if (encoder->new_crtc)
7370                         *prepare_pipes |= 1 << encoder->new_crtc->pipe;
7371         }
7372
7373         /* Check for any pipes that will be fully disabled ... */
7374         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7375                             base.head) {
7376                 bool used = false;
7377
7378                 /* Don't try to disable disabled crtcs. */
7379                 if (!intel_crtc->base.enabled)
7380                         continue;
7381
7382                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7383                                     base.head) {
7384                         if (encoder->new_crtc == intel_crtc)
7385                                 used = true;
7386                 }
7387
7388                 if (!used)
7389                         *disable_pipes |= 1 << intel_crtc->pipe;
7390         }
7391
7392
7393         /* set_mode is also used to update properties on life display pipes. */
7394         intel_crtc = to_intel_crtc(crtc);
7395         if (crtc->enabled)
7396                 *prepare_pipes |= 1 << intel_crtc->pipe;
7397
7398         /* We only support modeset on one single crtc, hence we need to do that
7399          * only for the passed in crtc iff we change anything else than just
7400          * disable crtcs.
7401          *
7402          * This is actually not true, to be fully compatible with the old crtc
7403          * helper we automatically disable _any_ output (i.e. doesn't need to be
7404          * connected to the crtc we're modesetting on) if it's disconnected.
7405          * Which is a rather nutty api (since changed the output configuration
7406          * without userspace's explicit request can lead to confusion), but
7407          * alas. Hence we currently need to modeset on all pipes we prepare. */
7408         if (*prepare_pipes)
7409                 *modeset_pipes = *prepare_pipes;
7410
7411         /* ... and mask these out. */
7412         *modeset_pipes &= ~(*disable_pipes);
7413         *prepare_pipes &= ~(*disable_pipes);
7414 }
7415
7416 static bool intel_crtc_in_use(struct drm_crtc *crtc)
7417 {
7418         struct drm_encoder *encoder;
7419         struct drm_device *dev = crtc->dev;
7420
7421         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head)
7422                 if (encoder->crtc == crtc)
7423                         return true;
7424
7425         return false;
7426 }
7427
7428 static void
7429 intel_modeset_update_state(struct drm_device *dev, unsigned prepare_pipes)
7430 {
7431         struct intel_encoder *intel_encoder;
7432         struct intel_crtc *intel_crtc;
7433         struct drm_connector *connector;
7434
7435         list_for_each_entry(intel_encoder, &dev->mode_config.encoder_list,
7436                             base.head) {
7437                 if (!intel_encoder->base.crtc)
7438                         continue;
7439
7440                 intel_crtc = to_intel_crtc(intel_encoder->base.crtc);
7441
7442                 if (prepare_pipes & (1 << intel_crtc->pipe))
7443                         intel_encoder->connectors_active = false;
7444         }
7445
7446         intel_modeset_commit_output_state(dev);
7447
7448         /* Update computed state. */
7449         list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
7450                             base.head) {
7451                 intel_crtc->base.enabled = intel_crtc_in_use(&intel_crtc->base);
7452         }
7453
7454         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7455                 if (!connector->encoder || !connector->encoder->crtc)
7456                         continue;
7457
7458                 intel_crtc = to_intel_crtc(connector->encoder->crtc);
7459
7460                 if (prepare_pipes & (1 << intel_crtc->pipe)) {
7461                         struct drm_property *dpms_property =
7462                                 dev->mode_config.dpms_property;
7463
7464                         connector->dpms = DRM_MODE_DPMS_ON;
7465                         drm_object_property_set_value(&connector->base,
7466                                                          dpms_property,
7467                                                          DRM_MODE_DPMS_ON);
7468
7469                         intel_encoder = to_intel_encoder(connector->encoder);
7470                         intel_encoder->connectors_active = true;
7471                 }
7472         }
7473
7474 }
7475
7476 #define for_each_intel_crtc_masked(dev, mask, intel_crtc) \
7477         list_for_each_entry((intel_crtc), \
7478                             &(dev)->mode_config.crtc_list, \
7479                             base.head) \
7480                 if (mask & (1 <<(intel_crtc)->pipe)) \
7481
7482 void
7483 intel_modeset_check_state(struct drm_device *dev)
7484 {
7485         struct intel_crtc *crtc;
7486         struct intel_encoder *encoder;
7487         struct intel_connector *connector;
7488
7489         list_for_each_entry(connector, &dev->mode_config.connector_list,
7490                             base.head) {
7491                 /* This also checks the encoder/connector hw state with the
7492                  * ->get_hw_state callbacks. */
7493                 intel_connector_check_state(connector);
7494
7495                 WARN(&connector->new_encoder->base != connector->base.encoder,
7496                      "connector's staged encoder doesn't match current encoder\n");
7497         }
7498
7499         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7500                             base.head) {
7501                 bool enabled = false;
7502                 bool active = false;
7503                 enum pipe pipe, tracked_pipe;
7504
7505                 DRM_DEBUG_KMS("[ENCODER:%d:%s]\n",
7506                               encoder->base.base.id,
7507                               drm_get_encoder_name(&encoder->base));
7508
7509                 WARN(&encoder->new_crtc->base != encoder->base.crtc,
7510                      "encoder's stage crtc doesn't match current crtc\n");
7511                 WARN(encoder->connectors_active && !encoder->base.crtc,
7512                      "encoder's active_connectors set, but no crtc\n");
7513
7514                 list_for_each_entry(connector, &dev->mode_config.connector_list,
7515                                     base.head) {
7516                         if (connector->base.encoder != &encoder->base)
7517                                 continue;
7518                         enabled = true;
7519                         if (connector->base.dpms != DRM_MODE_DPMS_OFF)
7520                                 active = true;
7521                 }
7522                 WARN(!!encoder->base.crtc != enabled,
7523                      "encoder's enabled state mismatch "
7524                      "(expected %i, found %i)\n",
7525                      !!encoder->base.crtc, enabled);
7526                 WARN(active && !encoder->base.crtc,
7527                      "active encoder with no crtc\n");
7528
7529                 WARN(encoder->connectors_active != active,
7530                      "encoder's computed active state doesn't match tracked active state "
7531                      "(expected %i, found %i)\n", active, encoder->connectors_active);
7532
7533                 active = encoder->get_hw_state(encoder, &pipe);
7534                 WARN(active != encoder->connectors_active,
7535                      "encoder's hw state doesn't match sw tracking "
7536                      "(expected %i, found %i)\n",
7537                      encoder->connectors_active, active);
7538
7539                 if (!encoder->base.crtc)
7540                         continue;
7541
7542                 tracked_pipe = to_intel_crtc(encoder->base.crtc)->pipe;
7543                 WARN(active && pipe != tracked_pipe,
7544                      "active encoder's pipe doesn't match"
7545                      "(expected %i, found %i)\n",
7546                      tracked_pipe, pipe);
7547
7548         }
7549
7550         list_for_each_entry(crtc, &dev->mode_config.crtc_list,
7551                             base.head) {
7552                 bool enabled = false;
7553                 bool active = false;
7554
7555                 DRM_DEBUG_KMS("[CRTC:%d]\n",
7556                               crtc->base.base.id);
7557
7558                 WARN(crtc->active && !crtc->base.enabled,
7559                      "active crtc, but not enabled in sw tracking\n");
7560
7561                 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7562                                     base.head) {
7563                         if (encoder->base.crtc != &crtc->base)
7564                                 continue;
7565                         enabled = true;
7566                         if (encoder->connectors_active)
7567                                 active = true;
7568                 }
7569                 WARN(active != crtc->active,
7570                      "crtc's computed active state doesn't match tracked active state "
7571                      "(expected %i, found %i)\n", active, crtc->active);
7572                 WARN(enabled != crtc->base.enabled,
7573                      "crtc's computed enabled state doesn't match tracked enabled state "
7574                      "(expected %i, found %i)\n", enabled, crtc->base.enabled);
7575
7576                 assert_pipe(dev->dev_private, crtc->pipe, crtc->active);
7577         }
7578 }
7579
7580 bool intel_set_mode(struct drm_crtc *crtc,
7581                     struct drm_display_mode *mode,
7582                     int x, int y, struct drm_framebuffer *fb)
7583 {
7584         struct drm_device *dev = crtc->dev;
7585         drm_i915_private_t *dev_priv = dev->dev_private;
7586         struct drm_display_mode *adjusted_mode, saved_mode, saved_hwmode;
7587         struct intel_crtc *intel_crtc;
7588         unsigned disable_pipes, prepare_pipes, modeset_pipes;
7589         bool ret = true;
7590
7591         intel_modeset_affected_pipes(crtc, &modeset_pipes,
7592                                      &prepare_pipes, &disable_pipes);
7593
7594         DRM_DEBUG_KMS("set mode pipe masks: modeset: %x, prepare: %x, disable: %x\n",
7595                       modeset_pipes, prepare_pipes, disable_pipes);
7596
7597         for_each_intel_crtc_masked(dev, disable_pipes, intel_crtc)
7598                 intel_crtc_disable(&intel_crtc->base);
7599
7600         saved_hwmode = crtc->hwmode;
7601         saved_mode = crtc->mode;
7602
7603         /* Hack: Because we don't (yet) support global modeset on multiple
7604          * crtcs, we don't keep track of the new mode for more than one crtc.
7605          * Hence simply check whether any bit is set in modeset_pipes in all the
7606          * pieces of code that are not yet converted to deal with mutliple crtcs
7607          * changing their mode at the same time. */
7608         adjusted_mode = NULL;
7609         if (modeset_pipes) {
7610                 adjusted_mode = intel_modeset_adjusted_mode(crtc, mode);
7611                 if (IS_ERR(adjusted_mode)) {
7612                         return false;
7613                 }
7614         }
7615
7616         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc) {
7617                 if (intel_crtc->base.enabled)
7618                         dev_priv->display.crtc_disable(&intel_crtc->base);
7619         }
7620
7621         /* crtc->mode is already used by the ->mode_set callbacks, hence we need
7622          * to set it here already despite that we pass it down the callchain.
7623          */
7624         if (modeset_pipes)
7625                 crtc->mode = *mode;
7626
7627         /* Only after disabling all output pipelines that will be changed can we
7628          * update the the output configuration. */
7629         intel_modeset_update_state(dev, prepare_pipes);
7630
7631         if (dev_priv->display.modeset_global_resources)
7632                 dev_priv->display.modeset_global_resources(dev);
7633
7634         /* Set up the DPLL and any encoders state that needs to adjust or depend
7635          * on the DPLL.
7636          */
7637         for_each_intel_crtc_masked(dev, modeset_pipes, intel_crtc) {
7638                 ret = !intel_crtc_mode_set(&intel_crtc->base,
7639                                            mode, adjusted_mode,
7640                                            x, y, fb);
7641                 if (!ret)
7642                     goto done;
7643         }
7644
7645         /* Now enable the clocks, plane, pipe, and connectors that we set up. */
7646         for_each_intel_crtc_masked(dev, prepare_pipes, intel_crtc)
7647                 dev_priv->display.crtc_enable(&intel_crtc->base);
7648
7649         if (modeset_pipes) {
7650                 /* Store real post-adjustment hardware mode. */
7651                 crtc->hwmode = *adjusted_mode;
7652
7653                 /* Calculate and store various constants which
7654                  * are later needed by vblank and swap-completion
7655                  * timestamping. They are derived from true hwmode.
7656                  */
7657                 drm_calc_timestamping_constants(crtc);
7658         }
7659
7660         /* FIXME: add subpixel order */
7661 done:
7662         drm_mode_destroy(dev, adjusted_mode);
7663         if (!ret && crtc->enabled) {
7664                 crtc->hwmode = saved_hwmode;
7665                 crtc->mode = saved_mode;
7666         } else {
7667                 intel_modeset_check_state(dev);
7668         }
7669
7670         return ret;
7671 }
7672
7673 #undef for_each_intel_crtc_masked
7674
7675 static void intel_set_config_free(struct intel_set_config *config)
7676 {
7677         if (!config)
7678                 return;
7679
7680         kfree(config->save_connector_encoders);
7681         kfree(config->save_encoder_crtcs);
7682         kfree(config);
7683 }
7684
7685 static int intel_set_config_save_state(struct drm_device *dev,
7686                                        struct intel_set_config *config)
7687 {
7688         struct drm_encoder *encoder;
7689         struct drm_connector *connector;
7690         int count;
7691
7692         config->save_encoder_crtcs =
7693                 kcalloc(dev->mode_config.num_encoder,
7694                         sizeof(struct drm_crtc *), GFP_KERNEL);
7695         if (!config->save_encoder_crtcs)
7696                 return -ENOMEM;
7697
7698         config->save_connector_encoders =
7699                 kcalloc(dev->mode_config.num_connector,
7700                         sizeof(struct drm_encoder *), GFP_KERNEL);
7701         if (!config->save_connector_encoders)
7702                 return -ENOMEM;
7703
7704         /* Copy data. Note that driver private data is not affected.
7705          * Should anything bad happen only the expected state is
7706          * restored, not the drivers personal bookkeeping.
7707          */
7708         count = 0;
7709         list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
7710                 config->save_encoder_crtcs[count++] = encoder->crtc;
7711         }
7712
7713         count = 0;
7714         list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
7715                 config->save_connector_encoders[count++] = connector->encoder;
7716         }
7717
7718         return 0;
7719 }
7720
7721 static void intel_set_config_restore_state(struct drm_device *dev,
7722                                            struct intel_set_config *config)
7723 {
7724         struct intel_encoder *encoder;
7725         struct intel_connector *connector;
7726         int count;
7727
7728         count = 0;
7729         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
7730                 encoder->new_crtc =
7731                         to_intel_crtc(config->save_encoder_crtcs[count++]);
7732         }
7733
7734         count = 0;
7735         list_for_each_entry(connector, &dev->mode_config.connector_list, base.head) {
7736                 connector->new_encoder =
7737                         to_intel_encoder(config->save_connector_encoders[count++]);
7738         }
7739 }
7740
7741 static void
7742 intel_set_config_compute_mode_changes(struct drm_mode_set *set,
7743                                       struct intel_set_config *config)
7744 {
7745
7746         /* We should be able to check here if the fb has the same properties
7747          * and then just flip_or_move it */
7748         if (set->crtc->fb != set->fb) {
7749                 /* If we have no fb then treat it as a full mode set */
7750                 if (set->crtc->fb == NULL) {
7751                         DRM_DEBUG_KMS("crtc has no fb, full mode set\n");
7752                         config->mode_changed = true;
7753                 } else if (set->fb == NULL) {
7754                         config->mode_changed = true;
7755                 } else if (set->fb->depth != set->crtc->fb->depth) {
7756                         config->mode_changed = true;
7757                 } else if (set->fb->bits_per_pixel !=
7758                            set->crtc->fb->bits_per_pixel) {
7759                         config->mode_changed = true;
7760                 } else
7761                         config->fb_changed = true;
7762         }
7763
7764         if (set->fb && (set->x != set->crtc->x || set->y != set->crtc->y))
7765                 config->fb_changed = true;
7766
7767         if (set->mode && !drm_mode_equal(set->mode, &set->crtc->mode)) {
7768                 DRM_DEBUG_KMS("modes are different, full mode set\n");
7769                 drm_mode_debug_printmodeline(&set->crtc->mode);
7770                 drm_mode_debug_printmodeline(set->mode);
7771                 config->mode_changed = true;
7772         }
7773 }
7774
7775 static int
7776 intel_modeset_stage_output_state(struct drm_device *dev,
7777                                  struct drm_mode_set *set,
7778                                  struct intel_set_config *config)
7779 {
7780         struct drm_crtc *new_crtc;
7781         struct intel_connector *connector;
7782         struct intel_encoder *encoder;
7783         int count, ro;
7784
7785         /* The upper layers ensure that we either disabl a crtc or have a list
7786          * of connectors. For paranoia, double-check this. */
7787         WARN_ON(!set->fb && (set->num_connectors != 0));
7788         WARN_ON(set->fb && (set->num_connectors == 0));
7789
7790         count = 0;
7791         list_for_each_entry(connector, &dev->mode_config.connector_list,
7792                             base.head) {
7793                 /* Otherwise traverse passed in connector list and get encoders
7794                  * for them. */
7795                 for (ro = 0; ro < set->num_connectors; ro++) {
7796                         if (set->connectors[ro] == &connector->base) {
7797                                 connector->new_encoder = connector->encoder;
7798                                 break;
7799                         }
7800                 }
7801
7802                 /* If we disable the crtc, disable all its connectors. Also, if
7803                  * the connector is on the changing crtc but not on the new
7804                  * connector list, disable it. */
7805                 if ((!set->fb || ro == set->num_connectors) &&
7806                     connector->base.encoder &&
7807                     connector->base.encoder->crtc == set->crtc) {
7808                         connector->new_encoder = NULL;
7809
7810                         DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [NOCRTC]\n",
7811                                 connector->base.base.id,
7812                                 drm_get_connector_name(&connector->base));
7813                 }
7814
7815
7816                 if (&connector->new_encoder->base != connector->base.encoder) {
7817                         DRM_DEBUG_KMS("encoder changed, full mode switch\n");
7818                         config->mode_changed = true;
7819                 }
7820
7821                 /* Disable all disconnected encoders. */
7822                 if (connector->base.status == connector_status_disconnected)
7823                         connector->new_encoder = NULL;
7824         }
7825         /* connector->new_encoder is now updated for all connectors. */
7826
7827         /* Update crtc of enabled connectors. */
7828         count = 0;
7829         list_for_each_entry(connector, &dev->mode_config.connector_list,
7830                             base.head) {
7831                 if (!connector->new_encoder)
7832                         continue;
7833
7834                 new_crtc = connector->new_encoder->base.crtc;
7835
7836                 for (ro = 0; ro < set->num_connectors; ro++) {
7837                         if (set->connectors[ro] == &connector->base)
7838                                 new_crtc = set->crtc;
7839                 }
7840
7841                 /* Make sure the new CRTC will work with the encoder */
7842                 if (!intel_encoder_crtc_ok(&connector->new_encoder->base,
7843                                            new_crtc)) {
7844                         return -EINVAL;
7845                 }
7846                 connector->encoder->new_crtc = to_intel_crtc(new_crtc);
7847
7848                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] to [CRTC:%d]\n",
7849                         connector->base.base.id,
7850                         drm_get_connector_name(&connector->base),
7851                         new_crtc->base.id);
7852         }
7853
7854         /* Check for any encoders that needs to be disabled. */
7855         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
7856                             base.head) {
7857                 list_for_each_entry(connector,
7858                                     &dev->mode_config.connector_list,
7859                                     base.head) {
7860                         if (connector->new_encoder == encoder) {
7861                                 WARN_ON(!connector->new_encoder->new_crtc);
7862
7863                                 goto next_encoder;
7864                         }
7865                 }
7866                 encoder->new_crtc = NULL;
7867 next_encoder:
7868                 /* Only now check for crtc changes so we don't miss encoders
7869                  * that will be disabled. */
7870                 if (&encoder->new_crtc->base != encoder->base.crtc) {
7871                         DRM_DEBUG_KMS("crtc changed, full mode switch\n");
7872                         config->mode_changed = true;
7873                 }
7874         }
7875         /* Now we've also updated encoder->new_crtc for all encoders. */
7876
7877         return 0;
7878 }
7879
7880 static int intel_crtc_set_config(struct drm_mode_set *set)
7881 {
7882         struct drm_device *dev;
7883         struct drm_mode_set save_set;
7884         struct intel_set_config *config;
7885         int ret;
7886
7887         BUG_ON(!set);
7888         BUG_ON(!set->crtc);
7889         BUG_ON(!set->crtc->helper_private);
7890
7891         if (!set->mode)
7892                 set->fb = NULL;
7893
7894         /* The fb helper likes to play gross jokes with ->mode_set_config.
7895          * Unfortunately the crtc helper doesn't do much at all for this case,
7896          * so we have to cope with this madness until the fb helper is fixed up. */
7897         if (set->fb && set->num_connectors == 0)
7898                 return 0;
7899
7900         if (set->fb) {
7901                 DRM_DEBUG_KMS("[CRTC:%d] [FB:%d] #connectors=%d (x y) (%i %i)\n",
7902                                 set->crtc->base.id, set->fb->base.id,
7903                                 (int)set->num_connectors, set->x, set->y);
7904         } else {
7905                 DRM_DEBUG_KMS("[CRTC:%d] [NOFB]\n", set->crtc->base.id);
7906         }
7907
7908         dev = set->crtc->dev;
7909
7910         ret = -ENOMEM;
7911         config = kzalloc(sizeof(*config), GFP_KERNEL);
7912         if (!config)
7913                 goto out_config;
7914
7915         ret = intel_set_config_save_state(dev, config);
7916         if (ret)
7917                 goto out_config;
7918
7919         save_set.crtc = set->crtc;
7920         save_set.mode = &set->crtc->mode;
7921         save_set.x = set->crtc->x;
7922         save_set.y = set->crtc->y;
7923         save_set.fb = set->crtc->fb;
7924
7925         /* Compute whether we need a full modeset, only an fb base update or no
7926          * change at all. In the future we might also check whether only the
7927          * mode changed, e.g. for LVDS where we only change the panel fitter in
7928          * such cases. */
7929         intel_set_config_compute_mode_changes(set, config);
7930
7931         ret = intel_modeset_stage_output_state(dev, set, config);
7932         if (ret)
7933                 goto fail;
7934
7935         if (config->mode_changed) {
7936                 if (set->mode) {
7937                         DRM_DEBUG_KMS("attempting to set mode from"
7938                                         " userspace\n");
7939                         drm_mode_debug_printmodeline(set->mode);
7940                 }
7941
7942                 if (!intel_set_mode(set->crtc, set->mode,
7943                                     set->x, set->y, set->fb)) {
7944                         DRM_ERROR("failed to set mode on [CRTC:%d]\n",
7945                                   set->crtc->base.id);
7946                         ret = -EINVAL;
7947                         goto fail;
7948                 }
7949         } else if (config->fb_changed) {
7950                 ret = intel_pipe_set_base(set->crtc,
7951                                           set->x, set->y, set->fb);
7952         }
7953
7954         intel_set_config_free(config);
7955
7956         return 0;
7957
7958 fail:
7959         intel_set_config_restore_state(dev, config);
7960
7961         /* Try to restore the config */
7962         if (config->mode_changed &&
7963             !intel_set_mode(save_set.crtc, save_set.mode,
7964                             save_set.x, save_set.y, save_set.fb))
7965                 DRM_ERROR("failed to restore config after modeset failure\n");
7966
7967 out_config:
7968         intel_set_config_free(config);
7969         return ret;
7970 }
7971
7972 static const struct drm_crtc_funcs intel_crtc_funcs = {
7973         .cursor_set = intel_crtc_cursor_set,
7974         .cursor_move = intel_crtc_cursor_move,
7975         .gamma_set = intel_crtc_gamma_set,
7976         .set_config = intel_crtc_set_config,
7977         .destroy = intel_crtc_destroy,
7978         .page_flip = intel_crtc_page_flip,
7979 };
7980
7981 static void intel_cpu_pll_init(struct drm_device *dev)
7982 {
7983         if (IS_HASWELL(dev))
7984                 intel_ddi_pll_init(dev);
7985 }
7986
7987 static void intel_pch_pll_init(struct drm_device *dev)
7988 {
7989         drm_i915_private_t *dev_priv = dev->dev_private;
7990         int i;
7991
7992         if (dev_priv->num_pch_pll == 0) {
7993                 DRM_DEBUG_KMS("No PCH PLLs on this hardware, skipping initialisation\n");
7994                 return;
7995         }
7996
7997         for (i = 0; i < dev_priv->num_pch_pll; i++) {
7998                 dev_priv->pch_plls[i].pll_reg = _PCH_DPLL(i);
7999                 dev_priv->pch_plls[i].fp0_reg = _PCH_FP0(i);
8000                 dev_priv->pch_plls[i].fp1_reg = _PCH_FP1(i);
8001         }
8002 }
8003
8004 static void intel_crtc_init(struct drm_device *dev, int pipe)
8005 {
8006         drm_i915_private_t *dev_priv = dev->dev_private;
8007         struct intel_crtc *intel_crtc;
8008         int i;
8009
8010         intel_crtc = kzalloc(sizeof(struct intel_crtc) + (INTELFB_CONN_LIMIT * sizeof(struct drm_connector *)), GFP_KERNEL);
8011         if (intel_crtc == NULL)
8012                 return;
8013
8014         drm_crtc_init(dev, &intel_crtc->base, &intel_crtc_funcs);
8015
8016         drm_mode_crtc_set_gamma_size(&intel_crtc->base, 256);
8017         for (i = 0; i < 256; i++) {
8018                 intel_crtc->lut_r[i] = i;
8019                 intel_crtc->lut_g[i] = i;
8020                 intel_crtc->lut_b[i] = i;
8021         }
8022
8023         /* Swap pipes & planes for FBC on pre-965 */
8024         intel_crtc->pipe = pipe;
8025         intel_crtc->plane = pipe;
8026         intel_crtc->cpu_transcoder = pipe;
8027         if (IS_MOBILE(dev) && IS_GEN3(dev)) {
8028                 DRM_DEBUG_KMS("swapping pipes & planes for FBC\n");
8029                 intel_crtc->plane = !pipe;
8030         }
8031
8032         BUG_ON(pipe >= ARRAY_SIZE(dev_priv->plane_to_crtc_mapping) ||
8033                dev_priv->plane_to_crtc_mapping[intel_crtc->plane] != NULL);
8034         dev_priv->plane_to_crtc_mapping[intel_crtc->plane] = &intel_crtc->base;
8035         dev_priv->pipe_to_crtc_mapping[intel_crtc->pipe] = &intel_crtc->base;
8036
8037         intel_crtc->bpp = 24; /* default for pre-Ironlake */
8038
8039         drm_crtc_helper_add(&intel_crtc->base, &intel_helper_funcs);
8040 }
8041
8042 int intel_get_pipe_from_crtc_id(struct drm_device *dev, void *data,
8043                                 struct drm_file *file)
8044 {
8045         struct drm_i915_get_pipe_from_crtc_id *pipe_from_crtc_id = data;
8046         struct drm_mode_object *drmmode_obj;
8047         struct intel_crtc *crtc;
8048
8049         if (!drm_core_check_feature(dev, DRIVER_MODESET))
8050                 return -ENODEV;
8051
8052         drmmode_obj = drm_mode_object_find(dev, pipe_from_crtc_id->crtc_id,
8053                         DRM_MODE_OBJECT_CRTC);
8054
8055         if (!drmmode_obj) {
8056                 DRM_ERROR("no such CRTC id\n");
8057                 return -EINVAL;
8058         }
8059
8060         crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
8061         pipe_from_crtc_id->pipe = crtc->pipe;
8062
8063         return 0;
8064 }
8065
8066 static int intel_encoder_clones(struct intel_encoder *encoder)
8067 {
8068         struct drm_device *dev = encoder->base.dev;
8069         struct intel_encoder *source_encoder;
8070         int index_mask = 0;
8071         int entry = 0;
8072
8073         list_for_each_entry(source_encoder,
8074                             &dev->mode_config.encoder_list, base.head) {
8075
8076                 if (encoder == source_encoder)
8077                         index_mask |= (1 << entry);
8078
8079                 /* Intel hw has only one MUX where enocoders could be cloned. */
8080                 if (encoder->cloneable && source_encoder->cloneable)
8081                         index_mask |= (1 << entry);
8082
8083                 entry++;
8084         }
8085
8086         return index_mask;
8087 }
8088
8089 static bool has_edp_a(struct drm_device *dev)
8090 {
8091         struct drm_i915_private *dev_priv = dev->dev_private;
8092
8093         if (!IS_MOBILE(dev))
8094                 return false;
8095
8096         if ((I915_READ(DP_A) & DP_DETECTED) == 0)
8097                 return false;
8098
8099         if (IS_GEN5(dev) &&
8100             (I915_READ(ILK_DISPLAY_CHICKEN_FUSES) & ILK_eDP_A_DISABLE))
8101                 return false;
8102
8103         return true;
8104 }
8105
8106 static void intel_setup_outputs(struct drm_device *dev)
8107 {
8108         struct drm_i915_private *dev_priv = dev->dev_private;
8109         struct intel_encoder *encoder;
8110         bool dpd_is_edp = false;
8111         bool has_lvds;
8112
8113         has_lvds = intel_lvds_init(dev);
8114         if (!has_lvds && !HAS_PCH_SPLIT(dev)) {
8115                 /* disable the panel fitter on everything but LVDS */
8116                 I915_WRITE(PFIT_CONTROL, 0);
8117         }
8118
8119         if (!(IS_HASWELL(dev) &&
8120               (I915_READ(DDI_BUF_CTL(PORT_A)) & DDI_A_4_LANES)))
8121                 intel_crt_init(dev);
8122
8123         if (IS_HASWELL(dev)) {
8124                 int found;
8125
8126                 /* Haswell uses DDI functions to detect digital outputs */
8127                 found = I915_READ(DDI_BUF_CTL_A) & DDI_INIT_DISPLAY_DETECTED;
8128                 /* DDI A only supports eDP */
8129                 if (found)
8130                         intel_ddi_init(dev, PORT_A);
8131
8132                 /* DDI B, C and D detection is indicated by the SFUSE_STRAP
8133                  * register */
8134                 found = I915_READ(SFUSE_STRAP);
8135
8136                 if (found & SFUSE_STRAP_DDIB_DETECTED)
8137                         intel_ddi_init(dev, PORT_B);
8138                 if (found & SFUSE_STRAP_DDIC_DETECTED)
8139                         intel_ddi_init(dev, PORT_C);
8140                 if (found & SFUSE_STRAP_DDID_DETECTED)
8141                         intel_ddi_init(dev, PORT_D);
8142         } else if (HAS_PCH_SPLIT(dev)) {
8143                 int found;
8144                 dpd_is_edp = intel_dpd_is_edp(dev);
8145
8146                 if (has_edp_a(dev))
8147                         intel_dp_init(dev, DP_A, PORT_A);
8148
8149                 if (I915_READ(HDMIB) & PORT_DETECTED) {
8150                         /* PCH SDVOB multiplex with HDMIB */
8151                         found = intel_sdvo_init(dev, PCH_SDVOB, true);
8152                         if (!found)
8153                                 intel_hdmi_init(dev, HDMIB, PORT_B);
8154                         if (!found && (I915_READ(PCH_DP_B) & DP_DETECTED))
8155                                 intel_dp_init(dev, PCH_DP_B, PORT_B);
8156                 }
8157
8158                 if (I915_READ(HDMIC) & PORT_DETECTED)
8159                         intel_hdmi_init(dev, HDMIC, PORT_C);
8160
8161                 if (!dpd_is_edp && I915_READ(HDMID) & PORT_DETECTED)
8162                         intel_hdmi_init(dev, HDMID, PORT_D);
8163
8164                 if (I915_READ(PCH_DP_C) & DP_DETECTED)
8165                         intel_dp_init(dev, PCH_DP_C, PORT_C);
8166
8167                 if (I915_READ(PCH_DP_D) & DP_DETECTED)
8168                         intel_dp_init(dev, PCH_DP_D, PORT_D);
8169         } else if (IS_VALLEYVIEW(dev)) {
8170                 int found;
8171
8172                 /* Check for built-in panel first. Shares lanes with HDMI on SDVOC */
8173                 if (I915_READ(DP_C) & DP_DETECTED)
8174                         intel_dp_init(dev, DP_C, PORT_C);
8175
8176                 if (I915_READ(SDVOB) & PORT_DETECTED) {
8177                         /* SDVOB multiplex with HDMIB */
8178                         found = intel_sdvo_init(dev, SDVOB, true);
8179                         if (!found)
8180                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8181                         if (!found && (I915_READ(DP_B) & DP_DETECTED))
8182                                 intel_dp_init(dev, DP_B, PORT_B);
8183                 }
8184
8185                 if (I915_READ(SDVOC) & PORT_DETECTED)
8186                         intel_hdmi_init(dev, SDVOC, PORT_C);
8187
8188         } else if (SUPPORTS_DIGITAL_OUTPUTS(dev)) {
8189                 bool found = false;
8190
8191                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8192                         DRM_DEBUG_KMS("probing SDVOB\n");
8193                         found = intel_sdvo_init(dev, SDVOB, true);
8194                         if (!found && SUPPORTS_INTEGRATED_HDMI(dev)) {
8195                                 DRM_DEBUG_KMS("probing HDMI on SDVOB\n");
8196                                 intel_hdmi_init(dev, SDVOB, PORT_B);
8197                         }
8198
8199                         if (!found && SUPPORTS_INTEGRATED_DP(dev)) {
8200                                 DRM_DEBUG_KMS("probing DP_B\n");
8201                                 intel_dp_init(dev, DP_B, PORT_B);
8202                         }
8203                 }
8204
8205                 /* Before G4X SDVOC doesn't have its own detect register */
8206
8207                 if (I915_READ(SDVOB) & SDVO_DETECTED) {
8208                         DRM_DEBUG_KMS("probing SDVOC\n");
8209                         found = intel_sdvo_init(dev, SDVOC, false);
8210                 }
8211
8212                 if (!found && (I915_READ(SDVOC) & SDVO_DETECTED)) {
8213
8214                         if (SUPPORTS_INTEGRATED_HDMI(dev)) {
8215                                 DRM_DEBUG_KMS("probing HDMI on SDVOC\n");
8216                                 intel_hdmi_init(dev, SDVOC, PORT_C);
8217                         }
8218                         if (SUPPORTS_INTEGRATED_DP(dev)) {
8219                                 DRM_DEBUG_KMS("probing DP_C\n");
8220                                 intel_dp_init(dev, DP_C, PORT_C);
8221                         }
8222                 }
8223
8224                 if (SUPPORTS_INTEGRATED_DP(dev) &&
8225                     (I915_READ(DP_D) & DP_DETECTED)) {
8226                         DRM_DEBUG_KMS("probing DP_D\n");
8227                         intel_dp_init(dev, DP_D, PORT_D);
8228                 }
8229         } else if (IS_GEN2(dev))
8230                 intel_dvo_init(dev);
8231
8232         if (SUPPORTS_TV(dev))
8233                 intel_tv_init(dev);
8234
8235         list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.head) {
8236                 encoder->base.possible_crtcs = encoder->crtc_mask;
8237                 encoder->base.possible_clones =
8238                         intel_encoder_clones(encoder);
8239         }
8240
8241         if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
8242                 ironlake_init_pch_refclk(dev);
8243
8244         drm_helper_move_panel_connectors_to_head(dev);
8245 }
8246
8247 static void intel_user_framebuffer_destroy(struct drm_framebuffer *fb)
8248 {
8249         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8250
8251         drm_framebuffer_cleanup(fb);
8252         drm_gem_object_unreference_unlocked(&intel_fb->obj->base);
8253
8254         kfree(intel_fb);
8255 }
8256
8257 static int intel_user_framebuffer_create_handle(struct drm_framebuffer *fb,
8258                                                 struct drm_file *file,
8259                                                 unsigned int *handle)
8260 {
8261         struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
8262         struct drm_i915_gem_object *obj = intel_fb->obj;
8263
8264         return drm_gem_handle_create(file, &obj->base, handle);
8265 }
8266
8267 static const struct drm_framebuffer_funcs intel_fb_funcs = {
8268         .destroy = intel_user_framebuffer_destroy,
8269         .create_handle = intel_user_framebuffer_create_handle,
8270 };
8271
8272 int intel_framebuffer_init(struct drm_device *dev,
8273                            struct intel_framebuffer *intel_fb,
8274                            struct drm_mode_fb_cmd2 *mode_cmd,
8275                            struct drm_i915_gem_object *obj)
8276 {
8277         int ret;
8278
8279         if (obj->tiling_mode == I915_TILING_Y)
8280                 return -EINVAL;
8281
8282         if (mode_cmd->pitches[0] & 63)
8283                 return -EINVAL;
8284
8285         /* FIXME <= Gen4 stride limits are bit unclear */
8286         if (mode_cmd->pitches[0] > 32768)
8287                 return -EINVAL;
8288
8289         if (obj->tiling_mode != I915_TILING_NONE &&
8290             mode_cmd->pitches[0] != obj->stride)
8291                 return -EINVAL;
8292
8293         /* Reject formats not supported by any plane early. */
8294         switch (mode_cmd->pixel_format) {
8295         case DRM_FORMAT_C8:
8296         case DRM_FORMAT_RGB565:
8297         case DRM_FORMAT_XRGB8888:
8298         case DRM_FORMAT_ARGB8888:
8299                 break;
8300         case DRM_FORMAT_XRGB1555:
8301         case DRM_FORMAT_ARGB1555:
8302                 if (INTEL_INFO(dev)->gen > 3)
8303                         return -EINVAL;
8304                 break;
8305         case DRM_FORMAT_XBGR8888:
8306         case DRM_FORMAT_ABGR8888:
8307         case DRM_FORMAT_XRGB2101010:
8308         case DRM_FORMAT_ARGB2101010:
8309         case DRM_FORMAT_XBGR2101010:
8310         case DRM_FORMAT_ABGR2101010:
8311                 if (INTEL_INFO(dev)->gen < 4)
8312                         return -EINVAL;
8313                 break;
8314         case DRM_FORMAT_YUYV:
8315         case DRM_FORMAT_UYVY:
8316         case DRM_FORMAT_YVYU:
8317         case DRM_FORMAT_VYUY:
8318                 if (INTEL_INFO(dev)->gen < 6)
8319                         return -EINVAL;
8320                 break;
8321         default:
8322                 DRM_DEBUG_KMS("unsupported pixel format 0x%08x\n", mode_cmd->pixel_format);
8323                 return -EINVAL;
8324         }
8325
8326         /* FIXME need to adjust LINOFF/TILEOFF accordingly. */
8327         if (mode_cmd->offsets[0] != 0)
8328                 return -EINVAL;
8329
8330         ret = drm_framebuffer_init(dev, &intel_fb->base, &intel_fb_funcs);
8331         if (ret) {
8332                 DRM_ERROR("framebuffer init failed %d\n", ret);
8333                 return ret;
8334         }
8335
8336         drm_helper_mode_fill_fb_struct(&intel_fb->base, mode_cmd);
8337         intel_fb->obj = obj;
8338         return 0;
8339 }
8340
8341 static struct drm_framebuffer *
8342 intel_user_framebuffer_create(struct drm_device *dev,
8343                               struct drm_file *filp,
8344                               struct drm_mode_fb_cmd2 *mode_cmd)
8345 {
8346         struct drm_i915_gem_object *obj;
8347
8348         obj = to_intel_bo(drm_gem_object_lookup(dev, filp,
8349                                                 mode_cmd->handles[0]));
8350         if (&obj->base == NULL)
8351                 return ERR_PTR(-ENOENT);
8352
8353         return intel_framebuffer_create(dev, mode_cmd, obj);
8354 }
8355
8356 static const struct drm_mode_config_funcs intel_mode_funcs = {
8357         .fb_create = intel_user_framebuffer_create,
8358         .output_poll_changed = intel_fb_output_poll_changed,
8359 };
8360
8361 /* Set up chip specific display functions */
8362 static void intel_init_display(struct drm_device *dev)
8363 {
8364         struct drm_i915_private *dev_priv = dev->dev_private;
8365
8366         /* We always want a DPMS function */
8367         if (IS_HASWELL(dev)) {
8368                 dev_priv->display.crtc_mode_set = haswell_crtc_mode_set;
8369                 dev_priv->display.crtc_enable = haswell_crtc_enable;
8370                 dev_priv->display.crtc_disable = haswell_crtc_disable;
8371                 dev_priv->display.off = haswell_crtc_off;
8372                 dev_priv->display.update_plane = ironlake_update_plane;
8373         } else if (HAS_PCH_SPLIT(dev)) {
8374                 dev_priv->display.crtc_mode_set = ironlake_crtc_mode_set;
8375                 dev_priv->display.crtc_enable = ironlake_crtc_enable;
8376                 dev_priv->display.crtc_disable = ironlake_crtc_disable;
8377                 dev_priv->display.off = ironlake_crtc_off;
8378                 dev_priv->display.update_plane = ironlake_update_plane;
8379         } else {
8380                 dev_priv->display.crtc_mode_set = i9xx_crtc_mode_set;
8381                 dev_priv->display.crtc_enable = i9xx_crtc_enable;
8382                 dev_priv->display.crtc_disable = i9xx_crtc_disable;
8383                 dev_priv->display.off = i9xx_crtc_off;
8384                 dev_priv->display.update_plane = i9xx_update_plane;
8385         }
8386
8387         /* Returns the core display clock speed */
8388         if (IS_VALLEYVIEW(dev))
8389                 dev_priv->display.get_display_clock_speed =
8390                         valleyview_get_display_clock_speed;
8391         else if (IS_I945G(dev) || (IS_G33(dev) && !IS_PINEVIEW_M(dev)))
8392                 dev_priv->display.get_display_clock_speed =
8393                         i945_get_display_clock_speed;
8394         else if (IS_I915G(dev))
8395                 dev_priv->display.get_display_clock_speed =
8396                         i915_get_display_clock_speed;
8397         else if (IS_I945GM(dev) || IS_845G(dev) || IS_PINEVIEW_M(dev))
8398                 dev_priv->display.get_display_clock_speed =
8399                         i9xx_misc_get_display_clock_speed;
8400         else if (IS_I915GM(dev))
8401                 dev_priv->display.get_display_clock_speed =
8402                         i915gm_get_display_clock_speed;
8403         else if (IS_I865G(dev))
8404                 dev_priv->display.get_display_clock_speed =
8405                         i865_get_display_clock_speed;
8406         else if (IS_I85X(dev))
8407                 dev_priv->display.get_display_clock_speed =
8408                         i855_get_display_clock_speed;
8409         else /* 852, 830 */
8410                 dev_priv->display.get_display_clock_speed =
8411                         i830_get_display_clock_speed;
8412
8413         if (HAS_PCH_SPLIT(dev)) {
8414                 if (IS_GEN5(dev)) {
8415                         dev_priv->display.fdi_link_train = ironlake_fdi_link_train;
8416                         dev_priv->display.write_eld = ironlake_write_eld;
8417                 } else if (IS_GEN6(dev)) {
8418                         dev_priv->display.fdi_link_train = gen6_fdi_link_train;
8419                         dev_priv->display.write_eld = ironlake_write_eld;
8420                 } else if (IS_IVYBRIDGE(dev)) {
8421                         /* FIXME: detect B0+ stepping and use auto training */
8422                         dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
8423                         dev_priv->display.write_eld = ironlake_write_eld;
8424                         dev_priv->display.modeset_global_resources =
8425                                 ivb_modeset_global_resources;
8426                 } else if (IS_HASWELL(dev)) {
8427                         dev_priv->display.fdi_link_train = hsw_fdi_link_train;
8428                         dev_priv->display.write_eld = haswell_write_eld;
8429                 } else
8430                         dev_priv->display.update_wm = NULL;
8431         } else if (IS_G4X(dev)) {
8432                 dev_priv->display.write_eld = g4x_write_eld;
8433         }
8434
8435         /* Default just returns -ENODEV to indicate unsupported */
8436         dev_priv->display.queue_flip = intel_default_queue_flip;
8437
8438         switch (INTEL_INFO(dev)->gen) {
8439         case 2:
8440                 dev_priv->display.queue_flip = intel_gen2_queue_flip;
8441                 break;
8442
8443         case 3:
8444                 dev_priv->display.queue_flip = intel_gen3_queue_flip;
8445                 break;
8446
8447         case 4:
8448         case 5:
8449                 dev_priv->display.queue_flip = intel_gen4_queue_flip;
8450                 break;
8451
8452         case 6:
8453                 dev_priv->display.queue_flip = intel_gen6_queue_flip;
8454                 break;
8455         case 7:
8456                 dev_priv->display.queue_flip = intel_gen7_queue_flip;
8457                 break;
8458         }
8459 }
8460
8461 /*
8462  * Some BIOSes insist on assuming the GPU's pipe A is enabled at suspend,
8463  * resume, or other times.  This quirk makes sure that's the case for
8464  * affected systems.
8465  */
8466 static void quirk_pipea_force(struct drm_device *dev)
8467 {
8468         struct drm_i915_private *dev_priv = dev->dev_private;
8469
8470         dev_priv->quirks |= QUIRK_PIPEA_FORCE;
8471         DRM_INFO("applying pipe a force quirk\n");
8472 }
8473
8474 /*
8475  * Some machines (Lenovo U160) do not work with SSC on LVDS for some reason
8476  */
8477 static void quirk_ssc_force_disable(struct drm_device *dev)
8478 {
8479         struct drm_i915_private *dev_priv = dev->dev_private;
8480         dev_priv->quirks |= QUIRK_LVDS_SSC_DISABLE;
8481         DRM_INFO("applying lvds SSC disable quirk\n");
8482 }
8483
8484 /*
8485  * A machine (e.g. Acer Aspire 5734Z) may need to invert the panel backlight
8486  * brightness value
8487  */
8488 static void quirk_invert_brightness(struct drm_device *dev)
8489 {
8490         struct drm_i915_private *dev_priv = dev->dev_private;
8491         dev_priv->quirks |= QUIRK_INVERT_BRIGHTNESS;
8492         DRM_INFO("applying inverted panel brightness quirk\n");
8493 }
8494
8495 struct intel_quirk {
8496         int device;
8497         int subsystem_vendor;
8498         int subsystem_device;
8499         void (*hook)(struct drm_device *dev);
8500 };
8501
8502 /* For systems that don't have a meaningful PCI subdevice/subvendor ID */
8503 struct intel_dmi_quirk {
8504         void (*hook)(struct drm_device *dev);
8505         const struct dmi_system_id (*dmi_id_list)[];
8506 };
8507
8508 static int intel_dmi_reverse_brightness(const struct dmi_system_id *id)
8509 {
8510         DRM_INFO("Backlight polarity reversed on %s\n", id->ident);
8511         return 1;
8512 }
8513
8514 static const struct intel_dmi_quirk intel_dmi_quirks[] = {
8515         {
8516                 .dmi_id_list = &(const struct dmi_system_id[]) {
8517                         {
8518                                 .callback = intel_dmi_reverse_brightness,
8519                                 .ident = "NCR Corporation",
8520                                 .matches = {DMI_MATCH(DMI_SYS_VENDOR, "NCR Corporation"),
8521                                             DMI_MATCH(DMI_PRODUCT_NAME, ""),
8522                                 },
8523                         },
8524                         { }  /* terminating entry */
8525                 },
8526                 .hook = quirk_invert_brightness,
8527         },
8528 };
8529
8530 static struct intel_quirk intel_quirks[] = {
8531         /* HP Mini needs pipe A force quirk (LP: #322104) */
8532         { 0x27ae, 0x103c, 0x361a, quirk_pipea_force },
8533
8534         /* Toshiba Protege R-205, S-209 needs pipe A force quirk */
8535         { 0x2592, 0x1179, 0x0001, quirk_pipea_force },
8536
8537         /* ThinkPad T60 needs pipe A force quirk (bug #16494) */
8538         { 0x2782, 0x17aa, 0x201a, quirk_pipea_force },
8539
8540         /* 830/845 need to leave pipe A & dpll A up */
8541         { 0x2562, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8542         { 0x3577, PCI_ANY_ID, PCI_ANY_ID, quirk_pipea_force },
8543
8544         /* Lenovo U160 cannot use SSC on LVDS */
8545         { 0x0046, 0x17aa, 0x3920, quirk_ssc_force_disable },
8546
8547         /* Sony Vaio Y cannot use SSC on LVDS */
8548         { 0x0046, 0x104d, 0x9076, quirk_ssc_force_disable },
8549
8550         /* Acer Aspire 5734Z must invert backlight brightness */
8551         { 0x2a42, 0x1025, 0x0459, quirk_invert_brightness },
8552 };
8553
8554 static void intel_init_quirks(struct drm_device *dev)
8555 {
8556         struct pci_dev *d = dev->pdev;
8557         int i;
8558
8559         for (i = 0; i < ARRAY_SIZE(intel_quirks); i++) {
8560                 struct intel_quirk *q = &intel_quirks[i];
8561
8562                 if (d->device == q->device &&
8563                     (d->subsystem_vendor == q->subsystem_vendor ||
8564                      q->subsystem_vendor == PCI_ANY_ID) &&
8565                     (d->subsystem_device == q->subsystem_device ||
8566                      q->subsystem_device == PCI_ANY_ID))
8567                         q->hook(dev);
8568         }
8569         for (i = 0; i < ARRAY_SIZE(intel_dmi_quirks); i++) {
8570                 if (dmi_check_system(*intel_dmi_quirks[i].dmi_id_list) != 0)
8571                         intel_dmi_quirks[i].hook(dev);
8572         }
8573 }
8574
8575 /* Disable the VGA plane that we never use */
8576 static void i915_disable_vga(struct drm_device *dev)
8577 {
8578         struct drm_i915_private *dev_priv = dev->dev_private;
8579         u8 sr1;
8580         u32 vga_reg;
8581
8582         if (HAS_PCH_SPLIT(dev))
8583                 vga_reg = CPU_VGACNTRL;
8584         else
8585                 vga_reg = VGACNTRL;
8586
8587         vga_get_uninterruptible(dev->pdev, VGA_RSRC_LEGACY_IO);
8588         outb(SR01, VGA_SR_INDEX);
8589         sr1 = inb(VGA_SR_DATA);
8590         outb(sr1 | 1<<5, VGA_SR_DATA);
8591         vga_put(dev->pdev, VGA_RSRC_LEGACY_IO);
8592         udelay(300);
8593
8594         I915_WRITE(vga_reg, VGA_DISP_DISABLE);
8595         POSTING_READ(vga_reg);
8596 }
8597
8598 void intel_modeset_init_hw(struct drm_device *dev)
8599 {
8600         /* We attempt to init the necessary power wells early in the initialization
8601          * time, so the subsystems that expect power to be enabled can work.
8602          */
8603         intel_init_power_wells(dev);
8604
8605         intel_prepare_ddi(dev);
8606
8607         intel_init_clock_gating(dev);
8608
8609         mutex_lock(&dev->struct_mutex);
8610         intel_enable_gt_powersave(dev);
8611         mutex_unlock(&dev->struct_mutex);
8612 }
8613
8614 void intel_modeset_init(struct drm_device *dev)
8615 {
8616         struct drm_i915_private *dev_priv = dev->dev_private;
8617         int i, ret;
8618
8619         drm_mode_config_init(dev);
8620
8621         dev->mode_config.min_width = 0;
8622         dev->mode_config.min_height = 0;
8623
8624         dev->mode_config.preferred_depth = 24;
8625         dev->mode_config.prefer_shadow = 1;
8626
8627         dev->mode_config.funcs = &intel_mode_funcs;
8628
8629         intel_init_quirks(dev);
8630
8631         intel_init_pm(dev);
8632
8633         intel_init_display(dev);
8634
8635         if (IS_GEN2(dev)) {
8636                 dev->mode_config.max_width = 2048;
8637                 dev->mode_config.max_height = 2048;
8638         } else if (IS_GEN3(dev)) {
8639                 dev->mode_config.max_width = 4096;
8640                 dev->mode_config.max_height = 4096;
8641         } else {
8642                 dev->mode_config.max_width = 8192;
8643                 dev->mode_config.max_height = 8192;
8644         }
8645         dev->mode_config.fb_base = dev_priv->mm.gtt_base_addr;
8646
8647         DRM_DEBUG_KMS("%d display pipe%s available.\n",
8648                       dev_priv->num_pipe, dev_priv->num_pipe > 1 ? "s" : "");
8649
8650         for (i = 0; i < dev_priv->num_pipe; i++) {
8651                 intel_crtc_init(dev, i);
8652                 ret = intel_plane_init(dev, i);
8653                 if (ret)
8654                         DRM_DEBUG_KMS("plane %d init failed: %d\n", i, ret);
8655         }
8656
8657         intel_cpu_pll_init(dev);
8658         intel_pch_pll_init(dev);
8659
8660         /* Just disable it once at startup */
8661         i915_disable_vga(dev);
8662         intel_setup_outputs(dev);
8663 }
8664
8665 static void
8666 intel_connector_break_all_links(struct intel_connector *connector)
8667 {
8668         connector->base.dpms = DRM_MODE_DPMS_OFF;
8669         connector->base.encoder = NULL;
8670         connector->encoder->connectors_active = false;
8671         connector->encoder->base.crtc = NULL;
8672 }
8673
8674 static void intel_enable_pipe_a(struct drm_device *dev)
8675 {
8676         struct intel_connector *connector;
8677         struct drm_connector *crt = NULL;
8678         struct intel_load_detect_pipe load_detect_temp;
8679
8680         /* We can't just switch on the pipe A, we need to set things up with a
8681          * proper mode and output configuration. As a gross hack, enable pipe A
8682          * by enabling the load detect pipe once. */
8683         list_for_each_entry(connector,
8684                             &dev->mode_config.connector_list,
8685                             base.head) {
8686                 if (connector->encoder->type == INTEL_OUTPUT_ANALOG) {
8687                         crt = &connector->base;
8688                         break;
8689                 }
8690         }
8691
8692         if (!crt)
8693                 return;
8694
8695         if (intel_get_load_detect_pipe(crt, NULL, &load_detect_temp))
8696                 intel_release_load_detect_pipe(crt, &load_detect_temp);
8697
8698
8699 }
8700
8701 static bool
8702 intel_check_plane_mapping(struct intel_crtc *crtc)
8703 {
8704         struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
8705         u32 reg, val;
8706
8707         if (dev_priv->num_pipe == 1)
8708                 return true;
8709
8710         reg = DSPCNTR(!crtc->plane);
8711         val = I915_READ(reg);
8712
8713         if ((val & DISPLAY_PLANE_ENABLE) &&
8714             (!!(val & DISPPLANE_SEL_PIPE_MASK) == crtc->pipe))
8715                 return false;
8716
8717         return true;
8718 }
8719
8720 static void intel_sanitize_crtc(struct intel_crtc *crtc)
8721 {
8722         struct drm_device *dev = crtc->base.dev;
8723         struct drm_i915_private *dev_priv = dev->dev_private;
8724         u32 reg;
8725
8726         /* Clear any frame start delays used for debugging left by the BIOS */
8727         reg = PIPECONF(crtc->cpu_transcoder);
8728         I915_WRITE(reg, I915_READ(reg) & ~PIPECONF_FRAME_START_DELAY_MASK);
8729
8730         /* We need to sanitize the plane -> pipe mapping first because this will
8731          * disable the crtc (and hence change the state) if it is wrong. Note
8732          * that gen4+ has a fixed plane -> pipe mapping.  */
8733         if (INTEL_INFO(dev)->gen < 4 && !intel_check_plane_mapping(crtc)) {
8734                 struct intel_connector *connector;
8735                 bool plane;
8736
8737                 DRM_DEBUG_KMS("[CRTC:%d] wrong plane connection detected!\n",
8738                               crtc->base.base.id);
8739
8740                 /* Pipe has the wrong plane attached and the plane is active.
8741                  * Temporarily change the plane mapping and disable everything
8742                  * ...  */
8743                 plane = crtc->plane;
8744                 crtc->plane = !plane;
8745                 dev_priv->display.crtc_disable(&crtc->base);
8746                 crtc->plane = plane;
8747
8748                 /* ... and break all links. */
8749                 list_for_each_entry(connector, &dev->mode_config.connector_list,
8750                                     base.head) {
8751                         if (connector->encoder->base.crtc != &crtc->base)
8752                                 continue;
8753
8754                         intel_connector_break_all_links(connector);
8755                 }
8756
8757                 WARN_ON(crtc->active);
8758                 crtc->base.enabled = false;
8759         }
8760
8761         if (dev_priv->quirks & QUIRK_PIPEA_FORCE &&
8762             crtc->pipe == PIPE_A && !crtc->active) {
8763                 /* BIOS forgot to enable pipe A, this mostly happens after
8764                  * resume. Force-enable the pipe to fix this, the update_dpms
8765                  * call below we restore the pipe to the right state, but leave
8766                  * the required bits on. */
8767                 intel_enable_pipe_a(dev);
8768         }
8769
8770         /* Adjust the state of the output pipe according to whether we
8771          * have active connectors/encoders. */
8772         intel_crtc_update_dpms(&crtc->base);
8773
8774         if (crtc->active != crtc->base.enabled) {
8775                 struct intel_encoder *encoder;
8776
8777                 /* This can happen either due to bugs in the get_hw_state
8778                  * functions or because the pipe is force-enabled due to the
8779                  * pipe A quirk. */
8780                 DRM_DEBUG_KMS("[CRTC:%d] hw state adjusted, was %s, now %s\n",
8781                               crtc->base.base.id,
8782                               crtc->base.enabled ? "enabled" : "disabled",
8783                               crtc->active ? "enabled" : "disabled");
8784
8785                 crtc->base.enabled = crtc->active;
8786
8787                 /* Because we only establish the connector -> encoder ->
8788                  * crtc links if something is active, this means the
8789                  * crtc is now deactivated. Break the links. connector
8790                  * -> encoder links are only establish when things are
8791                  *  actually up, hence no need to break them. */
8792                 WARN_ON(crtc->active);
8793
8794                 for_each_encoder_on_crtc(dev, &crtc->base, encoder) {
8795                         WARN_ON(encoder->connectors_active);
8796                         encoder->base.crtc = NULL;
8797                 }
8798         }
8799 }
8800
8801 static void intel_sanitize_encoder(struct intel_encoder *encoder)
8802 {
8803         struct intel_connector *connector;
8804         struct drm_device *dev = encoder->base.dev;
8805
8806         /* We need to check both for a crtc link (meaning that the
8807          * encoder is active and trying to read from a pipe) and the
8808          * pipe itself being active. */
8809         bool has_active_crtc = encoder->base.crtc &&
8810                 to_intel_crtc(encoder->base.crtc)->active;
8811
8812         if (encoder->connectors_active && !has_active_crtc) {
8813                 DRM_DEBUG_KMS("[ENCODER:%d:%s] has active connectors but no active pipe!\n",
8814                               encoder->base.base.id,
8815                               drm_get_encoder_name(&encoder->base));
8816
8817                 /* Connector is active, but has no active pipe. This is
8818                  * fallout from our resume register restoring. Disable
8819                  * the encoder manually again. */
8820                 if (encoder->base.crtc) {
8821                         DRM_DEBUG_KMS("[ENCODER:%d:%s] manually disabled\n",
8822                                       encoder->base.base.id,
8823                                       drm_get_encoder_name(&encoder->base));
8824                         encoder->disable(encoder);
8825                 }
8826
8827                 /* Inconsistent output/port/pipe state happens presumably due to
8828                  * a bug in one of the get_hw_state functions. Or someplace else
8829                  * in our code, like the register restore mess on resume. Clamp
8830                  * things to off as a safer default. */
8831                 list_for_each_entry(connector,
8832                                     &dev->mode_config.connector_list,
8833                                     base.head) {
8834                         if (connector->encoder != encoder)
8835                                 continue;
8836
8837                         intel_connector_break_all_links(connector);
8838                 }
8839         }
8840         /* Enabled encoders without active connectors will be fixed in
8841          * the crtc fixup. */
8842 }
8843
8844 /* Scan out the current hw modeset state, sanitizes it and maps it into the drm
8845  * and i915 state tracking structures. */
8846 void intel_modeset_setup_hw_state(struct drm_device *dev,
8847                                   bool force_restore)
8848 {
8849         struct drm_i915_private *dev_priv = dev->dev_private;
8850         enum pipe pipe;
8851         u32 tmp;
8852         struct intel_crtc *crtc;
8853         struct intel_encoder *encoder;
8854         struct intel_connector *connector;
8855
8856         if (IS_HASWELL(dev)) {
8857                 tmp = I915_READ(TRANS_DDI_FUNC_CTL(TRANSCODER_EDP));
8858
8859                 if (tmp & TRANS_DDI_FUNC_ENABLE) {
8860                         switch (tmp & TRANS_DDI_EDP_INPUT_MASK) {
8861                         case TRANS_DDI_EDP_INPUT_A_ON:
8862                         case TRANS_DDI_EDP_INPUT_A_ONOFF:
8863                                 pipe = PIPE_A;
8864                                 break;
8865                         case TRANS_DDI_EDP_INPUT_B_ONOFF:
8866                                 pipe = PIPE_B;
8867                                 break;
8868                         case TRANS_DDI_EDP_INPUT_C_ONOFF:
8869                                 pipe = PIPE_C;
8870                                 break;
8871                         }
8872
8873                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8874                         crtc->cpu_transcoder = TRANSCODER_EDP;
8875
8876                         DRM_DEBUG_KMS("Pipe %c using transcoder EDP\n",
8877                                       pipe_name(pipe));
8878                 }
8879         }
8880
8881         for_each_pipe(pipe) {
8882                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8883
8884                 tmp = I915_READ(PIPECONF(crtc->cpu_transcoder));
8885                 if (tmp & PIPECONF_ENABLE)
8886                         crtc->active = true;
8887                 else
8888                         crtc->active = false;
8889
8890                 crtc->base.enabled = crtc->active;
8891
8892                 DRM_DEBUG_KMS("[CRTC:%d] hw state readout: %s\n",
8893                               crtc->base.base.id,
8894                               crtc->active ? "enabled" : "disabled");
8895         }
8896
8897         if (IS_HASWELL(dev))
8898                 intel_ddi_setup_hw_pll_state(dev);
8899
8900         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8901                             base.head) {
8902                 pipe = 0;
8903
8904                 if (encoder->get_hw_state(encoder, &pipe)) {
8905                         encoder->base.crtc =
8906                                 dev_priv->pipe_to_crtc_mapping[pipe];
8907                 } else {
8908                         encoder->base.crtc = NULL;
8909                 }
8910
8911                 encoder->connectors_active = false;
8912                 DRM_DEBUG_KMS("[ENCODER:%d:%s] hw state readout: %s, pipe=%i\n",
8913                               encoder->base.base.id,
8914                               drm_get_encoder_name(&encoder->base),
8915                               encoder->base.crtc ? "enabled" : "disabled",
8916                               pipe);
8917         }
8918
8919         list_for_each_entry(connector, &dev->mode_config.connector_list,
8920                             base.head) {
8921                 if (connector->get_hw_state(connector)) {
8922                         connector->base.dpms = DRM_MODE_DPMS_ON;
8923                         connector->encoder->connectors_active = true;
8924                         connector->base.encoder = &connector->encoder->base;
8925                 } else {
8926                         connector->base.dpms = DRM_MODE_DPMS_OFF;
8927                         connector->base.encoder = NULL;
8928                 }
8929                 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] hw state readout: %s\n",
8930                               connector->base.base.id,
8931                               drm_get_connector_name(&connector->base),
8932                               connector->base.encoder ? "enabled" : "disabled");
8933         }
8934
8935         /* HW state is read out, now we need to sanitize this mess. */
8936         list_for_each_entry(encoder, &dev->mode_config.encoder_list,
8937                             base.head) {
8938                 intel_sanitize_encoder(encoder);
8939         }
8940
8941         for_each_pipe(pipe) {
8942                 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8943                 intel_sanitize_crtc(crtc);
8944         }
8945
8946         if (force_restore) {
8947                 for_each_pipe(pipe) {
8948                         crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
8949                         intel_set_mode(&crtc->base, &crtc->base.mode,
8950                                        crtc->base.x, crtc->base.y, crtc->base.fb);
8951                 }
8952         } else {
8953                 intel_modeset_update_staged_output_state(dev);
8954         }
8955
8956         intel_modeset_check_state(dev);
8957
8958         drm_mode_config_reset(dev);
8959 }
8960
8961 void intel_modeset_gem_init(struct drm_device *dev)
8962 {
8963         intel_modeset_init_hw(dev);
8964
8965         intel_setup_overlay(dev);
8966
8967         intel_modeset_setup_hw_state(dev, false);
8968 }
8969
8970 void intel_modeset_cleanup(struct drm_device *dev)
8971 {
8972         struct drm_i915_private *dev_priv = dev->dev_private;
8973         struct drm_crtc *crtc;
8974         struct intel_crtc *intel_crtc;
8975
8976         drm_kms_helper_poll_fini(dev);
8977         mutex_lock(&dev->struct_mutex);
8978
8979         intel_unregister_dsm_handler();
8980
8981
8982         list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
8983                 /* Skip inactive CRTCs */
8984                 if (!crtc->fb)
8985                         continue;
8986
8987                 intel_crtc = to_intel_crtc(crtc);
8988                 intel_increase_pllclock(crtc);
8989         }
8990
8991         intel_disable_fbc(dev);
8992
8993         intel_disable_gt_powersave(dev);
8994
8995         ironlake_teardown_rc6(dev);
8996
8997         if (IS_VALLEYVIEW(dev))
8998                 vlv_init_dpio(dev);
8999
9000         mutex_unlock(&dev->struct_mutex);
9001
9002         /* Disable the irq before mode object teardown, for the irq might
9003          * enqueue unpin/hotplug work. */
9004         drm_irq_uninstall(dev);
9005         cancel_work_sync(&dev_priv->hotplug_work);
9006         cancel_work_sync(&dev_priv->rps.work);
9007
9008         /* flush any delayed tasks or pending work */
9009         flush_scheduled_work();
9010
9011         drm_mode_config_cleanup(dev);
9012 }
9013
9014 /*
9015  * Return which encoder is currently attached for connector.
9016  */
9017 struct drm_encoder *intel_best_encoder(struct drm_connector *connector)
9018 {
9019         return &intel_attached_encoder(connector)->base;
9020 }
9021
9022 void intel_connector_attach_encoder(struct intel_connector *connector,
9023                                     struct intel_encoder *encoder)
9024 {
9025         connector->encoder = encoder;
9026         drm_mode_connector_attach_encoder(&connector->base,
9027                                           &encoder->base);
9028 }
9029
9030 /*
9031  * set vga decode state - true == enable VGA decode
9032  */
9033 int intel_modeset_vga_set_state(struct drm_device *dev, bool state)
9034 {
9035         struct drm_i915_private *dev_priv = dev->dev_private;
9036         u16 gmch_ctrl;
9037
9038         pci_read_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, &gmch_ctrl);
9039         if (state)
9040                 gmch_ctrl &= ~INTEL_GMCH_VGA_DISABLE;
9041         else
9042                 gmch_ctrl |= INTEL_GMCH_VGA_DISABLE;
9043         pci_write_config_word(dev_priv->bridge_dev, INTEL_GMCH_CTRL, gmch_ctrl);
9044         return 0;
9045 }
9046
9047 #ifdef CONFIG_DEBUG_FS
9048 #include <linux/seq_file.h>
9049
9050 struct intel_display_error_state {
9051         struct intel_cursor_error_state {
9052                 u32 control;
9053                 u32 position;
9054                 u32 base;
9055                 u32 size;
9056         } cursor[I915_MAX_PIPES];
9057
9058         struct intel_pipe_error_state {
9059                 u32 conf;
9060                 u32 source;
9061
9062                 u32 htotal;
9063                 u32 hblank;
9064                 u32 hsync;
9065                 u32 vtotal;
9066                 u32 vblank;
9067                 u32 vsync;
9068         } pipe[I915_MAX_PIPES];
9069
9070         struct intel_plane_error_state {
9071                 u32 control;
9072                 u32 stride;
9073                 u32 size;
9074                 u32 pos;
9075                 u32 addr;
9076                 u32 surface;
9077                 u32 tile_offset;
9078         } plane[I915_MAX_PIPES];
9079 };
9080
9081 struct intel_display_error_state *
9082 intel_display_capture_error_state(struct drm_device *dev)
9083 {
9084         drm_i915_private_t *dev_priv = dev->dev_private;
9085         struct intel_display_error_state *error;
9086         enum transcoder cpu_transcoder;
9087         int i;
9088
9089         error = kmalloc(sizeof(*error), GFP_ATOMIC);
9090         if (error == NULL)
9091                 return NULL;
9092
9093         for_each_pipe(i) {
9094                 cpu_transcoder = intel_pipe_to_cpu_transcoder(dev_priv, i);
9095
9096                 error->cursor[i].control = I915_READ(CURCNTR(i));
9097                 error->cursor[i].position = I915_READ(CURPOS(i));
9098                 error->cursor[i].base = I915_READ(CURBASE(i));
9099
9100                 error->plane[i].control = I915_READ(DSPCNTR(i));
9101                 error->plane[i].stride = I915_READ(DSPSTRIDE(i));
9102                 error->plane[i].size = I915_READ(DSPSIZE(i));
9103                 error->plane[i].pos = I915_READ(DSPPOS(i));
9104                 error->plane[i].addr = I915_READ(DSPADDR(i));
9105                 if (INTEL_INFO(dev)->gen >= 4) {
9106                         error->plane[i].surface = I915_READ(DSPSURF(i));
9107                         error->plane[i].tile_offset = I915_READ(DSPTILEOFF(i));
9108                 }
9109
9110                 error->pipe[i].conf = I915_READ(PIPECONF(cpu_transcoder));
9111                 error->pipe[i].source = I915_READ(PIPESRC(i));
9112                 error->pipe[i].htotal = I915_READ(HTOTAL(cpu_transcoder));
9113                 error->pipe[i].hblank = I915_READ(HBLANK(cpu_transcoder));
9114                 error->pipe[i].hsync = I915_READ(HSYNC(cpu_transcoder));
9115                 error->pipe[i].vtotal = I915_READ(VTOTAL(cpu_transcoder));
9116                 error->pipe[i].vblank = I915_READ(VBLANK(cpu_transcoder));
9117                 error->pipe[i].vsync = I915_READ(VSYNC(cpu_transcoder));
9118         }
9119
9120         return error;
9121 }
9122
9123 void
9124 intel_display_print_error_state(struct seq_file *m,
9125                                 struct drm_device *dev,
9126                                 struct intel_display_error_state *error)
9127 {
9128         drm_i915_private_t *dev_priv = dev->dev_private;
9129         int i;
9130
9131         seq_printf(m, "Num Pipes: %d\n", dev_priv->num_pipe);
9132         for_each_pipe(i) {
9133                 seq_printf(m, "Pipe [%d]:\n", i);
9134                 seq_printf(m, "  CONF: %08x\n", error->pipe[i].conf);
9135                 seq_printf(m, "  SRC: %08x\n", error->pipe[i].source);
9136                 seq_printf(m, "  HTOTAL: %08x\n", error->pipe[i].htotal);
9137                 seq_printf(m, "  HBLANK: %08x\n", error->pipe[i].hblank);
9138                 seq_printf(m, "  HSYNC: %08x\n", error->pipe[i].hsync);
9139                 seq_printf(m, "  VTOTAL: %08x\n", error->pipe[i].vtotal);
9140                 seq_printf(m, "  VBLANK: %08x\n", error->pipe[i].vblank);
9141                 seq_printf(m, "  VSYNC: %08x\n", error->pipe[i].vsync);
9142
9143                 seq_printf(m, "Plane [%d]:\n", i);
9144                 seq_printf(m, "  CNTR: %08x\n", error->plane[i].control);
9145                 seq_printf(m, "  STRIDE: %08x\n", error->plane[i].stride);
9146                 seq_printf(m, "  SIZE: %08x\n", error->plane[i].size);
9147                 seq_printf(m, "  POS: %08x\n", error->plane[i].pos);
9148                 seq_printf(m, "  ADDR: %08x\n", error->plane[i].addr);
9149                 if (INTEL_INFO(dev)->gen >= 4) {
9150                         seq_printf(m, "  SURF: %08x\n", error->plane[i].surface);
9151                         seq_printf(m, "  TILEOFF: %08x\n", error->plane[i].tile_offset);
9152                 }
9153
9154                 seq_printf(m, "Cursor [%d]:\n", i);
9155                 seq_printf(m, "  CNTR: %08x\n", error->cursor[i].control);
9156                 seq_printf(m, "  POS: %08x\n", error->cursor[i].position);
9157                 seq_printf(m, "  BASE: %08x\n", error->cursor[i].base);
9158         }
9159 }
9160 #endif