2 * Copyright 2008 Advanced Micro Devices, Inc.
3 * Copyright 2008 Red Hat Inc.
4 * Copyright 2009 Jerome Glisse.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
22 * OTHER DEALINGS IN THE SOFTWARE.
24 * Authors: Dave Airlie
29 #include <linux/console.h>
31 #include <drm/drm_crtc_helper.h>
32 #include <drm/radeon_drm.h>
33 #include <linux/vgaarb.h>
34 #include <linux/vga_switcheroo.h>
35 #include "radeon_reg.h"
37 #include "radeon_asic.h"
41 * Registers accessors functions.
44 * radeon_invalid_rreg - dummy reg read function
46 * @rdev: radeon device pointer
47 * @reg: offset of register
49 * Dummy register read function. Used for register blocks
50 * that certain asics don't have (all asics).
51 * Returns the value in the register.
53 static uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg)
55 DRM_ERROR("Invalid callback to read register 0x%04X\n", reg);
61 * radeon_invalid_wreg - dummy reg write function
63 * @rdev: radeon device pointer
64 * @reg: offset of register
65 * @v: value to write to the register
67 * Dummy register read function. Used for register blocks
68 * that certain asics don't have (all asics).
70 static void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v)
72 DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n",
78 * radeon_register_accessor_init - sets up the register accessor callbacks
80 * @rdev: radeon device pointer
82 * Sets up the register accessor callbacks for various register
83 * apertures. Not all asics have all apertures (all asics).
85 static void radeon_register_accessor_init(struct radeon_device *rdev)
87 rdev->mc_rreg = &radeon_invalid_rreg;
88 rdev->mc_wreg = &radeon_invalid_wreg;
89 rdev->pll_rreg = &radeon_invalid_rreg;
90 rdev->pll_wreg = &radeon_invalid_wreg;
91 rdev->pciep_rreg = &radeon_invalid_rreg;
92 rdev->pciep_wreg = &radeon_invalid_wreg;
94 /* Don't change order as we are overridding accessor. */
95 if (rdev->family < CHIP_RV515) {
96 rdev->pcie_reg_mask = 0xff;
98 rdev->pcie_reg_mask = 0x7ff;
100 /* FIXME: not sure here */
101 if (rdev->family <= CHIP_R580) {
102 rdev->pll_rreg = &r100_pll_rreg;
103 rdev->pll_wreg = &r100_pll_wreg;
105 if (rdev->family >= CHIP_R420) {
106 rdev->mc_rreg = &r420_mc_rreg;
107 rdev->mc_wreg = &r420_mc_wreg;
109 if (rdev->family >= CHIP_RV515) {
110 rdev->mc_rreg = &rv515_mc_rreg;
111 rdev->mc_wreg = &rv515_mc_wreg;
113 if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) {
114 rdev->mc_rreg = &rs400_mc_rreg;
115 rdev->mc_wreg = &rs400_mc_wreg;
117 if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) {
118 rdev->mc_rreg = &rs690_mc_rreg;
119 rdev->mc_wreg = &rs690_mc_wreg;
121 if (rdev->family == CHIP_RS600) {
122 rdev->mc_rreg = &rs600_mc_rreg;
123 rdev->mc_wreg = &rs600_mc_wreg;
125 if (rdev->family == CHIP_RS780 || rdev->family == CHIP_RS880) {
126 rdev->mc_rreg = &rs780_mc_rreg;
127 rdev->mc_wreg = &rs780_mc_wreg;
130 if (rdev->family >= CHIP_BONAIRE) {
131 rdev->pciep_rreg = &cik_pciep_rreg;
132 rdev->pciep_wreg = &cik_pciep_wreg;
133 } else if (rdev->family >= CHIP_R600) {
134 rdev->pciep_rreg = &r600_pciep_rreg;
135 rdev->pciep_wreg = &r600_pciep_wreg;
140 /* helper to disable agp */
142 * radeon_agp_disable - AGP disable helper function
144 * @rdev: radeon device pointer
146 * Removes AGP flags and changes the gart callbacks on AGP
147 * cards when using the internal gart rather than AGP (all asics).
149 void radeon_agp_disable(struct radeon_device *rdev)
151 rdev->flags &= ~RADEON_IS_AGP;
152 if (rdev->family >= CHIP_R600) {
153 DRM_INFO("Forcing AGP to PCIE mode\n");
154 rdev->flags |= RADEON_IS_PCIE;
155 } else if (rdev->family >= CHIP_RV515 ||
156 rdev->family == CHIP_RV380 ||
157 rdev->family == CHIP_RV410 ||
158 rdev->family == CHIP_R423) {
159 DRM_INFO("Forcing AGP to PCIE mode\n");
160 rdev->flags |= RADEON_IS_PCIE;
161 rdev->asic->gart.tlb_flush = &rv370_pcie_gart_tlb_flush;
162 rdev->asic->gart.set_page = &rv370_pcie_gart_set_page;
164 DRM_INFO("Forcing AGP to PCI mode\n");
165 rdev->flags |= RADEON_IS_PCI;
166 rdev->asic->gart.tlb_flush = &r100_pci_gart_tlb_flush;
167 rdev->asic->gart.set_page = &r100_pci_gart_set_page;
169 rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024;
175 static struct radeon_asic r100_asic = {
178 .suspend = &r100_suspend,
179 .resume = &r100_resume,
180 .vga_set_state = &r100_vga_set_state,
181 .asic_reset = &r100_asic_reset,
182 .ioctl_wait_idle = NULL,
183 .gui_idle = &r100_gui_idle,
184 .mc_wait_for_idle = &r100_mc_wait_for_idle,
186 .tlb_flush = &r100_pci_gart_tlb_flush,
187 .set_page = &r100_pci_gart_set_page,
190 [RADEON_RING_TYPE_GFX_INDEX] = {
191 .ib_execute = &r100_ring_ib_execute,
192 .emit_fence = &r100_fence_ring_emit,
193 .emit_semaphore = &r100_semaphore_ring_emit,
194 .cs_parse = &r100_cs_parse,
195 .ring_start = &r100_ring_start,
196 .ring_test = &r100_ring_test,
197 .ib_test = &r100_ib_test,
198 .is_lockup = &r100_gpu_is_lockup,
199 .get_rptr = &radeon_ring_generic_get_rptr,
200 .get_wptr = &radeon_ring_generic_get_wptr,
201 .set_wptr = &radeon_ring_generic_set_wptr,
205 .set = &r100_irq_set,
206 .process = &r100_irq_process,
209 .bandwidth_update = &r100_bandwidth_update,
210 .get_vblank_counter = &r100_get_vblank_counter,
211 .wait_for_vblank = &r100_wait_for_vblank,
212 .set_backlight_level = &radeon_legacy_set_backlight_level,
213 .get_backlight_level = &radeon_legacy_get_backlight_level,
216 .blit = &r100_copy_blit,
217 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
219 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
220 .copy = &r100_copy_blit,
221 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
224 .set_reg = r100_set_surface_reg,
225 .clear_reg = r100_clear_surface_reg,
228 .init = &r100_hpd_init,
229 .fini = &r100_hpd_fini,
230 .sense = &r100_hpd_sense,
231 .set_polarity = &r100_hpd_set_polarity,
234 .misc = &r100_pm_misc,
235 .prepare = &r100_pm_prepare,
236 .finish = &r100_pm_finish,
237 .init_profile = &r100_pm_init_profile,
238 .get_dynpm_state = &r100_pm_get_dynpm_state,
239 .get_engine_clock = &radeon_legacy_get_engine_clock,
240 .set_engine_clock = &radeon_legacy_set_engine_clock,
241 .get_memory_clock = &radeon_legacy_get_memory_clock,
242 .set_memory_clock = NULL,
243 .get_pcie_lanes = NULL,
244 .set_pcie_lanes = NULL,
245 .set_clock_gating = &radeon_legacy_set_clock_gating,
248 .pre_page_flip = &r100_pre_page_flip,
249 .page_flip = &r100_page_flip,
250 .post_page_flip = &r100_post_page_flip,
254 static struct radeon_asic r200_asic = {
257 .suspend = &r100_suspend,
258 .resume = &r100_resume,
259 .vga_set_state = &r100_vga_set_state,
260 .asic_reset = &r100_asic_reset,
261 .ioctl_wait_idle = NULL,
262 .gui_idle = &r100_gui_idle,
263 .mc_wait_for_idle = &r100_mc_wait_for_idle,
265 .tlb_flush = &r100_pci_gart_tlb_flush,
266 .set_page = &r100_pci_gart_set_page,
269 [RADEON_RING_TYPE_GFX_INDEX] = {
270 .ib_execute = &r100_ring_ib_execute,
271 .emit_fence = &r100_fence_ring_emit,
272 .emit_semaphore = &r100_semaphore_ring_emit,
273 .cs_parse = &r100_cs_parse,
274 .ring_start = &r100_ring_start,
275 .ring_test = &r100_ring_test,
276 .ib_test = &r100_ib_test,
277 .is_lockup = &r100_gpu_is_lockup,
278 .get_rptr = &radeon_ring_generic_get_rptr,
279 .get_wptr = &radeon_ring_generic_get_wptr,
280 .set_wptr = &radeon_ring_generic_set_wptr,
284 .set = &r100_irq_set,
285 .process = &r100_irq_process,
288 .bandwidth_update = &r100_bandwidth_update,
289 .get_vblank_counter = &r100_get_vblank_counter,
290 .wait_for_vblank = &r100_wait_for_vblank,
291 .set_backlight_level = &radeon_legacy_set_backlight_level,
292 .get_backlight_level = &radeon_legacy_get_backlight_level,
295 .blit = &r100_copy_blit,
296 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
297 .dma = &r200_copy_dma,
298 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
299 .copy = &r100_copy_blit,
300 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
303 .set_reg = r100_set_surface_reg,
304 .clear_reg = r100_clear_surface_reg,
307 .init = &r100_hpd_init,
308 .fini = &r100_hpd_fini,
309 .sense = &r100_hpd_sense,
310 .set_polarity = &r100_hpd_set_polarity,
313 .misc = &r100_pm_misc,
314 .prepare = &r100_pm_prepare,
315 .finish = &r100_pm_finish,
316 .init_profile = &r100_pm_init_profile,
317 .get_dynpm_state = &r100_pm_get_dynpm_state,
318 .get_engine_clock = &radeon_legacy_get_engine_clock,
319 .set_engine_clock = &radeon_legacy_set_engine_clock,
320 .get_memory_clock = &radeon_legacy_get_memory_clock,
321 .set_memory_clock = NULL,
322 .get_pcie_lanes = NULL,
323 .set_pcie_lanes = NULL,
324 .set_clock_gating = &radeon_legacy_set_clock_gating,
327 .pre_page_flip = &r100_pre_page_flip,
328 .page_flip = &r100_page_flip,
329 .post_page_flip = &r100_post_page_flip,
333 static struct radeon_asic r300_asic = {
336 .suspend = &r300_suspend,
337 .resume = &r300_resume,
338 .vga_set_state = &r100_vga_set_state,
339 .asic_reset = &r300_asic_reset,
340 .ioctl_wait_idle = NULL,
341 .gui_idle = &r100_gui_idle,
342 .mc_wait_for_idle = &r300_mc_wait_for_idle,
344 .tlb_flush = &r100_pci_gart_tlb_flush,
345 .set_page = &r100_pci_gart_set_page,
348 [RADEON_RING_TYPE_GFX_INDEX] = {
349 .ib_execute = &r100_ring_ib_execute,
350 .emit_fence = &r300_fence_ring_emit,
351 .emit_semaphore = &r100_semaphore_ring_emit,
352 .cs_parse = &r300_cs_parse,
353 .ring_start = &r300_ring_start,
354 .ring_test = &r100_ring_test,
355 .ib_test = &r100_ib_test,
356 .is_lockup = &r100_gpu_is_lockup,
357 .get_rptr = &radeon_ring_generic_get_rptr,
358 .get_wptr = &radeon_ring_generic_get_wptr,
359 .set_wptr = &radeon_ring_generic_set_wptr,
363 .set = &r100_irq_set,
364 .process = &r100_irq_process,
367 .bandwidth_update = &r100_bandwidth_update,
368 .get_vblank_counter = &r100_get_vblank_counter,
369 .wait_for_vblank = &r100_wait_for_vblank,
370 .set_backlight_level = &radeon_legacy_set_backlight_level,
371 .get_backlight_level = &radeon_legacy_get_backlight_level,
374 .blit = &r100_copy_blit,
375 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
376 .dma = &r200_copy_dma,
377 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
378 .copy = &r100_copy_blit,
379 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
382 .set_reg = r100_set_surface_reg,
383 .clear_reg = r100_clear_surface_reg,
386 .init = &r100_hpd_init,
387 .fini = &r100_hpd_fini,
388 .sense = &r100_hpd_sense,
389 .set_polarity = &r100_hpd_set_polarity,
392 .misc = &r100_pm_misc,
393 .prepare = &r100_pm_prepare,
394 .finish = &r100_pm_finish,
395 .init_profile = &r100_pm_init_profile,
396 .get_dynpm_state = &r100_pm_get_dynpm_state,
397 .get_engine_clock = &radeon_legacy_get_engine_clock,
398 .set_engine_clock = &radeon_legacy_set_engine_clock,
399 .get_memory_clock = &radeon_legacy_get_memory_clock,
400 .set_memory_clock = NULL,
401 .get_pcie_lanes = &rv370_get_pcie_lanes,
402 .set_pcie_lanes = &rv370_set_pcie_lanes,
403 .set_clock_gating = &radeon_legacy_set_clock_gating,
406 .pre_page_flip = &r100_pre_page_flip,
407 .page_flip = &r100_page_flip,
408 .post_page_flip = &r100_post_page_flip,
412 static struct radeon_asic r300_asic_pcie = {
415 .suspend = &r300_suspend,
416 .resume = &r300_resume,
417 .vga_set_state = &r100_vga_set_state,
418 .asic_reset = &r300_asic_reset,
419 .ioctl_wait_idle = NULL,
420 .gui_idle = &r100_gui_idle,
421 .mc_wait_for_idle = &r300_mc_wait_for_idle,
423 .tlb_flush = &rv370_pcie_gart_tlb_flush,
424 .set_page = &rv370_pcie_gart_set_page,
427 [RADEON_RING_TYPE_GFX_INDEX] = {
428 .ib_execute = &r100_ring_ib_execute,
429 .emit_fence = &r300_fence_ring_emit,
430 .emit_semaphore = &r100_semaphore_ring_emit,
431 .cs_parse = &r300_cs_parse,
432 .ring_start = &r300_ring_start,
433 .ring_test = &r100_ring_test,
434 .ib_test = &r100_ib_test,
435 .is_lockup = &r100_gpu_is_lockup,
436 .get_rptr = &radeon_ring_generic_get_rptr,
437 .get_wptr = &radeon_ring_generic_get_wptr,
438 .set_wptr = &radeon_ring_generic_set_wptr,
442 .set = &r100_irq_set,
443 .process = &r100_irq_process,
446 .bandwidth_update = &r100_bandwidth_update,
447 .get_vblank_counter = &r100_get_vblank_counter,
448 .wait_for_vblank = &r100_wait_for_vblank,
449 .set_backlight_level = &radeon_legacy_set_backlight_level,
450 .get_backlight_level = &radeon_legacy_get_backlight_level,
453 .blit = &r100_copy_blit,
454 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
455 .dma = &r200_copy_dma,
456 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
457 .copy = &r100_copy_blit,
458 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
461 .set_reg = r100_set_surface_reg,
462 .clear_reg = r100_clear_surface_reg,
465 .init = &r100_hpd_init,
466 .fini = &r100_hpd_fini,
467 .sense = &r100_hpd_sense,
468 .set_polarity = &r100_hpd_set_polarity,
471 .misc = &r100_pm_misc,
472 .prepare = &r100_pm_prepare,
473 .finish = &r100_pm_finish,
474 .init_profile = &r100_pm_init_profile,
475 .get_dynpm_state = &r100_pm_get_dynpm_state,
476 .get_engine_clock = &radeon_legacy_get_engine_clock,
477 .set_engine_clock = &radeon_legacy_set_engine_clock,
478 .get_memory_clock = &radeon_legacy_get_memory_clock,
479 .set_memory_clock = NULL,
480 .get_pcie_lanes = &rv370_get_pcie_lanes,
481 .set_pcie_lanes = &rv370_set_pcie_lanes,
482 .set_clock_gating = &radeon_legacy_set_clock_gating,
485 .pre_page_flip = &r100_pre_page_flip,
486 .page_flip = &r100_page_flip,
487 .post_page_flip = &r100_post_page_flip,
491 static struct radeon_asic r420_asic = {
494 .suspend = &r420_suspend,
495 .resume = &r420_resume,
496 .vga_set_state = &r100_vga_set_state,
497 .asic_reset = &r300_asic_reset,
498 .ioctl_wait_idle = NULL,
499 .gui_idle = &r100_gui_idle,
500 .mc_wait_for_idle = &r300_mc_wait_for_idle,
502 .tlb_flush = &rv370_pcie_gart_tlb_flush,
503 .set_page = &rv370_pcie_gart_set_page,
506 [RADEON_RING_TYPE_GFX_INDEX] = {
507 .ib_execute = &r100_ring_ib_execute,
508 .emit_fence = &r300_fence_ring_emit,
509 .emit_semaphore = &r100_semaphore_ring_emit,
510 .cs_parse = &r300_cs_parse,
511 .ring_start = &r300_ring_start,
512 .ring_test = &r100_ring_test,
513 .ib_test = &r100_ib_test,
514 .is_lockup = &r100_gpu_is_lockup,
515 .get_rptr = &radeon_ring_generic_get_rptr,
516 .get_wptr = &radeon_ring_generic_get_wptr,
517 .set_wptr = &radeon_ring_generic_set_wptr,
521 .set = &r100_irq_set,
522 .process = &r100_irq_process,
525 .bandwidth_update = &r100_bandwidth_update,
526 .get_vblank_counter = &r100_get_vblank_counter,
527 .wait_for_vblank = &r100_wait_for_vblank,
528 .set_backlight_level = &atombios_set_backlight_level,
529 .get_backlight_level = &atombios_get_backlight_level,
532 .blit = &r100_copy_blit,
533 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
534 .dma = &r200_copy_dma,
535 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
536 .copy = &r100_copy_blit,
537 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
540 .set_reg = r100_set_surface_reg,
541 .clear_reg = r100_clear_surface_reg,
544 .init = &r100_hpd_init,
545 .fini = &r100_hpd_fini,
546 .sense = &r100_hpd_sense,
547 .set_polarity = &r100_hpd_set_polarity,
550 .misc = &r100_pm_misc,
551 .prepare = &r100_pm_prepare,
552 .finish = &r100_pm_finish,
553 .init_profile = &r420_pm_init_profile,
554 .get_dynpm_state = &r100_pm_get_dynpm_state,
555 .get_engine_clock = &radeon_atom_get_engine_clock,
556 .set_engine_clock = &radeon_atom_set_engine_clock,
557 .get_memory_clock = &radeon_atom_get_memory_clock,
558 .set_memory_clock = &radeon_atom_set_memory_clock,
559 .get_pcie_lanes = &rv370_get_pcie_lanes,
560 .set_pcie_lanes = &rv370_set_pcie_lanes,
561 .set_clock_gating = &radeon_atom_set_clock_gating,
564 .pre_page_flip = &r100_pre_page_flip,
565 .page_flip = &r100_page_flip,
566 .post_page_flip = &r100_post_page_flip,
570 static struct radeon_asic rs400_asic = {
573 .suspend = &rs400_suspend,
574 .resume = &rs400_resume,
575 .vga_set_state = &r100_vga_set_state,
576 .asic_reset = &r300_asic_reset,
577 .ioctl_wait_idle = NULL,
578 .gui_idle = &r100_gui_idle,
579 .mc_wait_for_idle = &rs400_mc_wait_for_idle,
581 .tlb_flush = &rs400_gart_tlb_flush,
582 .set_page = &rs400_gart_set_page,
585 [RADEON_RING_TYPE_GFX_INDEX] = {
586 .ib_execute = &r100_ring_ib_execute,
587 .emit_fence = &r300_fence_ring_emit,
588 .emit_semaphore = &r100_semaphore_ring_emit,
589 .cs_parse = &r300_cs_parse,
590 .ring_start = &r300_ring_start,
591 .ring_test = &r100_ring_test,
592 .ib_test = &r100_ib_test,
593 .is_lockup = &r100_gpu_is_lockup,
594 .get_rptr = &radeon_ring_generic_get_rptr,
595 .get_wptr = &radeon_ring_generic_get_wptr,
596 .set_wptr = &radeon_ring_generic_set_wptr,
600 .set = &r100_irq_set,
601 .process = &r100_irq_process,
604 .bandwidth_update = &r100_bandwidth_update,
605 .get_vblank_counter = &r100_get_vblank_counter,
606 .wait_for_vblank = &r100_wait_for_vblank,
607 .set_backlight_level = &radeon_legacy_set_backlight_level,
608 .get_backlight_level = &radeon_legacy_get_backlight_level,
611 .blit = &r100_copy_blit,
612 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
613 .dma = &r200_copy_dma,
614 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
615 .copy = &r100_copy_blit,
616 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
619 .set_reg = r100_set_surface_reg,
620 .clear_reg = r100_clear_surface_reg,
623 .init = &r100_hpd_init,
624 .fini = &r100_hpd_fini,
625 .sense = &r100_hpd_sense,
626 .set_polarity = &r100_hpd_set_polarity,
629 .misc = &r100_pm_misc,
630 .prepare = &r100_pm_prepare,
631 .finish = &r100_pm_finish,
632 .init_profile = &r100_pm_init_profile,
633 .get_dynpm_state = &r100_pm_get_dynpm_state,
634 .get_engine_clock = &radeon_legacy_get_engine_clock,
635 .set_engine_clock = &radeon_legacy_set_engine_clock,
636 .get_memory_clock = &radeon_legacy_get_memory_clock,
637 .set_memory_clock = NULL,
638 .get_pcie_lanes = NULL,
639 .set_pcie_lanes = NULL,
640 .set_clock_gating = &radeon_legacy_set_clock_gating,
643 .pre_page_flip = &r100_pre_page_flip,
644 .page_flip = &r100_page_flip,
645 .post_page_flip = &r100_post_page_flip,
649 static struct radeon_asic rs600_asic = {
652 .suspend = &rs600_suspend,
653 .resume = &rs600_resume,
654 .vga_set_state = &r100_vga_set_state,
655 .asic_reset = &rs600_asic_reset,
656 .ioctl_wait_idle = NULL,
657 .gui_idle = &r100_gui_idle,
658 .mc_wait_for_idle = &rs600_mc_wait_for_idle,
660 .tlb_flush = &rs600_gart_tlb_flush,
661 .set_page = &rs600_gart_set_page,
664 [RADEON_RING_TYPE_GFX_INDEX] = {
665 .ib_execute = &r100_ring_ib_execute,
666 .emit_fence = &r300_fence_ring_emit,
667 .emit_semaphore = &r100_semaphore_ring_emit,
668 .cs_parse = &r300_cs_parse,
669 .ring_start = &r300_ring_start,
670 .ring_test = &r100_ring_test,
671 .ib_test = &r100_ib_test,
672 .is_lockup = &r100_gpu_is_lockup,
673 .get_rptr = &radeon_ring_generic_get_rptr,
674 .get_wptr = &radeon_ring_generic_get_wptr,
675 .set_wptr = &radeon_ring_generic_set_wptr,
679 .set = &rs600_irq_set,
680 .process = &rs600_irq_process,
683 .bandwidth_update = &rs600_bandwidth_update,
684 .get_vblank_counter = &rs600_get_vblank_counter,
685 .wait_for_vblank = &avivo_wait_for_vblank,
686 .set_backlight_level = &atombios_set_backlight_level,
687 .get_backlight_level = &atombios_get_backlight_level,
688 .hdmi_enable = &r600_hdmi_enable,
689 .hdmi_setmode = &r600_hdmi_setmode,
692 .blit = &r100_copy_blit,
693 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
694 .dma = &r200_copy_dma,
695 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
696 .copy = &r100_copy_blit,
697 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
700 .set_reg = r100_set_surface_reg,
701 .clear_reg = r100_clear_surface_reg,
704 .init = &rs600_hpd_init,
705 .fini = &rs600_hpd_fini,
706 .sense = &rs600_hpd_sense,
707 .set_polarity = &rs600_hpd_set_polarity,
710 .misc = &rs600_pm_misc,
711 .prepare = &rs600_pm_prepare,
712 .finish = &rs600_pm_finish,
713 .init_profile = &r420_pm_init_profile,
714 .get_dynpm_state = &r100_pm_get_dynpm_state,
715 .get_engine_clock = &radeon_atom_get_engine_clock,
716 .set_engine_clock = &radeon_atom_set_engine_clock,
717 .get_memory_clock = &radeon_atom_get_memory_clock,
718 .set_memory_clock = &radeon_atom_set_memory_clock,
719 .get_pcie_lanes = NULL,
720 .set_pcie_lanes = NULL,
721 .set_clock_gating = &radeon_atom_set_clock_gating,
724 .pre_page_flip = &rs600_pre_page_flip,
725 .page_flip = &rs600_page_flip,
726 .post_page_flip = &rs600_post_page_flip,
730 static struct radeon_asic rs690_asic = {
733 .suspend = &rs690_suspend,
734 .resume = &rs690_resume,
735 .vga_set_state = &r100_vga_set_state,
736 .asic_reset = &rs600_asic_reset,
737 .ioctl_wait_idle = NULL,
738 .gui_idle = &r100_gui_idle,
739 .mc_wait_for_idle = &rs690_mc_wait_for_idle,
741 .tlb_flush = &rs400_gart_tlb_flush,
742 .set_page = &rs400_gart_set_page,
745 [RADEON_RING_TYPE_GFX_INDEX] = {
746 .ib_execute = &r100_ring_ib_execute,
747 .emit_fence = &r300_fence_ring_emit,
748 .emit_semaphore = &r100_semaphore_ring_emit,
749 .cs_parse = &r300_cs_parse,
750 .ring_start = &r300_ring_start,
751 .ring_test = &r100_ring_test,
752 .ib_test = &r100_ib_test,
753 .is_lockup = &r100_gpu_is_lockup,
754 .get_rptr = &radeon_ring_generic_get_rptr,
755 .get_wptr = &radeon_ring_generic_get_wptr,
756 .set_wptr = &radeon_ring_generic_set_wptr,
760 .set = &rs600_irq_set,
761 .process = &rs600_irq_process,
764 .get_vblank_counter = &rs600_get_vblank_counter,
765 .bandwidth_update = &rs690_bandwidth_update,
766 .wait_for_vblank = &avivo_wait_for_vblank,
767 .set_backlight_level = &atombios_set_backlight_level,
768 .get_backlight_level = &atombios_get_backlight_level,
769 .hdmi_enable = &r600_hdmi_enable,
770 .hdmi_setmode = &r600_hdmi_setmode,
773 .blit = &r100_copy_blit,
774 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
775 .dma = &r200_copy_dma,
776 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
777 .copy = &r200_copy_dma,
778 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
781 .set_reg = r100_set_surface_reg,
782 .clear_reg = r100_clear_surface_reg,
785 .init = &rs600_hpd_init,
786 .fini = &rs600_hpd_fini,
787 .sense = &rs600_hpd_sense,
788 .set_polarity = &rs600_hpd_set_polarity,
791 .misc = &rs600_pm_misc,
792 .prepare = &rs600_pm_prepare,
793 .finish = &rs600_pm_finish,
794 .init_profile = &r420_pm_init_profile,
795 .get_dynpm_state = &r100_pm_get_dynpm_state,
796 .get_engine_clock = &radeon_atom_get_engine_clock,
797 .set_engine_clock = &radeon_atom_set_engine_clock,
798 .get_memory_clock = &radeon_atom_get_memory_clock,
799 .set_memory_clock = &radeon_atom_set_memory_clock,
800 .get_pcie_lanes = NULL,
801 .set_pcie_lanes = NULL,
802 .set_clock_gating = &radeon_atom_set_clock_gating,
805 .pre_page_flip = &rs600_pre_page_flip,
806 .page_flip = &rs600_page_flip,
807 .post_page_flip = &rs600_post_page_flip,
811 static struct radeon_asic rv515_asic = {
814 .suspend = &rv515_suspend,
815 .resume = &rv515_resume,
816 .vga_set_state = &r100_vga_set_state,
817 .asic_reset = &rs600_asic_reset,
818 .ioctl_wait_idle = NULL,
819 .gui_idle = &r100_gui_idle,
820 .mc_wait_for_idle = &rv515_mc_wait_for_idle,
822 .tlb_flush = &rv370_pcie_gart_tlb_flush,
823 .set_page = &rv370_pcie_gart_set_page,
826 [RADEON_RING_TYPE_GFX_INDEX] = {
827 .ib_execute = &r100_ring_ib_execute,
828 .emit_fence = &r300_fence_ring_emit,
829 .emit_semaphore = &r100_semaphore_ring_emit,
830 .cs_parse = &r300_cs_parse,
831 .ring_start = &rv515_ring_start,
832 .ring_test = &r100_ring_test,
833 .ib_test = &r100_ib_test,
834 .is_lockup = &r100_gpu_is_lockup,
835 .get_rptr = &radeon_ring_generic_get_rptr,
836 .get_wptr = &radeon_ring_generic_get_wptr,
837 .set_wptr = &radeon_ring_generic_set_wptr,
841 .set = &rs600_irq_set,
842 .process = &rs600_irq_process,
845 .get_vblank_counter = &rs600_get_vblank_counter,
846 .bandwidth_update = &rv515_bandwidth_update,
847 .wait_for_vblank = &avivo_wait_for_vblank,
848 .set_backlight_level = &atombios_set_backlight_level,
849 .get_backlight_level = &atombios_get_backlight_level,
852 .blit = &r100_copy_blit,
853 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
854 .dma = &r200_copy_dma,
855 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
856 .copy = &r100_copy_blit,
857 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
860 .set_reg = r100_set_surface_reg,
861 .clear_reg = r100_clear_surface_reg,
864 .init = &rs600_hpd_init,
865 .fini = &rs600_hpd_fini,
866 .sense = &rs600_hpd_sense,
867 .set_polarity = &rs600_hpd_set_polarity,
870 .misc = &rs600_pm_misc,
871 .prepare = &rs600_pm_prepare,
872 .finish = &rs600_pm_finish,
873 .init_profile = &r420_pm_init_profile,
874 .get_dynpm_state = &r100_pm_get_dynpm_state,
875 .get_engine_clock = &radeon_atom_get_engine_clock,
876 .set_engine_clock = &radeon_atom_set_engine_clock,
877 .get_memory_clock = &radeon_atom_get_memory_clock,
878 .set_memory_clock = &radeon_atom_set_memory_clock,
879 .get_pcie_lanes = &rv370_get_pcie_lanes,
880 .set_pcie_lanes = &rv370_set_pcie_lanes,
881 .set_clock_gating = &radeon_atom_set_clock_gating,
884 .pre_page_flip = &rs600_pre_page_flip,
885 .page_flip = &rs600_page_flip,
886 .post_page_flip = &rs600_post_page_flip,
890 static struct radeon_asic r520_asic = {
893 .suspend = &rv515_suspend,
894 .resume = &r520_resume,
895 .vga_set_state = &r100_vga_set_state,
896 .asic_reset = &rs600_asic_reset,
897 .ioctl_wait_idle = NULL,
898 .gui_idle = &r100_gui_idle,
899 .mc_wait_for_idle = &r520_mc_wait_for_idle,
901 .tlb_flush = &rv370_pcie_gart_tlb_flush,
902 .set_page = &rv370_pcie_gart_set_page,
905 [RADEON_RING_TYPE_GFX_INDEX] = {
906 .ib_execute = &r100_ring_ib_execute,
907 .emit_fence = &r300_fence_ring_emit,
908 .emit_semaphore = &r100_semaphore_ring_emit,
909 .cs_parse = &r300_cs_parse,
910 .ring_start = &rv515_ring_start,
911 .ring_test = &r100_ring_test,
912 .ib_test = &r100_ib_test,
913 .is_lockup = &r100_gpu_is_lockup,
914 .get_rptr = &radeon_ring_generic_get_rptr,
915 .get_wptr = &radeon_ring_generic_get_wptr,
916 .set_wptr = &radeon_ring_generic_set_wptr,
920 .set = &rs600_irq_set,
921 .process = &rs600_irq_process,
924 .bandwidth_update = &rv515_bandwidth_update,
925 .get_vblank_counter = &rs600_get_vblank_counter,
926 .wait_for_vblank = &avivo_wait_for_vblank,
927 .set_backlight_level = &atombios_set_backlight_level,
928 .get_backlight_level = &atombios_get_backlight_level,
931 .blit = &r100_copy_blit,
932 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
933 .dma = &r200_copy_dma,
934 .dma_ring_index = RADEON_RING_TYPE_GFX_INDEX,
935 .copy = &r100_copy_blit,
936 .copy_ring_index = RADEON_RING_TYPE_GFX_INDEX,
939 .set_reg = r100_set_surface_reg,
940 .clear_reg = r100_clear_surface_reg,
943 .init = &rs600_hpd_init,
944 .fini = &rs600_hpd_fini,
945 .sense = &rs600_hpd_sense,
946 .set_polarity = &rs600_hpd_set_polarity,
949 .misc = &rs600_pm_misc,
950 .prepare = &rs600_pm_prepare,
951 .finish = &rs600_pm_finish,
952 .init_profile = &r420_pm_init_profile,
953 .get_dynpm_state = &r100_pm_get_dynpm_state,
954 .get_engine_clock = &radeon_atom_get_engine_clock,
955 .set_engine_clock = &radeon_atom_set_engine_clock,
956 .get_memory_clock = &radeon_atom_get_memory_clock,
957 .set_memory_clock = &radeon_atom_set_memory_clock,
958 .get_pcie_lanes = &rv370_get_pcie_lanes,
959 .set_pcie_lanes = &rv370_set_pcie_lanes,
960 .set_clock_gating = &radeon_atom_set_clock_gating,
963 .pre_page_flip = &rs600_pre_page_flip,
964 .page_flip = &rs600_page_flip,
965 .post_page_flip = &rs600_post_page_flip,
969 static struct radeon_asic r600_asic = {
972 .suspend = &r600_suspend,
973 .resume = &r600_resume,
974 .vga_set_state = &r600_vga_set_state,
975 .asic_reset = &r600_asic_reset,
976 .ioctl_wait_idle = r600_ioctl_wait_idle,
977 .gui_idle = &r600_gui_idle,
978 .mc_wait_for_idle = &r600_mc_wait_for_idle,
979 .get_xclk = &r600_get_xclk,
980 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
982 .tlb_flush = &r600_pcie_gart_tlb_flush,
983 .set_page = &rs600_gart_set_page,
986 [RADEON_RING_TYPE_GFX_INDEX] = {
987 .ib_execute = &r600_ring_ib_execute,
988 .emit_fence = &r600_fence_ring_emit,
989 .emit_semaphore = &r600_semaphore_ring_emit,
990 .cs_parse = &r600_cs_parse,
991 .ring_test = &r600_ring_test,
992 .ib_test = &r600_ib_test,
993 .is_lockup = &r600_gfx_is_lockup,
994 .get_rptr = &radeon_ring_generic_get_rptr,
995 .get_wptr = &radeon_ring_generic_get_wptr,
996 .set_wptr = &radeon_ring_generic_set_wptr,
998 [R600_RING_TYPE_DMA_INDEX] = {
999 .ib_execute = &r600_dma_ring_ib_execute,
1000 .emit_fence = &r600_dma_fence_ring_emit,
1001 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1002 .cs_parse = &r600_dma_cs_parse,
1003 .ring_test = &r600_dma_ring_test,
1004 .ib_test = &r600_dma_ib_test,
1005 .is_lockup = &r600_dma_is_lockup,
1006 .get_rptr = &radeon_ring_generic_get_rptr,
1007 .get_wptr = &radeon_ring_generic_get_wptr,
1008 .set_wptr = &radeon_ring_generic_set_wptr,
1012 .set = &r600_irq_set,
1013 .process = &r600_irq_process,
1016 .bandwidth_update = &rv515_bandwidth_update,
1017 .get_vblank_counter = &rs600_get_vblank_counter,
1018 .wait_for_vblank = &avivo_wait_for_vblank,
1019 .set_backlight_level = &atombios_set_backlight_level,
1020 .get_backlight_level = &atombios_get_backlight_level,
1021 .hdmi_enable = &r600_hdmi_enable,
1022 .hdmi_setmode = &r600_hdmi_setmode,
1025 .blit = &r600_copy_blit,
1026 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1027 .dma = &r600_copy_dma,
1028 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1029 .copy = &r600_copy_dma,
1030 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1033 .set_reg = r600_set_surface_reg,
1034 .clear_reg = r600_clear_surface_reg,
1037 .init = &r600_hpd_init,
1038 .fini = &r600_hpd_fini,
1039 .sense = &r600_hpd_sense,
1040 .set_polarity = &r600_hpd_set_polarity,
1043 .misc = &r600_pm_misc,
1044 .prepare = &rs600_pm_prepare,
1045 .finish = &rs600_pm_finish,
1046 .init_profile = &r600_pm_init_profile,
1047 .get_dynpm_state = &r600_pm_get_dynpm_state,
1048 .get_engine_clock = &radeon_atom_get_engine_clock,
1049 .set_engine_clock = &radeon_atom_set_engine_clock,
1050 .get_memory_clock = &radeon_atom_get_memory_clock,
1051 .set_memory_clock = &radeon_atom_set_memory_clock,
1052 .get_pcie_lanes = &r600_get_pcie_lanes,
1053 .set_pcie_lanes = &r600_set_pcie_lanes,
1054 .set_clock_gating = NULL,
1055 .get_temperature = &rv6xx_get_temp,
1058 .pre_page_flip = &rs600_pre_page_flip,
1059 .page_flip = &rs600_page_flip,
1060 .post_page_flip = &rs600_post_page_flip,
1064 static struct radeon_asic rv6xx_asic = {
1067 .suspend = &r600_suspend,
1068 .resume = &r600_resume,
1069 .vga_set_state = &r600_vga_set_state,
1070 .asic_reset = &r600_asic_reset,
1071 .ioctl_wait_idle = r600_ioctl_wait_idle,
1072 .gui_idle = &r600_gui_idle,
1073 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1074 .get_xclk = &r600_get_xclk,
1075 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1077 .tlb_flush = &r600_pcie_gart_tlb_flush,
1078 .set_page = &rs600_gart_set_page,
1081 [RADEON_RING_TYPE_GFX_INDEX] = {
1082 .ib_execute = &r600_ring_ib_execute,
1083 .emit_fence = &r600_fence_ring_emit,
1084 .emit_semaphore = &r600_semaphore_ring_emit,
1085 .cs_parse = &r600_cs_parse,
1086 .ring_test = &r600_ring_test,
1087 .ib_test = &r600_ib_test,
1088 .is_lockup = &r600_gfx_is_lockup,
1089 .get_rptr = &radeon_ring_generic_get_rptr,
1090 .get_wptr = &radeon_ring_generic_get_wptr,
1091 .set_wptr = &radeon_ring_generic_set_wptr,
1093 [R600_RING_TYPE_DMA_INDEX] = {
1094 .ib_execute = &r600_dma_ring_ib_execute,
1095 .emit_fence = &r600_dma_fence_ring_emit,
1096 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1097 .cs_parse = &r600_dma_cs_parse,
1098 .ring_test = &r600_dma_ring_test,
1099 .ib_test = &r600_dma_ib_test,
1100 .is_lockup = &r600_dma_is_lockup,
1101 .get_rptr = &radeon_ring_generic_get_rptr,
1102 .get_wptr = &radeon_ring_generic_get_wptr,
1103 .set_wptr = &radeon_ring_generic_set_wptr,
1107 .set = &r600_irq_set,
1108 .process = &r600_irq_process,
1111 .bandwidth_update = &rv515_bandwidth_update,
1112 .get_vblank_counter = &rs600_get_vblank_counter,
1113 .wait_for_vblank = &avivo_wait_for_vblank,
1114 .set_backlight_level = &atombios_set_backlight_level,
1115 .get_backlight_level = &atombios_get_backlight_level,
1118 .blit = &r600_copy_blit,
1119 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1120 .dma = &r600_copy_dma,
1121 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1122 .copy = &r600_copy_dma,
1123 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1126 .set_reg = r600_set_surface_reg,
1127 .clear_reg = r600_clear_surface_reg,
1130 .init = &r600_hpd_init,
1131 .fini = &r600_hpd_fini,
1132 .sense = &r600_hpd_sense,
1133 .set_polarity = &r600_hpd_set_polarity,
1136 .misc = &r600_pm_misc,
1137 .prepare = &rs600_pm_prepare,
1138 .finish = &rs600_pm_finish,
1139 .init_profile = &r600_pm_init_profile,
1140 .get_dynpm_state = &r600_pm_get_dynpm_state,
1141 .get_engine_clock = &radeon_atom_get_engine_clock,
1142 .set_engine_clock = &radeon_atom_set_engine_clock,
1143 .get_memory_clock = &radeon_atom_get_memory_clock,
1144 .set_memory_clock = &radeon_atom_set_memory_clock,
1145 .get_pcie_lanes = &r600_get_pcie_lanes,
1146 .set_pcie_lanes = &r600_set_pcie_lanes,
1147 .set_clock_gating = NULL,
1148 .get_temperature = &rv6xx_get_temp,
1151 .init = &rv6xx_dpm_init,
1152 .setup_asic = &rv6xx_setup_asic,
1153 .enable = &rv6xx_dpm_enable,
1154 .disable = &rv6xx_dpm_disable,
1155 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1156 .set_power_state = &rv6xx_dpm_set_power_state,
1157 .post_set_power_state = &r600_dpm_post_set_power_state,
1158 .display_configuration_changed = &rv6xx_dpm_display_configuration_changed,
1159 .fini = &rv6xx_dpm_fini,
1160 .get_sclk = &rv6xx_dpm_get_sclk,
1161 .get_mclk = &rv6xx_dpm_get_mclk,
1162 .print_power_state = &rv6xx_dpm_print_power_state,
1163 .debugfs_print_current_performance_level = &rv6xx_dpm_debugfs_print_current_performance_level,
1166 .pre_page_flip = &rs600_pre_page_flip,
1167 .page_flip = &rs600_page_flip,
1168 .post_page_flip = &rs600_post_page_flip,
1172 static struct radeon_asic rs780_asic = {
1175 .suspend = &r600_suspend,
1176 .resume = &r600_resume,
1177 .vga_set_state = &r600_vga_set_state,
1178 .asic_reset = &r600_asic_reset,
1179 .ioctl_wait_idle = r600_ioctl_wait_idle,
1180 .gui_idle = &r600_gui_idle,
1181 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1182 .get_xclk = &r600_get_xclk,
1183 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1185 .tlb_flush = &r600_pcie_gart_tlb_flush,
1186 .set_page = &rs600_gart_set_page,
1189 [RADEON_RING_TYPE_GFX_INDEX] = {
1190 .ib_execute = &r600_ring_ib_execute,
1191 .emit_fence = &r600_fence_ring_emit,
1192 .emit_semaphore = &r600_semaphore_ring_emit,
1193 .cs_parse = &r600_cs_parse,
1194 .ring_test = &r600_ring_test,
1195 .ib_test = &r600_ib_test,
1196 .is_lockup = &r600_gfx_is_lockup,
1197 .get_rptr = &radeon_ring_generic_get_rptr,
1198 .get_wptr = &radeon_ring_generic_get_wptr,
1199 .set_wptr = &radeon_ring_generic_set_wptr,
1201 [R600_RING_TYPE_DMA_INDEX] = {
1202 .ib_execute = &r600_dma_ring_ib_execute,
1203 .emit_fence = &r600_dma_fence_ring_emit,
1204 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1205 .cs_parse = &r600_dma_cs_parse,
1206 .ring_test = &r600_dma_ring_test,
1207 .ib_test = &r600_dma_ib_test,
1208 .is_lockup = &r600_dma_is_lockup,
1209 .get_rptr = &radeon_ring_generic_get_rptr,
1210 .get_wptr = &radeon_ring_generic_get_wptr,
1211 .set_wptr = &radeon_ring_generic_set_wptr,
1215 .set = &r600_irq_set,
1216 .process = &r600_irq_process,
1219 .bandwidth_update = &rs690_bandwidth_update,
1220 .get_vblank_counter = &rs600_get_vblank_counter,
1221 .wait_for_vblank = &avivo_wait_for_vblank,
1222 .set_backlight_level = &atombios_set_backlight_level,
1223 .get_backlight_level = &atombios_get_backlight_level,
1224 .hdmi_enable = &r600_hdmi_enable,
1225 .hdmi_setmode = &r600_hdmi_setmode,
1228 .blit = &r600_copy_blit,
1229 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1230 .dma = &r600_copy_dma,
1231 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1232 .copy = &r600_copy_dma,
1233 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1236 .set_reg = r600_set_surface_reg,
1237 .clear_reg = r600_clear_surface_reg,
1240 .init = &r600_hpd_init,
1241 .fini = &r600_hpd_fini,
1242 .sense = &r600_hpd_sense,
1243 .set_polarity = &r600_hpd_set_polarity,
1246 .misc = &r600_pm_misc,
1247 .prepare = &rs600_pm_prepare,
1248 .finish = &rs600_pm_finish,
1249 .init_profile = &rs780_pm_init_profile,
1250 .get_dynpm_state = &r600_pm_get_dynpm_state,
1251 .get_engine_clock = &radeon_atom_get_engine_clock,
1252 .set_engine_clock = &radeon_atom_set_engine_clock,
1253 .get_memory_clock = NULL,
1254 .set_memory_clock = NULL,
1255 .get_pcie_lanes = NULL,
1256 .set_pcie_lanes = NULL,
1257 .set_clock_gating = NULL,
1258 .get_temperature = &rv6xx_get_temp,
1261 .init = &rs780_dpm_init,
1262 .setup_asic = &rs780_dpm_setup_asic,
1263 .enable = &rs780_dpm_enable,
1264 .disable = &rs780_dpm_disable,
1265 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1266 .set_power_state = &rs780_dpm_set_power_state,
1267 .post_set_power_state = &r600_dpm_post_set_power_state,
1268 .display_configuration_changed = &rs780_dpm_display_configuration_changed,
1269 .fini = &rs780_dpm_fini,
1270 .get_sclk = &rs780_dpm_get_sclk,
1271 .get_mclk = &rs780_dpm_get_mclk,
1272 .print_power_state = &rs780_dpm_print_power_state,
1275 .pre_page_flip = &rs600_pre_page_flip,
1276 .page_flip = &rs600_page_flip,
1277 .post_page_flip = &rs600_post_page_flip,
1281 static struct radeon_asic rv770_asic = {
1282 .init = &rv770_init,
1283 .fini = &rv770_fini,
1284 .suspend = &rv770_suspend,
1285 .resume = &rv770_resume,
1286 .asic_reset = &r600_asic_reset,
1287 .vga_set_state = &r600_vga_set_state,
1288 .ioctl_wait_idle = r600_ioctl_wait_idle,
1289 .gui_idle = &r600_gui_idle,
1290 .mc_wait_for_idle = &r600_mc_wait_for_idle,
1291 .get_xclk = &rv770_get_xclk,
1292 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1294 .tlb_flush = &r600_pcie_gart_tlb_flush,
1295 .set_page = &rs600_gart_set_page,
1298 [RADEON_RING_TYPE_GFX_INDEX] = {
1299 .ib_execute = &r600_ring_ib_execute,
1300 .emit_fence = &r600_fence_ring_emit,
1301 .emit_semaphore = &r600_semaphore_ring_emit,
1302 .cs_parse = &r600_cs_parse,
1303 .ring_test = &r600_ring_test,
1304 .ib_test = &r600_ib_test,
1305 .is_lockup = &r600_gfx_is_lockup,
1306 .get_rptr = &radeon_ring_generic_get_rptr,
1307 .get_wptr = &radeon_ring_generic_get_wptr,
1308 .set_wptr = &radeon_ring_generic_set_wptr,
1310 [R600_RING_TYPE_DMA_INDEX] = {
1311 .ib_execute = &r600_dma_ring_ib_execute,
1312 .emit_fence = &r600_dma_fence_ring_emit,
1313 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1314 .cs_parse = &r600_dma_cs_parse,
1315 .ring_test = &r600_dma_ring_test,
1316 .ib_test = &r600_dma_ib_test,
1317 .is_lockup = &r600_dma_is_lockup,
1318 .get_rptr = &radeon_ring_generic_get_rptr,
1319 .get_wptr = &radeon_ring_generic_get_wptr,
1320 .set_wptr = &radeon_ring_generic_set_wptr,
1322 [R600_RING_TYPE_UVD_INDEX] = {
1323 .ib_execute = &r600_uvd_ib_execute,
1324 .emit_fence = &r600_uvd_fence_emit,
1325 .emit_semaphore = &r600_uvd_semaphore_emit,
1326 .cs_parse = &radeon_uvd_cs_parse,
1327 .ring_test = &r600_uvd_ring_test,
1328 .ib_test = &r600_uvd_ib_test,
1329 .is_lockup = &radeon_ring_test_lockup,
1330 .get_rptr = &radeon_ring_generic_get_rptr,
1331 .get_wptr = &radeon_ring_generic_get_wptr,
1332 .set_wptr = &radeon_ring_generic_set_wptr,
1336 .set = &r600_irq_set,
1337 .process = &r600_irq_process,
1340 .bandwidth_update = &rv515_bandwidth_update,
1341 .get_vblank_counter = &rs600_get_vblank_counter,
1342 .wait_for_vblank = &avivo_wait_for_vblank,
1343 .set_backlight_level = &atombios_set_backlight_level,
1344 .get_backlight_level = &atombios_get_backlight_level,
1345 .hdmi_enable = &r600_hdmi_enable,
1346 .hdmi_setmode = &r600_hdmi_setmode,
1349 .blit = &r600_copy_blit,
1350 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1351 .dma = &rv770_copy_dma,
1352 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1353 .copy = &rv770_copy_dma,
1354 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1357 .set_reg = r600_set_surface_reg,
1358 .clear_reg = r600_clear_surface_reg,
1361 .init = &r600_hpd_init,
1362 .fini = &r600_hpd_fini,
1363 .sense = &r600_hpd_sense,
1364 .set_polarity = &r600_hpd_set_polarity,
1367 .misc = &rv770_pm_misc,
1368 .prepare = &rs600_pm_prepare,
1369 .finish = &rs600_pm_finish,
1370 .init_profile = &r600_pm_init_profile,
1371 .get_dynpm_state = &r600_pm_get_dynpm_state,
1372 .get_engine_clock = &radeon_atom_get_engine_clock,
1373 .set_engine_clock = &radeon_atom_set_engine_clock,
1374 .get_memory_clock = &radeon_atom_get_memory_clock,
1375 .set_memory_clock = &radeon_atom_set_memory_clock,
1376 .get_pcie_lanes = &r600_get_pcie_lanes,
1377 .set_pcie_lanes = &r600_set_pcie_lanes,
1378 .set_clock_gating = &radeon_atom_set_clock_gating,
1379 .set_uvd_clocks = &rv770_set_uvd_clocks,
1380 .get_temperature = &rv770_get_temp,
1383 .init = &rv770_dpm_init,
1384 .setup_asic = &rv770_dpm_setup_asic,
1385 .enable = &rv770_dpm_enable,
1386 .disable = &rv770_dpm_disable,
1387 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1388 .set_power_state = &rv770_dpm_set_power_state,
1389 .post_set_power_state = &r600_dpm_post_set_power_state,
1390 .display_configuration_changed = &rv770_dpm_display_configuration_changed,
1391 .fini = &rv770_dpm_fini,
1392 .get_sclk = &rv770_dpm_get_sclk,
1393 .get_mclk = &rv770_dpm_get_mclk,
1394 .print_power_state = &rv770_dpm_print_power_state,
1397 .pre_page_flip = &rs600_pre_page_flip,
1398 .page_flip = &rv770_page_flip,
1399 .post_page_flip = &rs600_post_page_flip,
1403 static struct radeon_asic evergreen_asic = {
1404 .init = &evergreen_init,
1405 .fini = &evergreen_fini,
1406 .suspend = &evergreen_suspend,
1407 .resume = &evergreen_resume,
1408 .asic_reset = &evergreen_asic_reset,
1409 .vga_set_state = &r600_vga_set_state,
1410 .ioctl_wait_idle = r600_ioctl_wait_idle,
1411 .gui_idle = &r600_gui_idle,
1412 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1413 .get_xclk = &rv770_get_xclk,
1414 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1416 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1417 .set_page = &rs600_gart_set_page,
1420 [RADEON_RING_TYPE_GFX_INDEX] = {
1421 .ib_execute = &evergreen_ring_ib_execute,
1422 .emit_fence = &r600_fence_ring_emit,
1423 .emit_semaphore = &r600_semaphore_ring_emit,
1424 .cs_parse = &evergreen_cs_parse,
1425 .ring_test = &r600_ring_test,
1426 .ib_test = &r600_ib_test,
1427 .is_lockup = &evergreen_gfx_is_lockup,
1428 .get_rptr = &radeon_ring_generic_get_rptr,
1429 .get_wptr = &radeon_ring_generic_get_wptr,
1430 .set_wptr = &radeon_ring_generic_set_wptr,
1432 [R600_RING_TYPE_DMA_INDEX] = {
1433 .ib_execute = &evergreen_dma_ring_ib_execute,
1434 .emit_fence = &evergreen_dma_fence_ring_emit,
1435 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1436 .cs_parse = &evergreen_dma_cs_parse,
1437 .ring_test = &r600_dma_ring_test,
1438 .ib_test = &r600_dma_ib_test,
1439 .is_lockup = &evergreen_dma_is_lockup,
1440 .get_rptr = &radeon_ring_generic_get_rptr,
1441 .get_wptr = &radeon_ring_generic_get_wptr,
1442 .set_wptr = &radeon_ring_generic_set_wptr,
1444 [R600_RING_TYPE_UVD_INDEX] = {
1445 .ib_execute = &r600_uvd_ib_execute,
1446 .emit_fence = &r600_uvd_fence_emit,
1447 .emit_semaphore = &r600_uvd_semaphore_emit,
1448 .cs_parse = &radeon_uvd_cs_parse,
1449 .ring_test = &r600_uvd_ring_test,
1450 .ib_test = &r600_uvd_ib_test,
1451 .is_lockup = &radeon_ring_test_lockup,
1452 .get_rptr = &radeon_ring_generic_get_rptr,
1453 .get_wptr = &radeon_ring_generic_get_wptr,
1454 .set_wptr = &radeon_ring_generic_set_wptr,
1458 .set = &evergreen_irq_set,
1459 .process = &evergreen_irq_process,
1462 .bandwidth_update = &evergreen_bandwidth_update,
1463 .get_vblank_counter = &evergreen_get_vblank_counter,
1464 .wait_for_vblank = &dce4_wait_for_vblank,
1465 .set_backlight_level = &atombios_set_backlight_level,
1466 .get_backlight_level = &atombios_get_backlight_level,
1467 .hdmi_enable = &evergreen_hdmi_enable,
1468 .hdmi_setmode = &evergreen_hdmi_setmode,
1471 .blit = &r600_copy_blit,
1472 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1473 .dma = &evergreen_copy_dma,
1474 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1475 .copy = &evergreen_copy_dma,
1476 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1479 .set_reg = r600_set_surface_reg,
1480 .clear_reg = r600_clear_surface_reg,
1483 .init = &evergreen_hpd_init,
1484 .fini = &evergreen_hpd_fini,
1485 .sense = &evergreen_hpd_sense,
1486 .set_polarity = &evergreen_hpd_set_polarity,
1489 .misc = &evergreen_pm_misc,
1490 .prepare = &evergreen_pm_prepare,
1491 .finish = &evergreen_pm_finish,
1492 .init_profile = &r600_pm_init_profile,
1493 .get_dynpm_state = &r600_pm_get_dynpm_state,
1494 .get_engine_clock = &radeon_atom_get_engine_clock,
1495 .set_engine_clock = &radeon_atom_set_engine_clock,
1496 .get_memory_clock = &radeon_atom_get_memory_clock,
1497 .set_memory_clock = &radeon_atom_set_memory_clock,
1498 .get_pcie_lanes = &r600_get_pcie_lanes,
1499 .set_pcie_lanes = &r600_set_pcie_lanes,
1500 .set_clock_gating = NULL,
1501 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1502 .get_temperature = &evergreen_get_temp,
1505 .init = &cypress_dpm_init,
1506 .setup_asic = &cypress_dpm_setup_asic,
1507 .enable = &cypress_dpm_enable,
1508 .disable = &cypress_dpm_disable,
1509 .pre_set_power_state = &r600_dpm_pre_set_power_state,
1510 .set_power_state = &cypress_dpm_set_power_state,
1511 .post_set_power_state = &r600_dpm_post_set_power_state,
1512 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1513 .fini = &cypress_dpm_fini,
1514 .get_sclk = &rv770_dpm_get_sclk,
1515 .get_mclk = &rv770_dpm_get_mclk,
1516 .print_power_state = &rv770_dpm_print_power_state,
1519 .pre_page_flip = &evergreen_pre_page_flip,
1520 .page_flip = &evergreen_page_flip,
1521 .post_page_flip = &evergreen_post_page_flip,
1525 static struct radeon_asic sumo_asic = {
1526 .init = &evergreen_init,
1527 .fini = &evergreen_fini,
1528 .suspend = &evergreen_suspend,
1529 .resume = &evergreen_resume,
1530 .asic_reset = &evergreen_asic_reset,
1531 .vga_set_state = &r600_vga_set_state,
1532 .ioctl_wait_idle = r600_ioctl_wait_idle,
1533 .gui_idle = &r600_gui_idle,
1534 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1535 .get_xclk = &r600_get_xclk,
1536 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1538 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1539 .set_page = &rs600_gart_set_page,
1542 [RADEON_RING_TYPE_GFX_INDEX] = {
1543 .ib_execute = &evergreen_ring_ib_execute,
1544 .emit_fence = &r600_fence_ring_emit,
1545 .emit_semaphore = &r600_semaphore_ring_emit,
1546 .cs_parse = &evergreen_cs_parse,
1547 .ring_test = &r600_ring_test,
1548 .ib_test = &r600_ib_test,
1549 .is_lockup = &evergreen_gfx_is_lockup,
1550 .get_rptr = &radeon_ring_generic_get_rptr,
1551 .get_wptr = &radeon_ring_generic_get_wptr,
1552 .set_wptr = &radeon_ring_generic_set_wptr,
1554 [R600_RING_TYPE_DMA_INDEX] = {
1555 .ib_execute = &evergreen_dma_ring_ib_execute,
1556 .emit_fence = &evergreen_dma_fence_ring_emit,
1557 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1558 .cs_parse = &evergreen_dma_cs_parse,
1559 .ring_test = &r600_dma_ring_test,
1560 .ib_test = &r600_dma_ib_test,
1561 .is_lockup = &evergreen_dma_is_lockup,
1562 .get_rptr = &radeon_ring_generic_get_rptr,
1563 .get_wptr = &radeon_ring_generic_get_wptr,
1564 .set_wptr = &radeon_ring_generic_set_wptr,
1566 [R600_RING_TYPE_UVD_INDEX] = {
1567 .ib_execute = &r600_uvd_ib_execute,
1568 .emit_fence = &r600_uvd_fence_emit,
1569 .emit_semaphore = &r600_uvd_semaphore_emit,
1570 .cs_parse = &radeon_uvd_cs_parse,
1571 .ring_test = &r600_uvd_ring_test,
1572 .ib_test = &r600_uvd_ib_test,
1573 .is_lockup = &radeon_ring_test_lockup,
1574 .get_rptr = &radeon_ring_generic_get_rptr,
1575 .get_wptr = &radeon_ring_generic_get_wptr,
1576 .set_wptr = &radeon_ring_generic_set_wptr,
1580 .set = &evergreen_irq_set,
1581 .process = &evergreen_irq_process,
1584 .bandwidth_update = &evergreen_bandwidth_update,
1585 .get_vblank_counter = &evergreen_get_vblank_counter,
1586 .wait_for_vblank = &dce4_wait_for_vblank,
1587 .set_backlight_level = &atombios_set_backlight_level,
1588 .get_backlight_level = &atombios_get_backlight_level,
1589 .hdmi_enable = &evergreen_hdmi_enable,
1590 .hdmi_setmode = &evergreen_hdmi_setmode,
1593 .blit = &r600_copy_blit,
1594 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1595 .dma = &evergreen_copy_dma,
1596 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1597 .copy = &evergreen_copy_dma,
1598 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1601 .set_reg = r600_set_surface_reg,
1602 .clear_reg = r600_clear_surface_reg,
1605 .init = &evergreen_hpd_init,
1606 .fini = &evergreen_hpd_fini,
1607 .sense = &evergreen_hpd_sense,
1608 .set_polarity = &evergreen_hpd_set_polarity,
1611 .misc = &evergreen_pm_misc,
1612 .prepare = &evergreen_pm_prepare,
1613 .finish = &evergreen_pm_finish,
1614 .init_profile = &sumo_pm_init_profile,
1615 .get_dynpm_state = &r600_pm_get_dynpm_state,
1616 .get_engine_clock = &radeon_atom_get_engine_clock,
1617 .set_engine_clock = &radeon_atom_set_engine_clock,
1618 .get_memory_clock = NULL,
1619 .set_memory_clock = NULL,
1620 .get_pcie_lanes = NULL,
1621 .set_pcie_lanes = NULL,
1622 .set_clock_gating = NULL,
1623 .set_uvd_clocks = &sumo_set_uvd_clocks,
1624 .get_temperature = &sumo_get_temp,
1627 .init = &sumo_dpm_init,
1628 .setup_asic = &sumo_dpm_setup_asic,
1629 .enable = &sumo_dpm_enable,
1630 .disable = &sumo_dpm_disable,
1631 .pre_set_power_state = &sumo_dpm_pre_set_power_state,
1632 .set_power_state = &sumo_dpm_set_power_state,
1633 .post_set_power_state = &sumo_dpm_post_set_power_state,
1634 .display_configuration_changed = &sumo_dpm_display_configuration_changed,
1635 .fini = &sumo_dpm_fini,
1636 .get_sclk = &sumo_dpm_get_sclk,
1637 .get_mclk = &sumo_dpm_get_mclk,
1638 .print_power_state = &sumo_dpm_print_power_state,
1641 .pre_page_flip = &evergreen_pre_page_flip,
1642 .page_flip = &evergreen_page_flip,
1643 .post_page_flip = &evergreen_post_page_flip,
1647 static struct radeon_asic btc_asic = {
1648 .init = &evergreen_init,
1649 .fini = &evergreen_fini,
1650 .suspend = &evergreen_suspend,
1651 .resume = &evergreen_resume,
1652 .asic_reset = &evergreen_asic_reset,
1653 .vga_set_state = &r600_vga_set_state,
1654 .ioctl_wait_idle = r600_ioctl_wait_idle,
1655 .gui_idle = &r600_gui_idle,
1656 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1657 .get_xclk = &rv770_get_xclk,
1658 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1660 .tlb_flush = &evergreen_pcie_gart_tlb_flush,
1661 .set_page = &rs600_gart_set_page,
1664 [RADEON_RING_TYPE_GFX_INDEX] = {
1665 .ib_execute = &evergreen_ring_ib_execute,
1666 .emit_fence = &r600_fence_ring_emit,
1667 .emit_semaphore = &r600_semaphore_ring_emit,
1668 .cs_parse = &evergreen_cs_parse,
1669 .ring_test = &r600_ring_test,
1670 .ib_test = &r600_ib_test,
1671 .is_lockup = &evergreen_gfx_is_lockup,
1672 .get_rptr = &radeon_ring_generic_get_rptr,
1673 .get_wptr = &radeon_ring_generic_get_wptr,
1674 .set_wptr = &radeon_ring_generic_set_wptr,
1676 [R600_RING_TYPE_DMA_INDEX] = {
1677 .ib_execute = &evergreen_dma_ring_ib_execute,
1678 .emit_fence = &evergreen_dma_fence_ring_emit,
1679 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1680 .cs_parse = &evergreen_dma_cs_parse,
1681 .ring_test = &r600_dma_ring_test,
1682 .ib_test = &r600_dma_ib_test,
1683 .is_lockup = &evergreen_dma_is_lockup,
1684 .get_rptr = &radeon_ring_generic_get_rptr,
1685 .get_wptr = &radeon_ring_generic_get_wptr,
1686 .set_wptr = &radeon_ring_generic_set_wptr,
1688 [R600_RING_TYPE_UVD_INDEX] = {
1689 .ib_execute = &r600_uvd_ib_execute,
1690 .emit_fence = &r600_uvd_fence_emit,
1691 .emit_semaphore = &r600_uvd_semaphore_emit,
1692 .cs_parse = &radeon_uvd_cs_parse,
1693 .ring_test = &r600_uvd_ring_test,
1694 .ib_test = &r600_uvd_ib_test,
1695 .is_lockup = &radeon_ring_test_lockup,
1696 .get_rptr = &radeon_ring_generic_get_rptr,
1697 .get_wptr = &radeon_ring_generic_get_wptr,
1698 .set_wptr = &radeon_ring_generic_set_wptr,
1702 .set = &evergreen_irq_set,
1703 .process = &evergreen_irq_process,
1706 .bandwidth_update = &evergreen_bandwidth_update,
1707 .get_vblank_counter = &evergreen_get_vblank_counter,
1708 .wait_for_vblank = &dce4_wait_for_vblank,
1709 .set_backlight_level = &atombios_set_backlight_level,
1710 .get_backlight_level = &atombios_get_backlight_level,
1711 .hdmi_enable = &evergreen_hdmi_enable,
1712 .hdmi_setmode = &evergreen_hdmi_setmode,
1715 .blit = &r600_copy_blit,
1716 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1717 .dma = &evergreen_copy_dma,
1718 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1719 .copy = &evergreen_copy_dma,
1720 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1723 .set_reg = r600_set_surface_reg,
1724 .clear_reg = r600_clear_surface_reg,
1727 .init = &evergreen_hpd_init,
1728 .fini = &evergreen_hpd_fini,
1729 .sense = &evergreen_hpd_sense,
1730 .set_polarity = &evergreen_hpd_set_polarity,
1733 .misc = &evergreen_pm_misc,
1734 .prepare = &evergreen_pm_prepare,
1735 .finish = &evergreen_pm_finish,
1736 .init_profile = &btc_pm_init_profile,
1737 .get_dynpm_state = &r600_pm_get_dynpm_state,
1738 .get_engine_clock = &radeon_atom_get_engine_clock,
1739 .set_engine_clock = &radeon_atom_set_engine_clock,
1740 .get_memory_clock = &radeon_atom_get_memory_clock,
1741 .set_memory_clock = &radeon_atom_set_memory_clock,
1742 .get_pcie_lanes = &r600_get_pcie_lanes,
1743 .set_pcie_lanes = &r600_set_pcie_lanes,
1744 .set_clock_gating = NULL,
1745 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1746 .get_temperature = &evergreen_get_temp,
1749 .init = &btc_dpm_init,
1750 .setup_asic = &btc_dpm_setup_asic,
1751 .enable = &btc_dpm_enable,
1752 .disable = &btc_dpm_disable,
1753 .pre_set_power_state = &btc_dpm_pre_set_power_state,
1754 .set_power_state = &btc_dpm_set_power_state,
1755 .post_set_power_state = &btc_dpm_post_set_power_state,
1756 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1757 .fini = &btc_dpm_fini,
1758 .get_sclk = &btc_dpm_get_sclk,
1759 .get_mclk = &btc_dpm_get_mclk,
1760 .print_power_state = &rv770_dpm_print_power_state,
1763 .pre_page_flip = &evergreen_pre_page_flip,
1764 .page_flip = &evergreen_page_flip,
1765 .post_page_flip = &evergreen_post_page_flip,
1769 static struct radeon_asic cayman_asic = {
1770 .init = &cayman_init,
1771 .fini = &cayman_fini,
1772 .suspend = &cayman_suspend,
1773 .resume = &cayman_resume,
1774 .asic_reset = &cayman_asic_reset,
1775 .vga_set_state = &r600_vga_set_state,
1776 .ioctl_wait_idle = r600_ioctl_wait_idle,
1777 .gui_idle = &r600_gui_idle,
1778 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1779 .get_xclk = &rv770_get_xclk,
1780 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1782 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1783 .set_page = &rs600_gart_set_page,
1786 .init = &cayman_vm_init,
1787 .fini = &cayman_vm_fini,
1788 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1789 .set_page = &cayman_vm_set_page,
1792 [RADEON_RING_TYPE_GFX_INDEX] = {
1793 .ib_execute = &cayman_ring_ib_execute,
1794 .ib_parse = &evergreen_ib_parse,
1795 .emit_fence = &cayman_fence_ring_emit,
1796 .emit_semaphore = &r600_semaphore_ring_emit,
1797 .cs_parse = &evergreen_cs_parse,
1798 .ring_test = &r600_ring_test,
1799 .ib_test = &r600_ib_test,
1800 .is_lockup = &cayman_gfx_is_lockup,
1801 .vm_flush = &cayman_vm_flush,
1802 .get_rptr = &radeon_ring_generic_get_rptr,
1803 .get_wptr = &radeon_ring_generic_get_wptr,
1804 .set_wptr = &radeon_ring_generic_set_wptr,
1806 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1807 .ib_execute = &cayman_ring_ib_execute,
1808 .ib_parse = &evergreen_ib_parse,
1809 .emit_fence = &cayman_fence_ring_emit,
1810 .emit_semaphore = &r600_semaphore_ring_emit,
1811 .cs_parse = &evergreen_cs_parse,
1812 .ring_test = &r600_ring_test,
1813 .ib_test = &r600_ib_test,
1814 .is_lockup = &cayman_gfx_is_lockup,
1815 .vm_flush = &cayman_vm_flush,
1816 .get_rptr = &radeon_ring_generic_get_rptr,
1817 .get_wptr = &radeon_ring_generic_get_wptr,
1818 .set_wptr = &radeon_ring_generic_set_wptr,
1820 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1821 .ib_execute = &cayman_ring_ib_execute,
1822 .ib_parse = &evergreen_ib_parse,
1823 .emit_fence = &cayman_fence_ring_emit,
1824 .emit_semaphore = &r600_semaphore_ring_emit,
1825 .cs_parse = &evergreen_cs_parse,
1826 .ring_test = &r600_ring_test,
1827 .ib_test = &r600_ib_test,
1828 .is_lockup = &cayman_gfx_is_lockup,
1829 .vm_flush = &cayman_vm_flush,
1830 .get_rptr = &radeon_ring_generic_get_rptr,
1831 .get_wptr = &radeon_ring_generic_get_wptr,
1832 .set_wptr = &radeon_ring_generic_set_wptr,
1834 [R600_RING_TYPE_DMA_INDEX] = {
1835 .ib_execute = &cayman_dma_ring_ib_execute,
1836 .ib_parse = &evergreen_dma_ib_parse,
1837 .emit_fence = &evergreen_dma_fence_ring_emit,
1838 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1839 .cs_parse = &evergreen_dma_cs_parse,
1840 .ring_test = &r600_dma_ring_test,
1841 .ib_test = &r600_dma_ib_test,
1842 .is_lockup = &cayman_dma_is_lockup,
1843 .vm_flush = &cayman_dma_vm_flush,
1844 .get_rptr = &radeon_ring_generic_get_rptr,
1845 .get_wptr = &radeon_ring_generic_get_wptr,
1846 .set_wptr = &radeon_ring_generic_set_wptr,
1848 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
1849 .ib_execute = &cayman_dma_ring_ib_execute,
1850 .ib_parse = &evergreen_dma_ib_parse,
1851 .emit_fence = &evergreen_dma_fence_ring_emit,
1852 .emit_semaphore = &r600_dma_semaphore_ring_emit,
1853 .cs_parse = &evergreen_dma_cs_parse,
1854 .ring_test = &r600_dma_ring_test,
1855 .ib_test = &r600_dma_ib_test,
1856 .is_lockup = &cayman_dma_is_lockup,
1857 .vm_flush = &cayman_dma_vm_flush,
1858 .get_rptr = &radeon_ring_generic_get_rptr,
1859 .get_wptr = &radeon_ring_generic_get_wptr,
1860 .set_wptr = &radeon_ring_generic_set_wptr,
1862 [R600_RING_TYPE_UVD_INDEX] = {
1863 .ib_execute = &r600_uvd_ib_execute,
1864 .emit_fence = &r600_uvd_fence_emit,
1865 .emit_semaphore = &cayman_uvd_semaphore_emit,
1866 .cs_parse = &radeon_uvd_cs_parse,
1867 .ring_test = &r600_uvd_ring_test,
1868 .ib_test = &r600_uvd_ib_test,
1869 .is_lockup = &radeon_ring_test_lockup,
1870 .get_rptr = &radeon_ring_generic_get_rptr,
1871 .get_wptr = &radeon_ring_generic_get_wptr,
1872 .set_wptr = &radeon_ring_generic_set_wptr,
1876 .set = &evergreen_irq_set,
1877 .process = &evergreen_irq_process,
1880 .bandwidth_update = &evergreen_bandwidth_update,
1881 .get_vblank_counter = &evergreen_get_vblank_counter,
1882 .wait_for_vblank = &dce4_wait_for_vblank,
1883 .set_backlight_level = &atombios_set_backlight_level,
1884 .get_backlight_level = &atombios_get_backlight_level,
1885 .hdmi_enable = &evergreen_hdmi_enable,
1886 .hdmi_setmode = &evergreen_hdmi_setmode,
1889 .blit = &r600_copy_blit,
1890 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
1891 .dma = &evergreen_copy_dma,
1892 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
1893 .copy = &evergreen_copy_dma,
1894 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
1897 .set_reg = r600_set_surface_reg,
1898 .clear_reg = r600_clear_surface_reg,
1901 .init = &evergreen_hpd_init,
1902 .fini = &evergreen_hpd_fini,
1903 .sense = &evergreen_hpd_sense,
1904 .set_polarity = &evergreen_hpd_set_polarity,
1907 .misc = &evergreen_pm_misc,
1908 .prepare = &evergreen_pm_prepare,
1909 .finish = &evergreen_pm_finish,
1910 .init_profile = &btc_pm_init_profile,
1911 .get_dynpm_state = &r600_pm_get_dynpm_state,
1912 .get_engine_clock = &radeon_atom_get_engine_clock,
1913 .set_engine_clock = &radeon_atom_set_engine_clock,
1914 .get_memory_clock = &radeon_atom_get_memory_clock,
1915 .set_memory_clock = &radeon_atom_set_memory_clock,
1916 .get_pcie_lanes = &r600_get_pcie_lanes,
1917 .set_pcie_lanes = &r600_set_pcie_lanes,
1918 .set_clock_gating = NULL,
1919 .set_uvd_clocks = &evergreen_set_uvd_clocks,
1920 .get_temperature = &evergreen_get_temp,
1923 .init = &ni_dpm_init,
1924 .setup_asic = &ni_dpm_setup_asic,
1925 .enable = &ni_dpm_enable,
1926 .disable = &ni_dpm_disable,
1927 .pre_set_power_state = &ni_dpm_pre_set_power_state,
1928 .set_power_state = &ni_dpm_set_power_state,
1929 .post_set_power_state = &ni_dpm_post_set_power_state,
1930 .display_configuration_changed = &cypress_dpm_display_configuration_changed,
1931 .fini = &ni_dpm_fini,
1932 .get_sclk = &ni_dpm_get_sclk,
1933 .get_mclk = &ni_dpm_get_mclk,
1934 .print_power_state = &ni_dpm_print_power_state,
1937 .pre_page_flip = &evergreen_pre_page_flip,
1938 .page_flip = &evergreen_page_flip,
1939 .post_page_flip = &evergreen_post_page_flip,
1943 static struct radeon_asic trinity_asic = {
1944 .init = &cayman_init,
1945 .fini = &cayman_fini,
1946 .suspend = &cayman_suspend,
1947 .resume = &cayman_resume,
1948 .asic_reset = &cayman_asic_reset,
1949 .vga_set_state = &r600_vga_set_state,
1950 .ioctl_wait_idle = r600_ioctl_wait_idle,
1951 .gui_idle = &r600_gui_idle,
1952 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
1953 .get_xclk = &r600_get_xclk,
1954 .get_gpu_clock_counter = &r600_get_gpu_clock_counter,
1956 .tlb_flush = &cayman_pcie_gart_tlb_flush,
1957 .set_page = &rs600_gart_set_page,
1960 .init = &cayman_vm_init,
1961 .fini = &cayman_vm_fini,
1962 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
1963 .set_page = &cayman_vm_set_page,
1966 [RADEON_RING_TYPE_GFX_INDEX] = {
1967 .ib_execute = &cayman_ring_ib_execute,
1968 .ib_parse = &evergreen_ib_parse,
1969 .emit_fence = &cayman_fence_ring_emit,
1970 .emit_semaphore = &r600_semaphore_ring_emit,
1971 .cs_parse = &evergreen_cs_parse,
1972 .ring_test = &r600_ring_test,
1973 .ib_test = &r600_ib_test,
1974 .is_lockup = &cayman_gfx_is_lockup,
1975 .vm_flush = &cayman_vm_flush,
1976 .get_rptr = &radeon_ring_generic_get_rptr,
1977 .get_wptr = &radeon_ring_generic_get_wptr,
1978 .set_wptr = &radeon_ring_generic_set_wptr,
1980 [CAYMAN_RING_TYPE_CP1_INDEX] = {
1981 .ib_execute = &cayman_ring_ib_execute,
1982 .ib_parse = &evergreen_ib_parse,
1983 .emit_fence = &cayman_fence_ring_emit,
1984 .emit_semaphore = &r600_semaphore_ring_emit,
1985 .cs_parse = &evergreen_cs_parse,
1986 .ring_test = &r600_ring_test,
1987 .ib_test = &r600_ib_test,
1988 .is_lockup = &cayman_gfx_is_lockup,
1989 .vm_flush = &cayman_vm_flush,
1990 .get_rptr = &radeon_ring_generic_get_rptr,
1991 .get_wptr = &radeon_ring_generic_get_wptr,
1992 .set_wptr = &radeon_ring_generic_set_wptr,
1994 [CAYMAN_RING_TYPE_CP2_INDEX] = {
1995 .ib_execute = &cayman_ring_ib_execute,
1996 .ib_parse = &evergreen_ib_parse,
1997 .emit_fence = &cayman_fence_ring_emit,
1998 .emit_semaphore = &r600_semaphore_ring_emit,
1999 .cs_parse = &evergreen_cs_parse,
2000 .ring_test = &r600_ring_test,
2001 .ib_test = &r600_ib_test,
2002 .is_lockup = &cayman_gfx_is_lockup,
2003 .vm_flush = &cayman_vm_flush,
2004 .get_rptr = &radeon_ring_generic_get_rptr,
2005 .get_wptr = &radeon_ring_generic_get_wptr,
2006 .set_wptr = &radeon_ring_generic_set_wptr,
2008 [R600_RING_TYPE_DMA_INDEX] = {
2009 .ib_execute = &cayman_dma_ring_ib_execute,
2010 .ib_parse = &evergreen_dma_ib_parse,
2011 .emit_fence = &evergreen_dma_fence_ring_emit,
2012 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2013 .cs_parse = &evergreen_dma_cs_parse,
2014 .ring_test = &r600_dma_ring_test,
2015 .ib_test = &r600_dma_ib_test,
2016 .is_lockup = &cayman_dma_is_lockup,
2017 .vm_flush = &cayman_dma_vm_flush,
2018 .get_rptr = &radeon_ring_generic_get_rptr,
2019 .get_wptr = &radeon_ring_generic_get_wptr,
2020 .set_wptr = &radeon_ring_generic_set_wptr,
2022 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2023 .ib_execute = &cayman_dma_ring_ib_execute,
2024 .ib_parse = &evergreen_dma_ib_parse,
2025 .emit_fence = &evergreen_dma_fence_ring_emit,
2026 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2027 .cs_parse = &evergreen_dma_cs_parse,
2028 .ring_test = &r600_dma_ring_test,
2029 .ib_test = &r600_dma_ib_test,
2030 .is_lockup = &cayman_dma_is_lockup,
2031 .vm_flush = &cayman_dma_vm_flush,
2032 .get_rptr = &radeon_ring_generic_get_rptr,
2033 .get_wptr = &radeon_ring_generic_get_wptr,
2034 .set_wptr = &radeon_ring_generic_set_wptr,
2036 [R600_RING_TYPE_UVD_INDEX] = {
2037 .ib_execute = &r600_uvd_ib_execute,
2038 .emit_fence = &r600_uvd_fence_emit,
2039 .emit_semaphore = &cayman_uvd_semaphore_emit,
2040 .cs_parse = &radeon_uvd_cs_parse,
2041 .ring_test = &r600_uvd_ring_test,
2042 .ib_test = &r600_uvd_ib_test,
2043 .is_lockup = &radeon_ring_test_lockup,
2044 .get_rptr = &radeon_ring_generic_get_rptr,
2045 .get_wptr = &radeon_ring_generic_get_wptr,
2046 .set_wptr = &radeon_ring_generic_set_wptr,
2050 .set = &evergreen_irq_set,
2051 .process = &evergreen_irq_process,
2054 .bandwidth_update = &dce6_bandwidth_update,
2055 .get_vblank_counter = &evergreen_get_vblank_counter,
2056 .wait_for_vblank = &dce4_wait_for_vblank,
2057 .set_backlight_level = &atombios_set_backlight_level,
2058 .get_backlight_level = &atombios_get_backlight_level,
2061 .blit = &r600_copy_blit,
2062 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2063 .dma = &evergreen_copy_dma,
2064 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2065 .copy = &evergreen_copy_dma,
2066 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2069 .set_reg = r600_set_surface_reg,
2070 .clear_reg = r600_clear_surface_reg,
2073 .init = &evergreen_hpd_init,
2074 .fini = &evergreen_hpd_fini,
2075 .sense = &evergreen_hpd_sense,
2076 .set_polarity = &evergreen_hpd_set_polarity,
2079 .misc = &evergreen_pm_misc,
2080 .prepare = &evergreen_pm_prepare,
2081 .finish = &evergreen_pm_finish,
2082 .init_profile = &sumo_pm_init_profile,
2083 .get_dynpm_state = &r600_pm_get_dynpm_state,
2084 .get_engine_clock = &radeon_atom_get_engine_clock,
2085 .set_engine_clock = &radeon_atom_set_engine_clock,
2086 .get_memory_clock = NULL,
2087 .set_memory_clock = NULL,
2088 .get_pcie_lanes = NULL,
2089 .set_pcie_lanes = NULL,
2090 .set_clock_gating = NULL,
2091 .set_uvd_clocks = &sumo_set_uvd_clocks,
2092 .get_temperature = &tn_get_temp,
2095 .init = &trinity_dpm_init,
2096 .setup_asic = &trinity_dpm_setup_asic,
2097 .enable = &trinity_dpm_enable,
2098 .disable = &trinity_dpm_disable,
2099 .pre_set_power_state = &trinity_dpm_pre_set_power_state,
2100 .set_power_state = &trinity_dpm_set_power_state,
2101 .post_set_power_state = &trinity_dpm_post_set_power_state,
2102 .display_configuration_changed = &trinity_dpm_display_configuration_changed,
2103 .fini = &trinity_dpm_fini,
2104 .get_sclk = &trinity_dpm_get_sclk,
2105 .get_mclk = &trinity_dpm_get_mclk,
2106 .print_power_state = &trinity_dpm_print_power_state,
2109 .pre_page_flip = &evergreen_pre_page_flip,
2110 .page_flip = &evergreen_page_flip,
2111 .post_page_flip = &evergreen_post_page_flip,
2115 static struct radeon_asic si_asic = {
2118 .suspend = &si_suspend,
2119 .resume = &si_resume,
2120 .asic_reset = &si_asic_reset,
2121 .vga_set_state = &r600_vga_set_state,
2122 .ioctl_wait_idle = r600_ioctl_wait_idle,
2123 .gui_idle = &r600_gui_idle,
2124 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2125 .get_xclk = &si_get_xclk,
2126 .get_gpu_clock_counter = &si_get_gpu_clock_counter,
2128 .tlb_flush = &si_pcie_gart_tlb_flush,
2129 .set_page = &rs600_gart_set_page,
2132 .init = &si_vm_init,
2133 .fini = &si_vm_fini,
2134 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2135 .set_page = &si_vm_set_page,
2138 [RADEON_RING_TYPE_GFX_INDEX] = {
2139 .ib_execute = &si_ring_ib_execute,
2140 .ib_parse = &si_ib_parse,
2141 .emit_fence = &si_fence_ring_emit,
2142 .emit_semaphore = &r600_semaphore_ring_emit,
2144 .ring_test = &r600_ring_test,
2145 .ib_test = &r600_ib_test,
2146 .is_lockup = &si_gfx_is_lockup,
2147 .vm_flush = &si_vm_flush,
2148 .get_rptr = &radeon_ring_generic_get_rptr,
2149 .get_wptr = &radeon_ring_generic_get_wptr,
2150 .set_wptr = &radeon_ring_generic_set_wptr,
2152 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2153 .ib_execute = &si_ring_ib_execute,
2154 .ib_parse = &si_ib_parse,
2155 .emit_fence = &si_fence_ring_emit,
2156 .emit_semaphore = &r600_semaphore_ring_emit,
2158 .ring_test = &r600_ring_test,
2159 .ib_test = &r600_ib_test,
2160 .is_lockup = &si_gfx_is_lockup,
2161 .vm_flush = &si_vm_flush,
2162 .get_rptr = &radeon_ring_generic_get_rptr,
2163 .get_wptr = &radeon_ring_generic_get_wptr,
2164 .set_wptr = &radeon_ring_generic_set_wptr,
2166 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2167 .ib_execute = &si_ring_ib_execute,
2168 .ib_parse = &si_ib_parse,
2169 .emit_fence = &si_fence_ring_emit,
2170 .emit_semaphore = &r600_semaphore_ring_emit,
2172 .ring_test = &r600_ring_test,
2173 .ib_test = &r600_ib_test,
2174 .is_lockup = &si_gfx_is_lockup,
2175 .vm_flush = &si_vm_flush,
2176 .get_rptr = &radeon_ring_generic_get_rptr,
2177 .get_wptr = &radeon_ring_generic_get_wptr,
2178 .set_wptr = &radeon_ring_generic_set_wptr,
2180 [R600_RING_TYPE_DMA_INDEX] = {
2181 .ib_execute = &cayman_dma_ring_ib_execute,
2182 .ib_parse = &evergreen_dma_ib_parse,
2183 .emit_fence = &evergreen_dma_fence_ring_emit,
2184 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2186 .ring_test = &r600_dma_ring_test,
2187 .ib_test = &r600_dma_ib_test,
2188 .is_lockup = &si_dma_is_lockup,
2189 .vm_flush = &si_dma_vm_flush,
2190 .get_rptr = &radeon_ring_generic_get_rptr,
2191 .get_wptr = &radeon_ring_generic_get_wptr,
2192 .set_wptr = &radeon_ring_generic_set_wptr,
2194 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2195 .ib_execute = &cayman_dma_ring_ib_execute,
2196 .ib_parse = &evergreen_dma_ib_parse,
2197 .emit_fence = &evergreen_dma_fence_ring_emit,
2198 .emit_semaphore = &r600_dma_semaphore_ring_emit,
2200 .ring_test = &r600_dma_ring_test,
2201 .ib_test = &r600_dma_ib_test,
2202 .is_lockup = &si_dma_is_lockup,
2203 .vm_flush = &si_dma_vm_flush,
2204 .get_rptr = &radeon_ring_generic_get_rptr,
2205 .get_wptr = &radeon_ring_generic_get_wptr,
2206 .set_wptr = &radeon_ring_generic_set_wptr,
2208 [R600_RING_TYPE_UVD_INDEX] = {
2209 .ib_execute = &r600_uvd_ib_execute,
2210 .emit_fence = &r600_uvd_fence_emit,
2211 .emit_semaphore = &cayman_uvd_semaphore_emit,
2212 .cs_parse = &radeon_uvd_cs_parse,
2213 .ring_test = &r600_uvd_ring_test,
2214 .ib_test = &r600_uvd_ib_test,
2215 .is_lockup = &radeon_ring_test_lockup,
2216 .get_rptr = &radeon_ring_generic_get_rptr,
2217 .get_wptr = &radeon_ring_generic_get_wptr,
2218 .set_wptr = &radeon_ring_generic_set_wptr,
2223 .process = &si_irq_process,
2226 .bandwidth_update = &dce6_bandwidth_update,
2227 .get_vblank_counter = &evergreen_get_vblank_counter,
2228 .wait_for_vblank = &dce4_wait_for_vblank,
2229 .set_backlight_level = &atombios_set_backlight_level,
2230 .get_backlight_level = &atombios_get_backlight_level,
2234 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2235 .dma = &si_copy_dma,
2236 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2237 .copy = &si_copy_dma,
2238 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2241 .set_reg = r600_set_surface_reg,
2242 .clear_reg = r600_clear_surface_reg,
2245 .init = &evergreen_hpd_init,
2246 .fini = &evergreen_hpd_fini,
2247 .sense = &evergreen_hpd_sense,
2248 .set_polarity = &evergreen_hpd_set_polarity,
2251 .misc = &evergreen_pm_misc,
2252 .prepare = &evergreen_pm_prepare,
2253 .finish = &evergreen_pm_finish,
2254 .init_profile = &sumo_pm_init_profile,
2255 .get_dynpm_state = &r600_pm_get_dynpm_state,
2256 .get_engine_clock = &radeon_atom_get_engine_clock,
2257 .set_engine_clock = &radeon_atom_set_engine_clock,
2258 .get_memory_clock = &radeon_atom_get_memory_clock,
2259 .set_memory_clock = &radeon_atom_set_memory_clock,
2260 .get_pcie_lanes = &r600_get_pcie_lanes,
2261 .set_pcie_lanes = &r600_set_pcie_lanes,
2262 .set_clock_gating = NULL,
2263 .set_uvd_clocks = &si_set_uvd_clocks,
2264 .get_temperature = &si_get_temp,
2267 .init = &si_dpm_init,
2268 .setup_asic = &si_dpm_setup_asic,
2269 .enable = &si_dpm_enable,
2270 .disable = &si_dpm_disable,
2271 .pre_set_power_state = &si_dpm_pre_set_power_state,
2272 .set_power_state = &si_dpm_set_power_state,
2273 .post_set_power_state = &si_dpm_post_set_power_state,
2274 .display_configuration_changed = &si_dpm_display_configuration_changed,
2275 .fini = &si_dpm_fini,
2276 .get_sclk = &ni_dpm_get_sclk,
2277 .get_mclk = &ni_dpm_get_mclk,
2278 .print_power_state = &ni_dpm_print_power_state,
2281 .pre_page_flip = &evergreen_pre_page_flip,
2282 .page_flip = &evergreen_page_flip,
2283 .post_page_flip = &evergreen_post_page_flip,
2287 static struct radeon_asic ci_asic = {
2290 .suspend = &cik_suspend,
2291 .resume = &cik_resume,
2292 .asic_reset = &cik_asic_reset,
2293 .vga_set_state = &r600_vga_set_state,
2294 .ioctl_wait_idle = NULL,
2295 .gui_idle = &r600_gui_idle,
2296 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2297 .get_xclk = &cik_get_xclk,
2298 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2300 .tlb_flush = &cik_pcie_gart_tlb_flush,
2301 .set_page = &rs600_gart_set_page,
2304 .init = &cik_vm_init,
2305 .fini = &cik_vm_fini,
2306 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2307 .set_page = &cik_vm_set_page,
2310 [RADEON_RING_TYPE_GFX_INDEX] = {
2311 .ib_execute = &cik_ring_ib_execute,
2312 .ib_parse = &cik_ib_parse,
2313 .emit_fence = &cik_fence_gfx_ring_emit,
2314 .emit_semaphore = &cik_semaphore_ring_emit,
2316 .ring_test = &cik_ring_test,
2317 .ib_test = &cik_ib_test,
2318 .is_lockup = &cik_gfx_is_lockup,
2319 .vm_flush = &cik_vm_flush,
2320 .get_rptr = &radeon_ring_generic_get_rptr,
2321 .get_wptr = &radeon_ring_generic_get_wptr,
2322 .set_wptr = &radeon_ring_generic_set_wptr,
2324 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2325 .ib_execute = &cik_ring_ib_execute,
2326 .ib_parse = &cik_ib_parse,
2327 .emit_fence = &cik_fence_compute_ring_emit,
2328 .emit_semaphore = &cik_semaphore_ring_emit,
2330 .ring_test = &cik_ring_test,
2331 .ib_test = &cik_ib_test,
2332 .is_lockup = &cik_gfx_is_lockup,
2333 .vm_flush = &cik_vm_flush,
2334 .get_rptr = &cik_compute_ring_get_rptr,
2335 .get_wptr = &cik_compute_ring_get_wptr,
2336 .set_wptr = &cik_compute_ring_set_wptr,
2338 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2339 .ib_execute = &cik_ring_ib_execute,
2340 .ib_parse = &cik_ib_parse,
2341 .emit_fence = &cik_fence_compute_ring_emit,
2342 .emit_semaphore = &cik_semaphore_ring_emit,
2344 .ring_test = &cik_ring_test,
2345 .ib_test = &cik_ib_test,
2346 .is_lockup = &cik_gfx_is_lockup,
2347 .vm_flush = &cik_vm_flush,
2348 .get_rptr = &cik_compute_ring_get_rptr,
2349 .get_wptr = &cik_compute_ring_get_wptr,
2350 .set_wptr = &cik_compute_ring_set_wptr,
2352 [R600_RING_TYPE_DMA_INDEX] = {
2353 .ib_execute = &cik_sdma_ring_ib_execute,
2354 .ib_parse = &cik_ib_parse,
2355 .emit_fence = &cik_sdma_fence_ring_emit,
2356 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2358 .ring_test = &cik_sdma_ring_test,
2359 .ib_test = &cik_sdma_ib_test,
2360 .is_lockup = &cik_sdma_is_lockup,
2361 .vm_flush = &cik_dma_vm_flush,
2362 .get_rptr = &radeon_ring_generic_get_rptr,
2363 .get_wptr = &radeon_ring_generic_get_wptr,
2364 .set_wptr = &radeon_ring_generic_set_wptr,
2366 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2367 .ib_execute = &cik_sdma_ring_ib_execute,
2368 .ib_parse = &cik_ib_parse,
2369 .emit_fence = &cik_sdma_fence_ring_emit,
2370 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2372 .ring_test = &cik_sdma_ring_test,
2373 .ib_test = &cik_sdma_ib_test,
2374 .is_lockup = &cik_sdma_is_lockup,
2375 .vm_flush = &cik_dma_vm_flush,
2376 .get_rptr = &radeon_ring_generic_get_rptr,
2377 .get_wptr = &radeon_ring_generic_get_wptr,
2378 .set_wptr = &radeon_ring_generic_set_wptr,
2380 [R600_RING_TYPE_UVD_INDEX] = {
2381 .ib_execute = &r600_uvd_ib_execute,
2382 .emit_fence = &r600_uvd_fence_emit,
2383 .emit_semaphore = &cayman_uvd_semaphore_emit,
2384 .cs_parse = &radeon_uvd_cs_parse,
2385 .ring_test = &r600_uvd_ring_test,
2386 .ib_test = &r600_uvd_ib_test,
2387 .is_lockup = &radeon_ring_test_lockup,
2388 .get_rptr = &radeon_ring_generic_get_rptr,
2389 .get_wptr = &radeon_ring_generic_get_wptr,
2390 .set_wptr = &radeon_ring_generic_set_wptr,
2394 .set = &cik_irq_set,
2395 .process = &cik_irq_process,
2398 .bandwidth_update = &dce8_bandwidth_update,
2399 .get_vblank_counter = &evergreen_get_vblank_counter,
2400 .wait_for_vblank = &dce4_wait_for_vblank,
2404 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2405 .dma = &cik_copy_dma,
2406 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2407 .copy = &cik_copy_dma,
2408 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2411 .set_reg = r600_set_surface_reg,
2412 .clear_reg = r600_clear_surface_reg,
2415 .init = &evergreen_hpd_init,
2416 .fini = &evergreen_hpd_fini,
2417 .sense = &evergreen_hpd_sense,
2418 .set_polarity = &evergreen_hpd_set_polarity,
2421 .misc = &evergreen_pm_misc,
2422 .prepare = &evergreen_pm_prepare,
2423 .finish = &evergreen_pm_finish,
2424 .init_profile = &sumo_pm_init_profile,
2425 .get_dynpm_state = &r600_pm_get_dynpm_state,
2426 .get_engine_clock = &radeon_atom_get_engine_clock,
2427 .set_engine_clock = &radeon_atom_set_engine_clock,
2428 .get_memory_clock = &radeon_atom_get_memory_clock,
2429 .set_memory_clock = &radeon_atom_set_memory_clock,
2430 .get_pcie_lanes = NULL,
2431 .set_pcie_lanes = NULL,
2432 .set_clock_gating = NULL,
2433 .set_uvd_clocks = &cik_set_uvd_clocks,
2436 .pre_page_flip = &evergreen_pre_page_flip,
2437 .page_flip = &evergreen_page_flip,
2438 .post_page_flip = &evergreen_post_page_flip,
2442 static struct radeon_asic kv_asic = {
2445 .suspend = &cik_suspend,
2446 .resume = &cik_resume,
2447 .asic_reset = &cik_asic_reset,
2448 .vga_set_state = &r600_vga_set_state,
2449 .ioctl_wait_idle = NULL,
2450 .gui_idle = &r600_gui_idle,
2451 .mc_wait_for_idle = &evergreen_mc_wait_for_idle,
2452 .get_xclk = &cik_get_xclk,
2453 .get_gpu_clock_counter = &cik_get_gpu_clock_counter,
2455 .tlb_flush = &cik_pcie_gart_tlb_flush,
2456 .set_page = &rs600_gart_set_page,
2459 .init = &cik_vm_init,
2460 .fini = &cik_vm_fini,
2461 .pt_ring_index = R600_RING_TYPE_DMA_INDEX,
2462 .set_page = &cik_vm_set_page,
2465 [RADEON_RING_TYPE_GFX_INDEX] = {
2466 .ib_execute = &cik_ring_ib_execute,
2467 .ib_parse = &cik_ib_parse,
2468 .emit_fence = &cik_fence_gfx_ring_emit,
2469 .emit_semaphore = &cik_semaphore_ring_emit,
2471 .ring_test = &cik_ring_test,
2472 .ib_test = &cik_ib_test,
2473 .is_lockup = &cik_gfx_is_lockup,
2474 .vm_flush = &cik_vm_flush,
2475 .get_rptr = &radeon_ring_generic_get_rptr,
2476 .get_wptr = &radeon_ring_generic_get_wptr,
2477 .set_wptr = &radeon_ring_generic_set_wptr,
2479 [CAYMAN_RING_TYPE_CP1_INDEX] = {
2480 .ib_execute = &cik_ring_ib_execute,
2481 .ib_parse = &cik_ib_parse,
2482 .emit_fence = &cik_fence_compute_ring_emit,
2483 .emit_semaphore = &cik_semaphore_ring_emit,
2485 .ring_test = &cik_ring_test,
2486 .ib_test = &cik_ib_test,
2487 .is_lockup = &cik_gfx_is_lockup,
2488 .vm_flush = &cik_vm_flush,
2489 .get_rptr = &cik_compute_ring_get_rptr,
2490 .get_wptr = &cik_compute_ring_get_wptr,
2491 .set_wptr = &cik_compute_ring_set_wptr,
2493 [CAYMAN_RING_TYPE_CP2_INDEX] = {
2494 .ib_execute = &cik_ring_ib_execute,
2495 .ib_parse = &cik_ib_parse,
2496 .emit_fence = &cik_fence_compute_ring_emit,
2497 .emit_semaphore = &cik_semaphore_ring_emit,
2499 .ring_test = &cik_ring_test,
2500 .ib_test = &cik_ib_test,
2501 .is_lockup = &cik_gfx_is_lockup,
2502 .vm_flush = &cik_vm_flush,
2503 .get_rptr = &cik_compute_ring_get_rptr,
2504 .get_wptr = &cik_compute_ring_get_wptr,
2505 .set_wptr = &cik_compute_ring_set_wptr,
2507 [R600_RING_TYPE_DMA_INDEX] = {
2508 .ib_execute = &cik_sdma_ring_ib_execute,
2509 .ib_parse = &cik_ib_parse,
2510 .emit_fence = &cik_sdma_fence_ring_emit,
2511 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2513 .ring_test = &cik_sdma_ring_test,
2514 .ib_test = &cik_sdma_ib_test,
2515 .is_lockup = &cik_sdma_is_lockup,
2516 .vm_flush = &cik_dma_vm_flush,
2517 .get_rptr = &radeon_ring_generic_get_rptr,
2518 .get_wptr = &radeon_ring_generic_get_wptr,
2519 .set_wptr = &radeon_ring_generic_set_wptr,
2521 [CAYMAN_RING_TYPE_DMA1_INDEX] = {
2522 .ib_execute = &cik_sdma_ring_ib_execute,
2523 .ib_parse = &cik_ib_parse,
2524 .emit_fence = &cik_sdma_fence_ring_emit,
2525 .emit_semaphore = &cik_sdma_semaphore_ring_emit,
2527 .ring_test = &cik_sdma_ring_test,
2528 .ib_test = &cik_sdma_ib_test,
2529 .is_lockup = &cik_sdma_is_lockup,
2530 .vm_flush = &cik_dma_vm_flush,
2531 .get_rptr = &radeon_ring_generic_get_rptr,
2532 .get_wptr = &radeon_ring_generic_get_wptr,
2533 .set_wptr = &radeon_ring_generic_set_wptr,
2535 [R600_RING_TYPE_UVD_INDEX] = {
2536 .ib_execute = &r600_uvd_ib_execute,
2537 .emit_fence = &r600_uvd_fence_emit,
2538 .emit_semaphore = &cayman_uvd_semaphore_emit,
2539 .cs_parse = &radeon_uvd_cs_parse,
2540 .ring_test = &r600_uvd_ring_test,
2541 .ib_test = &r600_uvd_ib_test,
2542 .is_lockup = &radeon_ring_test_lockup,
2543 .get_rptr = &radeon_ring_generic_get_rptr,
2544 .get_wptr = &radeon_ring_generic_get_wptr,
2545 .set_wptr = &radeon_ring_generic_set_wptr,
2549 .set = &cik_irq_set,
2550 .process = &cik_irq_process,
2553 .bandwidth_update = &dce8_bandwidth_update,
2554 .get_vblank_counter = &evergreen_get_vblank_counter,
2555 .wait_for_vblank = &dce4_wait_for_vblank,
2559 .blit_ring_index = RADEON_RING_TYPE_GFX_INDEX,
2560 .dma = &cik_copy_dma,
2561 .dma_ring_index = R600_RING_TYPE_DMA_INDEX,
2562 .copy = &cik_copy_dma,
2563 .copy_ring_index = R600_RING_TYPE_DMA_INDEX,
2566 .set_reg = r600_set_surface_reg,
2567 .clear_reg = r600_clear_surface_reg,
2570 .init = &evergreen_hpd_init,
2571 .fini = &evergreen_hpd_fini,
2572 .sense = &evergreen_hpd_sense,
2573 .set_polarity = &evergreen_hpd_set_polarity,
2576 .misc = &evergreen_pm_misc,
2577 .prepare = &evergreen_pm_prepare,
2578 .finish = &evergreen_pm_finish,
2579 .init_profile = &sumo_pm_init_profile,
2580 .get_dynpm_state = &r600_pm_get_dynpm_state,
2581 .get_engine_clock = &radeon_atom_get_engine_clock,
2582 .set_engine_clock = &radeon_atom_set_engine_clock,
2583 .get_memory_clock = &radeon_atom_get_memory_clock,
2584 .set_memory_clock = &radeon_atom_set_memory_clock,
2585 .get_pcie_lanes = NULL,
2586 .set_pcie_lanes = NULL,
2587 .set_clock_gating = NULL,
2588 .set_uvd_clocks = &cik_set_uvd_clocks,
2591 .pre_page_flip = &evergreen_pre_page_flip,
2592 .page_flip = &evergreen_page_flip,
2593 .post_page_flip = &evergreen_post_page_flip,
2598 * radeon_asic_init - register asic specific callbacks
2600 * @rdev: radeon device pointer
2602 * Registers the appropriate asic specific callbacks for each
2603 * chip family. Also sets other asics specific info like the number
2604 * of crtcs and the register aperture accessors (all asics).
2605 * Returns 0 for success.
2607 int radeon_asic_init(struct radeon_device *rdev)
2609 radeon_register_accessor_init(rdev);
2611 /* set the number of crtcs */
2612 if (rdev->flags & RADEON_SINGLE_CRTC)
2617 rdev->has_uvd = false;
2619 switch (rdev->family) {
2625 rdev->asic = &r100_asic;
2631 rdev->asic = &r200_asic;
2637 if (rdev->flags & RADEON_IS_PCIE)
2638 rdev->asic = &r300_asic_pcie;
2640 rdev->asic = &r300_asic;
2645 rdev->asic = &r420_asic;
2647 if (rdev->bios == NULL) {
2648 rdev->asic->pm.get_engine_clock = &radeon_legacy_get_engine_clock;
2649 rdev->asic->pm.set_engine_clock = &radeon_legacy_set_engine_clock;
2650 rdev->asic->pm.get_memory_clock = &radeon_legacy_get_memory_clock;
2651 rdev->asic->pm.set_memory_clock = NULL;
2652 rdev->asic->display.set_backlight_level = &radeon_legacy_set_backlight_level;
2657 rdev->asic = &rs400_asic;
2660 rdev->asic = &rs600_asic;
2664 rdev->asic = &rs690_asic;
2667 rdev->asic = &rv515_asic;
2674 rdev->asic = &r520_asic;
2677 rdev->asic = &r600_asic;
2684 rdev->asic = &rv6xx_asic;
2685 rdev->has_uvd = true;
2689 rdev->asic = &rs780_asic;
2690 rdev->has_uvd = true;
2696 rdev->asic = &rv770_asic;
2697 rdev->has_uvd = true;
2705 if (rdev->family == CHIP_CEDAR)
2709 rdev->asic = &evergreen_asic;
2710 rdev->has_uvd = true;
2715 rdev->asic = &sumo_asic;
2716 rdev->has_uvd = true;
2722 if (rdev->family == CHIP_CAICOS)
2726 rdev->asic = &btc_asic;
2727 rdev->has_uvd = true;
2730 rdev->asic = &cayman_asic;
2733 rdev->has_uvd = true;
2736 rdev->asic = &trinity_asic;
2739 rdev->has_uvd = true;
2746 rdev->asic = &si_asic;
2748 if (rdev->family == CHIP_HAINAN)
2750 else if (rdev->family == CHIP_OLAND)
2754 if (rdev->family == CHIP_HAINAN)
2755 rdev->has_uvd = false;
2757 rdev->has_uvd = true;
2760 rdev->asic = &ci_asic;
2765 rdev->asic = &kv_asic;
2767 if (rdev->family == CHIP_KAVERI)
2773 /* FIXME: not supported yet */
2777 if (rdev->flags & RADEON_IS_IGP) {
2778 rdev->asic->pm.get_memory_clock = NULL;
2779 rdev->asic->pm.set_memory_clock = NULL;