arch/ia64/kernel/iosapic.c

   1 /*
   2  * I/O SAPIC support.
   3  *
   4  * Copyright (C) 1999 Intel Corp.
   5  * Copyright (C) 1999 Asit Mallick <asit.k.mallick@intel.com>
   6  * Copyright (C) 2000-2002 J.I. Lee <jung-ik.lee@intel.com>
   7  * Copyright (C) 1999-2000, 2002-2003 Hewlett-Packard Co.
   8  *      David Mosberger-Tang <davidm@hpl.hp.com>
   9  * Copyright (C) 1999 VA Linux Systems
  10  * Copyright (C) 1999,2000 Walt Drummond <drummond@valinux.com>
  11  *
  12  * 00/04/19     D. Mosberger    Rewritten to mirror more closely the x86 I/O
  13  *                              APIC code.  In particular, we now have separate
  14  *                              handlers for edge and level triggered
  15  *                              interrupts.
  16  * 00/10/27     Asit Mallick, Goutham Rao <goutham.rao@intel.com> IRQ vector
  17  *                              allocation PCI to vector mapping, shared PCI
  18  *                              interrupts.
  19  * 00/10/27     D. Mosberger    Document things a bit more to make them more
  20  *                              understandable.  Clean up much of the old
  21  *                              IOSAPIC cruft.
  22  * 01/07/27     J.I. Lee        PCI irq routing, Platform/Legacy interrupts
  23  *                              and fixes for ACPI S5(SoftOff) support.
  24  * 02/01/23     J.I. Lee        iosapic pgm fixes for PCI irq routing from _PRT
  25  * 02/01/07     E. Focht        <efocht@ess.nec.de> Redirectable interrupt
  26  *                              vectors in iosapic_set_affinity(),
  27  *                              initializations for /proc/irq/#/smp_affinity
  28  * 02/04/02     P. Diefenbaugh  Cleaned up ACPI PCI IRQ routing.
  29  * 02/04/18     J.I. Lee        bug fix in iosapic_init_pci_irq
  30  * 02/04/30     J.I. Lee        bug fix in find_iosapic to fix ACPI PCI IRQ to
  31  *                              IOSAPIC mapping error
  32  * 02/07/29     T. Kochi        Allocate interrupt vectors dynamically
  33  * 02/08/04     T. Kochi        Cleaned up terminology (irq, global system
  34  *                              interrupt, vector, etc.)
  35  * 02/09/20     D. Mosberger    Simplified by taking advantage of ACPI's
  36  *                              pci_irq code.
  37  * 03/02/19     B. Helgaas      Make pcat_compat system-wide, not per-IOSAPIC.
  38  *                              Remove iosapic_address & gsi_base from
  39  *                              external interfaces.  Rationalize
  40  *                              __init/__devinit attributes.
  41  * 04/12/04 Ashok Raj   <ashok.raj@intel.com> Intel Corporation 2004
  42  *                              Updated to work with irq migration necessary
  43  *                              for CPU Hotplug
  44  */
  45 /*
  46  * Here is what the interrupt logic between a PCI device and the kernel looks
  47  * like:
  48  *
  49  * (1) A PCI device raises one of the four interrupt pins (INTA, INTB, INTC,
  50  *     INTD).  The device is uniquely identified by its bus-, and slot-number
  51  *     (the function number does not matter here because all functions share
  52  *     the same interrupt lines).
  53  *
  54  * (2) The motherboard routes the interrupt line to a pin on a IOSAPIC
  55  *     controller.  Multiple interrupt lines may have to share the same
  56  *     IOSAPIC pin (if they're level triggered and use the same polarity).
  57  *     Each interrupt line has a unique Global System Interrupt (GSI) number
  58  *     which can be calculated as the sum of the controller's base GSI number
  59  *     and the IOSAPIC pin number to which the line connects.
  60  *
  61  * (3) The IOSAPIC uses an internal routing table entries (RTEs) to map the
  62  * IOSAPIC pin into the IA-64 interrupt vector.  This interrupt vector is then
  63  * sent to the CPU.
  64  *
  65  * (4) The kernel recognizes an interrupt as an IRQ.  The IRQ interface is
  66  *     used as architecture-independent interrupt handling mechanism in Linux.
  67  *     As an IRQ is a number, we have to have
  68  *     IA-64 interrupt vector number <-> IRQ number mapping.  On smaller
  69  *     systems, we use one-to-one mapping between IA-64 vector and IRQ.  A
  70  *     platform can implement platform_irq_to_vector(irq) and
  71  *     platform_local_vector_to_irq(vector) APIs to differentiate the mapping.
  72  *     Please see also include/asm-ia64/hw_irq.h for those APIs.
  73  *
  74  * To sum up, there are three levels of mappings involved:
  75  *
  76  *      PCI pin -> global system interrupt (GSI) -> IA-64 vector <-> IRQ
  77  *
  78  * Note: The term "IRQ" is loosely used everywhere in Linux kernel to
  79  * describeinterrupts.  Now we use "IRQ" only for Linux IRQ's.  ISA IRQ
  80  * (isa_irq) is the only exception in this source code.
  81  */
  82
  83 #include <linux/acpi.h>
  84 #include <linux/init.h>
  85 #include <linux/irq.h>
  86 #include <linux/kernel.h>
  87 #include <linux/list.h>
  88 #include <linux/pci.h>
  89 #include <linux/smp.h>
  90 #include <linux/string.h>
  91 #include <linux/bootmem.h>
  92
  93 #include <asm/delay.h>
  94 #include <asm/hw_irq.h>
  95 #include <asm/io.h>
  96 #include <asm/iosapic.h>
  97 #include <asm/machvec.h>
  98 #include <asm/processor.h>
  99 #include <asm/ptrace.h>
 100 #include <asm/system.h>
 101
 102 #undef DEBUG_INTERRUPT_ROUTING
 103
 104 #ifdef DEBUG_INTERRUPT_ROUTING
 105 #define DBG(fmt...)     printk(fmt)
 106 #else
 107 #define DBG(fmt...)
 108 #endif
 109
 110 #define NR_PREALLOCATE_RTE_ENTRIES \
 111         (PAGE_SIZE / sizeof(struct iosapic_rte_info))
 112 #define RTE_PREALLOCATED        (1)
 113
 114 static DEFINE_SPINLOCK(iosapic_lock);
 115
 116 /*
 117  * These tables map IA-64 vectors to the IOSAPIC pin that generates this
 118  * vector.
 119  */
 120 static struct iosapic {
 121         char __iomem    *addr;          /* base address of IOSAPIC */
 122         unsigned int    gsi_base;       /* GSI base */
 123         unsigned short  num_rte;        /* # of RTEs on this IOSAPIC */
 124         int             rtes_inuse;     /* # of RTEs in use on this IOSAPIC */
 125 #ifdef CONFIG_NUMA
 126         unsigned short  node;           /* numa node association via pxm */
 127 #endif
 128 } iosapic_lists[NR_IOSAPICS];
 129
 130 struct iosapic_rte_info {
 131         struct list_head rte_list;      /* RTEs sharing the same vector */
 132         char            rte_index;      /* IOSAPIC RTE index */
 133         int             refcnt;         /* reference counter */
 134         unsigned int    flags;          /* flags */
 135         struct iosapic  *iosapic;
 136 } ____cacheline_aligned;
 137
 138 static struct iosapic_intr_info {
 139         struct list_head rtes;          /* RTEs using this vector (empty =>
 140                                          * not an IOSAPIC interrupt) */
 141         int             count;          /* # of RTEs that shares this vector */
 142         u32             low32;          /* current value of low word of
 143                                          * Redirection table entry */
 144         unsigned int    dest;           /* destination CPU physical ID */
 145         unsigned char   dmode   : 3;    /* delivery mode (see iosapic.h) */
 146         unsigned char   polarity: 1;    /* interrupt polarity
 147                                          * (see iosapic.h) */
 148         unsigned char   trigger : 1;    /* trigger mode (see iosapic.h) */
 149 } iosapic_intr_info[IA64_NUM_VECTORS];
 150
 151 static unsigned char pcat_compat __devinitdata; /* 8259 compatibility flag */
 152
 153 static int iosapic_kmalloc_ok;
 154 static LIST_HEAD(free_rte_list);
 155
 156 /*
 157  * Find an IOSAPIC associated with a GSI
 158  */
 159 static inline int
 160 find_iosapic (unsigned int gsi)
 161 {
 162         int i;
 163
 164         for (i = 0; i < NR_IOSAPICS; i++) {
 165                 if ((unsigned) (gsi - iosapic_lists[i].gsi_base) <
 166                     iosapic_lists[i].num_rte)
 167                         return i;
 168         }
 169
 170         return -1;
 171 }
 172
 173 static inline int
 174 _gsi_to_vector (unsigned int gsi)
 175 {
 176         struct iosapic_intr_info *info;
 177         struct iosapic_rte_info *rte;
 178
 179         for (info = iosapic_intr_info; info <
 180                      iosapic_intr_info + IA64_NUM_VECTORS; ++info)
 181                 list_for_each_entry(rte, &info->rtes, rte_list)
 182                         if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 183                                 return info - iosapic_intr_info;
 184         return -1;
 185 }
 186
 187 /*
 188  * Translate GSI number to the corresponding IA-64 interrupt vector.  If no
 189  * entry exists, return -1.
 190  */
 191 inline int
 192 gsi_to_vector (unsigned int gsi)
 193 {
 194         return _gsi_to_vector(gsi);
 195 }
 196
 197 int
 198 gsi_to_irq (unsigned int gsi)
 199 {
 200         unsigned long flags;
 201         int irq;
 202         /*
 203          * XXX fix me: this assumes an identity mapping between IA-64 vector
 204          * and Linux irq numbers...
 205          */
 206         spin_lock_irqsave(&iosapic_lock, flags);
 207         irq = _gsi_to_vector(gsi);
 208         spin_unlock_irqrestore(&iosapic_lock, flags);
 209
 210         return irq;
 211 }
 212
 213 static struct iosapic_rte_info *gsi_vector_to_rte(unsigned int gsi,
 214                                                   unsigned int vec)
 215 {
 216         struct iosapic_rte_info *rte;
 217
 218         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 219                 if (rte->iosapic->gsi_base + rte->rte_index == gsi)
 220                         return rte;
 221         return NULL;
 222 }
 223
 224 static void
 225 set_rte (unsigned int gsi, unsigned int vector, unsigned int dest, int mask)
 226 {
 227         unsigned long pol, trigger, dmode;
 228         u32 low32, high32;
 229         char __iomem *addr;
 230         int rte_index;
 231         char redir;
 232         struct iosapic_rte_info *rte;
 233
 234         DBG(KERN_DEBUG"IOSAPIC: routing vector %d to 0x%x\n", vector, dest);
 235
 236         rte = gsi_vector_to_rte(gsi, vector);
 237         if (!rte)
 238                 return;         /* not an IOSAPIC interrupt */
 239
 240         rte_index = rte->rte_index;
 241         addr    = rte->iosapic->addr;
 242         pol     = iosapic_intr_info[vector].polarity;
 243         trigger = iosapic_intr_info[vector].trigger;
 244         dmode   = iosapic_intr_info[vector].dmode;
 245
 246         redir = (dmode == IOSAPIC_LOWEST_PRIORITY) ? 1 : 0;
 247
 248 #ifdef CONFIG_SMP
 249         {
 250                 unsigned int irq;
 251
 252                 for (irq = 0; irq < NR_IRQS; ++irq)
 253                         if (irq_to_vector(irq) == vector) {
 254                                 set_irq_affinity_info(irq,
 255                                                       (int)(dest & 0xffff),
 256                                                       redir);
 257                                 break;
 258                         }
 259         }
 260 #endif
 261
 262         low32 = ((pol << IOSAPIC_POLARITY_SHIFT) |
 263                  (trigger << IOSAPIC_TRIGGER_SHIFT) |
 264                  (dmode << IOSAPIC_DELIVERY_SHIFT) |
 265                  ((mask ? 1 : 0) << IOSAPIC_MASK_SHIFT) |
 266                  vector);
 267
 268         /* dest contains both id and eid */
 269         high32 = (dest << IOSAPIC_DEST_SHIFT);
 270
 271         iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 272         iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 273         iosapic_intr_info[vector].low32 = low32;
 274         iosapic_intr_info[vector].dest = dest;
 275 }
 276
 277 static void
 278 nop (unsigned int irq)
 279 {
 280         /* do nothing... */
 281 }
 282
 283
 284 #ifdef CONFIG_KEXEC
 285 void
 286 kexec_disable_iosapic(void)
 287 {
 288         struct iosapic_intr_info *info;
 289         struct iosapic_rte_info *rte;
 290         u8 vec = 0;
 291         for (info = iosapic_intr_info; info <
 292                         iosapic_intr_info + IA64_NUM_VECTORS; ++info, ++vec) {
 293                 list_for_each_entry(rte, &info->rtes,
 294                                 rte_list) {
 295                         iosapic_write(rte->iosapic->addr,
 296                                         IOSAPIC_RTE_LOW(rte->rte_index),
 297                                         IOSAPIC_MASK|vec);
 298                         iosapic_eoi(rte->iosapic->addr, vec);
 299                 }
 300         }
 301 }
 302 #endif
 303
 304 static void
 305 mask_irq (unsigned int irq)
 306 {
 307         unsigned long flags;
 308         char __iomem *addr;
 309         u32 low32;
 310         int rte_index;
 311         ia64_vector vec = irq_to_vector(irq);
 312         struct iosapic_rte_info *rte;
 313
 314         if (list_empty(&iosapic_intr_info[vec].rtes))
 315                 return;                 /* not an IOSAPIC interrupt! */
 316
 317         spin_lock_irqsave(&iosapic_lock, flags);
 318         /* set only the mask bit */
 319         low32 = iosapic_intr_info[vec].low32 |= IOSAPIC_MASK;
 320         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 321                 addr = rte->iosapic->addr;
 322                 rte_index = rte->rte_index;
 323                 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 324         }
 325         spin_unlock_irqrestore(&iosapic_lock, flags);
 326 }
 327
 328 static void
 329 unmask_irq (unsigned int irq)
 330 {
 331         unsigned long flags;
 332         char __iomem *addr;
 333         u32 low32;
 334         int rte_index;
 335         ia64_vector vec = irq_to_vector(irq);
 336         struct iosapic_rte_info *rte;
 337
 338         if (list_empty(&iosapic_intr_info[vec].rtes))
 339                 return;                 /* not an IOSAPIC interrupt! */
 340
 341         spin_lock_irqsave(&iosapic_lock, flags);
 342         low32 = iosapic_intr_info[vec].low32 &= ~IOSAPIC_MASK;
 343         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 344                 addr = rte->iosapic->addr;
 345                 rte_index = rte->rte_index;
 346                 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 347         }
 348         spin_unlock_irqrestore(&iosapic_lock, flags);
 349 }
 350
 351
 352 static void
 353 iosapic_set_affinity (unsigned int irq, cpumask_t mask)
 354 {
 355 #ifdef CONFIG_SMP
 356         unsigned long flags;
 357         u32 high32, low32;
 358         int dest, rte_index;
 359         char __iomem *addr;
 360         int redir = (irq & IA64_IRQ_REDIRECTED) ? 1 : 0;
 361         ia64_vector vec;
 362         struct iosapic_rte_info *rte;
 363
 364         irq &= (~IA64_IRQ_REDIRECTED);
 365         vec = irq_to_vector(irq);
 366
 367         if (cpus_empty(mask))
 368                 return;
 369
 370         dest = cpu_physical_id(first_cpu(mask));
 371
 372         if (list_empty(&iosapic_intr_info[vec].rtes))
 373                 return;                 /* not an IOSAPIC interrupt */
 374
 375         set_irq_affinity_info(irq, dest, redir);
 376
 377         /* dest contains both id and eid */
 378         high32 = dest << IOSAPIC_DEST_SHIFT;
 379
 380         spin_lock_irqsave(&iosapic_lock, flags);
 381         low32 = iosapic_intr_info[vec].low32 & ~(7 << IOSAPIC_DELIVERY_SHIFT);
 382         if (redir)
 383                 /* change delivery mode to lowest priority */
 384                 low32 |= (IOSAPIC_LOWEST_PRIORITY << IOSAPIC_DELIVERY_SHIFT);
 385         else
 386                 /* change delivery mode to fixed */
 387                 low32 |= (IOSAPIC_FIXED << IOSAPIC_DELIVERY_SHIFT);
 388
 389         iosapic_intr_info[vec].low32 = low32;
 390         iosapic_intr_info[vec].dest = dest;
 391         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list) {
 392                 addr = rte->iosapic->addr;
 393                 rte_index = rte->rte_index;
 394                 iosapic_write(addr, IOSAPIC_RTE_HIGH(rte_index), high32);
 395                 iosapic_write(addr, IOSAPIC_RTE_LOW(rte_index), low32);
 396         }
 397         spin_unlock_irqrestore(&iosapic_lock, flags);
 398 #endif
 399 }
 400
 401 /*
 402  * Handlers for level-triggered interrupts.
 403  */
 404
 405 static unsigned int
 406 iosapic_startup_level_irq (unsigned int irq)
 407 {
 408         unmask_irq(irq);
 409         return 0;
 410 }
 411
 412 static void
 413 iosapic_end_level_irq (unsigned int irq)
 414 {
 415         ia64_vector vec = irq_to_vector(irq);
 416         struct iosapic_rte_info *rte;
 417
 418         move_native_irq(irq);
 419         list_for_each_entry(rte, &iosapic_intr_info[vec].rtes, rte_list)
 420                 iosapic_eoi(rte->iosapic->addr, vec);
 421 }
 422
 423 #define iosapic_shutdown_level_irq      mask_irq
 424 #define iosapic_enable_level_irq        unmask_irq
 425 #define iosapic_disable_level_irq       mask_irq
 426 #define iosapic_ack_level_irq           nop
 427
 428 struct irq_chip irq_type_iosapic_level = {
 429         .name =         "IO-SAPIC-level",
 430         .startup =      iosapic_startup_level_irq,
 431         .shutdown =     iosapic_shutdown_level_irq,
 432         .enable =       iosapic_enable_level_irq,
 433         .disable =      iosapic_disable_level_irq,
 434         .ack =          iosapic_ack_level_irq,
 435         .end =          iosapic_end_level_irq,
 436         .mask =         mask_irq,
 437         .unmask =       unmask_irq,
 438         .set_affinity = iosapic_set_affinity
 439 };
 440
 441 /*
 442  * Handlers for edge-triggered interrupts.
 443  */
 444
 445 static unsigned int
 446 iosapic_startup_edge_irq (unsigned int irq)
 447 {
 448         unmask_irq(irq);
 449         /*
 450          * IOSAPIC simply drops interrupts pended while the
 451          * corresponding pin was masked, so we can't know if an
 452          * interrupt is pending already.  Let's hope not...
 453          */
 454         return 0;
 455 }
 456
 457 static void
 458 iosapic_ack_edge_irq (unsigned int irq)
 459 {
 460         irq_desc_t *idesc = irq_desc + irq;
 461
 462         move_native_irq(irq);
 463         /*
 464          * Once we have recorded IRQ_PENDING already, we can mask the
 465          * interrupt for real. This prevents IRQ storms from unhandled
 466          * devices.
 467          */
 468         if ((idesc->status & (IRQ_PENDING|IRQ_DISABLED)) ==
 469             (IRQ_PENDING|IRQ_DISABLED))
 470                 mask_irq(irq);
 471 }
 472
 473 #define iosapic_enable_edge_irq         unmask_irq
 474 #define iosapic_disable_edge_irq        nop
 475 #define iosapic_end_edge_irq            nop
 476
 477 struct irq_chip irq_type_iosapic_edge = {
 478         .name =         "IO-SAPIC-edge",
 479         .startup =      iosapic_startup_edge_irq,
 480         .shutdown =     iosapic_disable_edge_irq,
 481         .enable =       iosapic_enable_edge_irq,
 482         .disable =      iosapic_disable_edge_irq,
 483         .ack =          iosapic_ack_edge_irq,
 484         .end =          iosapic_end_edge_irq,
 485         .mask =         mask_irq,
 486         .unmask =       unmask_irq,
 487         .set_affinity = iosapic_set_affinity
 488 };
 489
 490 unsigned int
 491 iosapic_version (char __iomem *addr)
 492 {
 493         /*
 494          * IOSAPIC Version Register return 32 bit structure like:
 495          * {
 496          *      unsigned int version   : 8;
 497          *      unsigned int reserved1 : 8;
 498          *      unsigned int max_redir : 8;
 499          *      unsigned int reserved2 : 8;
 500          * }
 501          */
 502         return iosapic_read(addr, IOSAPIC_VERSION);
 503 }
 504
 505 static int iosapic_find_sharable_vector (unsigned long trigger,
 506                                          unsigned long pol)
 507 {
 508         int i, vector = -1, min_count = -1;
 509         struct iosapic_intr_info *info;
 510
 511         /*
 512          * shared vectors for edge-triggered interrupts are not
 513          * supported yet
 514          */
 515         if (trigger == IOSAPIC_EDGE)
 516                 return -1;
 517
 518         for (i = IA64_FIRST_DEVICE_VECTOR; i <= IA64_LAST_DEVICE_VECTOR; i++) {
 519                 info = &iosapic_intr_info[i];
 520                 if (info->trigger == trigger && info->polarity == pol &&
 521                     (info->dmode == IOSAPIC_FIXED || info->dmode ==
 522                      IOSAPIC_LOWEST_PRIORITY)) {
 523                         if (min_count == -1 || info->count < min_count) {
 524                                 vector = i;
 525                                 min_count = info->count;
 526                         }
 527                 }
 528         }
 529
 530         return vector;
 531 }
 532
 533 /*
 534  * if the given vector is already owned by other,
 535  *  assign a new vector for the other and make the vector available
 536  */
 537 static void __init
 538 iosapic_reassign_vector (int vector)
 539 {
 540         int new_vector;
 541
 542         if (!list_empty(&iosapic_intr_info[vector].rtes)) {
 543                 new_vector = assign_irq_vector(AUTO_ASSIGN);
 544                 if (new_vector < 0)
 545                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 546                 printk(KERN_INFO "Reassigning vector %d to %d\n",
 547                        vector, new_vector);
 548                 memcpy(&iosapic_intr_info[new_vector], &iosapic_intr_info[vector],
 549                        sizeof(struct iosapic_intr_info));
 550                 INIT_LIST_HEAD(&iosapic_intr_info[new_vector].rtes);
 551                 list_move(iosapic_intr_info[vector].rtes.next,
 552                           &iosapic_intr_info[new_vector].rtes);
 553                 memset(&iosapic_intr_info[vector], 0,
 554                        sizeof(struct iosapic_intr_info));
 555                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
 556                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 557         }
 558 }
 559
 560 static struct iosapic_rte_info *iosapic_alloc_rte (void)
 561 {
 562         int i;
 563         struct iosapic_rte_info *rte;
 564         int preallocated = 0;
 565
 566         if (!iosapic_kmalloc_ok && list_empty(&free_rte_list)) {
 567                 rte = alloc_bootmem(sizeof(struct iosapic_rte_info) *
 568                                     NR_PREALLOCATE_RTE_ENTRIES);
 569                 if (!rte)
 570                         return NULL;
 571                 for (i = 0; i < NR_PREALLOCATE_RTE_ENTRIES; i++, rte++)
 572                         list_add(&rte->rte_list, &free_rte_list);
 573         }
 574
 575         if (!list_empty(&free_rte_list)) {
 576                 rte = list_entry(free_rte_list.next, struct iosapic_rte_info,
 577                                  rte_list);
 578                 list_del(&rte->rte_list);
 579                 preallocated++;
 580         } else {
 581                 rte = kmalloc(sizeof(struct iosapic_rte_info), GFP_ATOMIC);
 582                 if (!rte)
 583                         return NULL;
 584         }
 585
 586         memset(rte, 0, sizeof(struct iosapic_rte_info));
 587         if (preallocated)
 588                 rte->flags |= RTE_PREALLOCATED;
 589
 590         return rte;
 591 }
 592
 593 static void iosapic_free_rte (struct iosapic_rte_info *rte)
 594 {
 595         if (rte->flags & RTE_PREALLOCATED)
 596                 list_add_tail(&rte->rte_list, &free_rte_list);
 597         else
 598                 kfree(rte);
 599 }
 600
 601 static inline int vector_is_shared (int vector)
 602 {
 603         return (iosapic_intr_info[vector].count > 1);
 604 }
 605
 606 static int
 607 register_intr (unsigned int gsi, int vector, unsigned char delivery,
 608                unsigned long polarity, unsigned long trigger)
 609 {
 610         irq_desc_t *idesc;
 611         struct hw_interrupt_type *irq_type;
 612         int index;
 613         struct iosapic_rte_info *rte;
 614
 615         index = find_iosapic(gsi);
 616         if (index < 0) {
 617                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
 618                        __FUNCTION__, gsi);
 619                 return -ENODEV;
 620         }
 621
 622         rte = gsi_vector_to_rte(gsi, vector);
 623         if (!rte) {
 624                 rte = iosapic_alloc_rte();
 625                 if (!rte) {
 626                         printk(KERN_WARNING "%s: cannot allocate memory\n",
 627                                __FUNCTION__);
 628                         return -ENOMEM;
 629                 }
 630
 631                 rte->iosapic    = &iosapic_lists[index];
 632                 rte->rte_index  = gsi - rte->iosapic->gsi_base;
 633                 rte->refcnt++;
 634                 list_add_tail(&rte->rte_list, &iosapic_intr_info[vector].rtes);
 635                 iosapic_intr_info[vector].count++;
 636                 iosapic_lists[index].rtes_inuse++;
 637         }
 638         else if (vector_is_shared(vector)) {
 639                 struct iosapic_intr_info *info = &iosapic_intr_info[vector];
 640                 if (info->trigger != trigger || info->polarity != polarity) {
 641                         printk (KERN_WARNING
 642                                 "%s: cannot override the interrupt\n",
 643                                 __FUNCTION__);
 644                         return -EINVAL;
 645                 }
 646         }
 647
 648         iosapic_intr_info[vector].polarity = polarity;
 649         iosapic_intr_info[vector].dmode    = delivery;
 650         iosapic_intr_info[vector].trigger  = trigger;
 651
 652         if (trigger == IOSAPIC_EDGE)
 653                 irq_type = &irq_type_iosapic_edge;
 654         else
 655                 irq_type = &irq_type_iosapic_level;
 656
 657         idesc = irq_desc + vector;
 658         if (idesc->chip != irq_type) {
 659                 if (idesc->chip != &no_irq_type)
 660                         printk(KERN_WARNING
 661                                "%s: changing vector %d from %s to %s\n",
 662                                __FUNCTION__, vector,
 663                                idesc->chip->name, irq_type->name);
 664                 idesc->chip = irq_type;
 665         }
 666         return 0;
 667 }
 668
 669 static unsigned int
 670 get_target_cpu (unsigned int gsi, int vector)
 671 {
 672 #ifdef CONFIG_SMP
 673         static int cpu = -1;
 674         extern int cpe_vector;
 675
 676         /*
 677          * In case of vector shared by multiple RTEs, all RTEs that
 678          * share the vector need to use the same destination CPU.
 679          */
 680         if (!list_empty(&iosapic_intr_info[vector].rtes))
 681                 return iosapic_intr_info[vector].dest;
 682
 683         /*
 684          * If the platform supports redirection via XTP, let it
 685          * distribute interrupts.
 686          */
 687         if (smp_int_redirect & SMP_IRQ_REDIRECTION)
 688                 return cpu_physical_id(smp_processor_id());
 689
 690         /*
 691          * Some interrupts (ACPI SCI, for instance) are registered
 692          * before the BSP is marked as online.
 693          */
 694         if (!cpu_online(smp_processor_id()))
 695                 return cpu_physical_id(smp_processor_id());
 696
 697 #ifdef CONFIG_ACPI
 698         if (cpe_vector > 0 && vector == IA64_CPEP_VECTOR)
 699                 return get_cpei_target_cpu();
 700 #endif
 701
 702 #ifdef CONFIG_NUMA
 703         {
 704                 int num_cpus, cpu_index, iosapic_index, numa_cpu, i = 0;
 705                 cpumask_t cpu_mask;
 706
 707                 iosapic_index = find_iosapic(gsi);
 708                 if (iosapic_index < 0 ||
 709                     iosapic_lists[iosapic_index].node == MAX_NUMNODES)
 710                         goto skip_numa_setup;
 711
 712                 cpu_mask = node_to_cpumask(iosapic_lists[iosapic_index].node);
 713
 714                 for_each_cpu_mask(numa_cpu, cpu_mask) {
 715                         if (!cpu_online(numa_cpu))
 716                                 cpu_clear(numa_cpu, cpu_mask);
 717                 }
 718
 719                 num_cpus = cpus_weight(cpu_mask);
 720
 721                 if (!num_cpus)
 722                         goto skip_numa_setup;
 723
 724                 /* Use vector assignment to distribute across cpus in node */
 725                 cpu_index = vector % num_cpus;
 726
 727                 for (numa_cpu = first_cpu(cpu_mask) ; i < cpu_index ; i++)
 728                         numa_cpu = next_cpu(numa_cpu, cpu_mask);
 729
 730                 if (numa_cpu != NR_CPUS)
 731                         return cpu_physical_id(numa_cpu);
 732         }
 733 skip_numa_setup:
 734 #endif
 735         /*
 736          * Otherwise, round-robin interrupt vectors across all the
 737          * processors.  (It'd be nice if we could be smarter in the
 738          * case of NUMA.)
 739          */
 740         do {
 741                 if (++cpu >= NR_CPUS)
 742                         cpu = 0;
 743         } while (!cpu_online(cpu));
 744
 745         return cpu_physical_id(cpu);
 746 #else  /* CONFIG_SMP */
 747         return cpu_physical_id(smp_processor_id());
 748 #endif
 749 }
 750
 751 /*
 752  * ACPI can describe IOSAPIC interrupts via static tables and namespace
 753  * methods.  This provides an interface to register those interrupts and
 754  * program the IOSAPIC RTE.
 755  */
 756 int
 757 iosapic_register_intr (unsigned int gsi,
 758                        unsigned long polarity, unsigned long trigger)
 759 {
 760         int vector, mask = 1, err;
 761         unsigned int dest;
 762         unsigned long flags;
 763         struct iosapic_rte_info *rte;
 764         u32 low32;
 765 again:
 766         /*
 767          * If this GSI has already been registered (i.e., it's a
 768          * shared interrupt, or we lost a race to register it),
 769          * don't touch the RTE.
 770          */
 771         spin_lock_irqsave(&iosapic_lock, flags);
 772         vector = gsi_to_vector(gsi);
 773         if (vector > 0) {
 774                 rte = gsi_vector_to_rte(gsi, vector);
 775                 rte->refcnt++;
 776                 spin_unlock_irqrestore(&iosapic_lock, flags);
 777                 return vector;
 778         }
 779         spin_unlock_irqrestore(&iosapic_lock, flags);
 780
 781         /* If vector is running out, we try to find a sharable vector */
 782         vector = assign_irq_vector(AUTO_ASSIGN);
 783         if (vector < 0) {
 784                 vector = iosapic_find_sharable_vector(trigger, polarity);
 785                 if (vector < 0)
 786                         return -ENOSPC;
 787         }
 788
 789         spin_lock_irqsave(&irq_desc[vector].lock, flags);
 790         spin_lock(&iosapic_lock);
 791         if (gsi_to_vector(gsi) > 0) {
 792                 if (list_empty(&iosapic_intr_info[vector].rtes))
 793                         free_irq_vector(vector);
 794                 spin_unlock(&iosapic_lock);
 795                 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
 796                 goto again;
 797         }
 798
 799         dest = get_target_cpu(gsi, vector);
 800         err = register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY,
 801                             polarity, trigger);
 802         if (err < 0) {
 803                 spin_unlock(&iosapic_lock);
 804                 spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
 805                 return err;
 806         }
 807
 808         /*
 809          * If the vector is shared and already unmasked for other
 810          * interrupt sources, don't mask it.
 811          */
 812         low32 = iosapic_intr_info[vector].low32;
 813         if (vector_is_shared(vector) && !(low32 & IOSAPIC_MASK))
 814                 mask = 0;
 815         set_rte(gsi, vector, dest, mask);
 816         spin_unlock(&iosapic_lock);
 817         spin_unlock_irqrestore(&irq_desc[vector].lock, flags);
 818
 819         printk(KERN_INFO "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d\n",
 820                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 821                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 822                cpu_logical_id(dest), dest, vector);
 823
 824         return vector;
 825 }
 826
 827 void
 828 iosapic_unregister_intr (unsigned int gsi)
 829 {
 830         unsigned long flags;
 831         int irq, vector, index;
 832         irq_desc_t *idesc;
 833         u32 low32;
 834         unsigned long trigger, polarity;
 835         unsigned int dest;
 836         struct iosapic_rte_info *rte;
 837
 838         /*
 839          * If the irq associated with the gsi is not found,
 840          * iosapic_unregister_intr() is unbalanced. We need to check
 841          * this again after getting locks.
 842          */
 843         irq = gsi_to_irq(gsi);
 844         if (irq < 0) {
 845                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 846                        gsi);
 847                 WARN_ON(1);
 848                 return;
 849         }
 850         vector = irq_to_vector(irq);
 851
 852         idesc = irq_desc + irq;
 853         spin_lock_irqsave(&idesc->lock, flags);
 854         spin_lock(&iosapic_lock);
 855         if ((rte = gsi_vector_to_rte(gsi, vector)) == NULL) {
 856                 printk(KERN_ERR "iosapic_unregister_intr(%u) unbalanced\n",
 857                        gsi);
 858                 WARN_ON(1);
 859                 goto out;
 860         }
 861
 862         if (--rte->refcnt > 0)
 863                 goto out;
 864
 865         /* Mask the interrupt */
 866         low32 = iosapic_intr_info[vector].low32 | IOSAPIC_MASK;
 867         iosapic_write(rte->iosapic->addr,
 868                       IOSAPIC_RTE_LOW(rte->rte_index), low32);
 869
 870         /* Remove the rte entry from the list */
 871         list_del(&rte->rte_list);
 872         iosapic_intr_info[vector].count--;
 873         iosapic_free_rte(rte);
 874         index = find_iosapic(gsi);
 875         iosapic_lists[index].rtes_inuse--;
 876         WARN_ON(iosapic_lists[index].rtes_inuse < 0);
 877
 878         trigger  = iosapic_intr_info[vector].trigger;
 879         polarity = iosapic_intr_info[vector].polarity;
 880         dest     = iosapic_intr_info[vector].dest;
 881         printk(KERN_INFO
 882                "GSI %u (%s, %s) -> CPU %d (0x%04x) vector %d unregistered\n",
 883                gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 884                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 885                cpu_logical_id(dest), dest, vector);
 886
 887         if (list_empty(&iosapic_intr_info[vector].rtes)) {
 888                 /* Sanity check */
 889                 BUG_ON(iosapic_intr_info[vector].count);
 890
 891                 /* Clear the interrupt controller descriptor */
 892                 idesc->chip = &no_irq_type;
 893
 894 #ifdef CONFIG_SMP
 895                 /* Clear affinity */
 896                 cpus_setall(idesc->affinity);
 897 #endif
 898
 899                 /* Clear the interrupt information */
 900                 memset(&iosapic_intr_info[vector], 0,
 901                        sizeof(struct iosapic_intr_info));
 902                 iosapic_intr_info[vector].low32 |= IOSAPIC_MASK;
 903                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
 904
 905                 if (idesc->action) {
 906                         printk(KERN_ERR
 907                                "interrupt handlers still exist on IRQ %u\n",
 908                                irq);
 909                         WARN_ON(1);
 910                 }
 911
 912                 /* Free the interrupt vector */
 913                 free_irq_vector(vector);
 914         }
 915  out:
 916         spin_unlock(&iosapic_lock);
 917         spin_unlock_irqrestore(&idesc->lock, flags);
 918 }
 919
 920 /*
 921  * ACPI calls this when it finds an entry for a platform interrupt.
 922  */
 923 int __init
 924 iosapic_register_platform_intr (u32 int_type, unsigned int gsi,
 925                                 int iosapic_vector, u16 eid, u16 id,
 926                                 unsigned long polarity, unsigned long trigger)
 927 {
 928         static const char * const name[] = {"unknown", "PMI", "INIT", "CPEI"};
 929         unsigned char delivery;
 930         int vector, mask = 0;
 931         unsigned int dest = ((id << 8) | eid) & 0xffff;
 932
 933         switch (int_type) {
 934               case ACPI_INTERRUPT_PMI:
 935                 vector = iosapic_vector;
 936                 /*
 937                  * since PMI vector is alloc'd by FW(ACPI) not by kernel,
 938                  * we need to make sure the vector is available
 939                  */
 940                 iosapic_reassign_vector(vector);
 941                 delivery = IOSAPIC_PMI;
 942                 break;
 943               case ACPI_INTERRUPT_INIT:
 944                 vector = assign_irq_vector(AUTO_ASSIGN);
 945                 if (vector < 0)
 946                         panic("%s: out of interrupt vectors!\n", __FUNCTION__);
 947                 delivery = IOSAPIC_INIT;
 948                 break;
 949               case ACPI_INTERRUPT_CPEI:
 950                 vector = IA64_CPE_VECTOR;
 951                 delivery = IOSAPIC_LOWEST_PRIORITY;
 952                 mask = 1;
 953                 break;
 954               default:
 955                 printk(KERN_ERR "%s: invalid int type 0x%x\n", __FUNCTION__,
 956                        int_type);
 957                 return -1;
 958         }
 959
 960         register_intr(gsi, vector, delivery, polarity, trigger);
 961
 962         printk(KERN_INFO
 963                "PLATFORM int %s (0x%x): GSI %u (%s, %s) -> CPU %d (0x%04x)"
 964                " vector %d\n",
 965                int_type < ARRAY_SIZE(name) ? name[int_type] : "unknown",
 966                int_type, gsi, (trigger == IOSAPIC_EDGE ? "edge" : "level"),
 967                (polarity == IOSAPIC_POL_HIGH ? "high" : "low"),
 968                cpu_logical_id(dest), dest, vector);
 969
 970         set_rte(gsi, vector, dest, mask);
 971         return vector;
 972 }
 973
 974 /*
 975  * ACPI calls this when it finds an entry for a legacy ISA IRQ override.
 976  */
 977 void __devinit
 978 iosapic_override_isa_irq (unsigned int isa_irq, unsigned int gsi,
 979                           unsigned long polarity,
 980                           unsigned long trigger)
 981 {
 982         int vector;
 983         unsigned int dest = cpu_physical_id(smp_processor_id());
 984
 985         vector = isa_irq_to_vector(isa_irq);
 986
 987         register_intr(gsi, vector, IOSAPIC_LOWEST_PRIORITY, polarity, trigger);
 988
 989         DBG("ISA: IRQ %u -> GSI %u (%s,%s) -> CPU %d (0x%04x) vector %d\n",
 990             isa_irq, gsi, trigger == IOSAPIC_EDGE ? "edge" : "level",
 991             polarity == IOSAPIC_POL_HIGH ? "high" : "low",
 992             cpu_logical_id(dest), dest, vector);
 993
 994         set_rte(gsi, vector, dest, 1);
 995 }
 996
 997 void __init
 998 iosapic_system_init (int system_pcat_compat)
 999 {
1000         int vector;
1001
1002         for (vector = 0; vector < IA64_NUM_VECTORS; ++vector) {
1003                 iosapic_intr_info[vector].low32 = IOSAPIC_MASK;
1004                 /* mark as unused */
1005                 INIT_LIST_HEAD(&iosapic_intr_info[vector].rtes);
1006         }
1007
1008         pcat_compat = system_pcat_compat;
1009         if (pcat_compat) {
1010                 /*
1011                  * Disable the compatibility mode interrupts (8259 style),
1012                  * needs IN/OUT support enabled.
1013                  */
1014                 printk(KERN_INFO
1015                        "%s: Disabling PC-AT compatible 8259 interrupts\n",
1016                        __FUNCTION__);
1017                 outb(0xff, 0xA1);
1018                 outb(0xff, 0x21);
1019         }
1020 }
1021
1022 static inline int
1023 iosapic_alloc (void)
1024 {
1025         int index;
1026
1027         for (index = 0; index < NR_IOSAPICS; index++)
1028                 if (!iosapic_lists[index].addr)
1029                         return index;
1030
1031         printk(KERN_WARNING "%s: failed to allocate iosapic\n", __FUNCTION__);
1032         return -1;
1033 }
1034
1035 static inline void
1036 iosapic_free (int index)
1037 {
1038         memset(&iosapic_lists[index], 0, sizeof(iosapic_lists[0]));
1039 }
1040
1041 static inline int
1042 iosapic_check_gsi_range (unsigned int gsi_base, unsigned int ver)
1043 {
1044         int index;
1045         unsigned int gsi_end, base, end;
1046
1047         /* check gsi range */
1048         gsi_end = gsi_base + ((ver >> 16) & 0xff);
1049         for (index = 0; index < NR_IOSAPICS; index++) {
1050                 if (!iosapic_lists[index].addr)
1051                         continue;
1052
1053                 base = iosapic_lists[index].gsi_base;
1054                 end  = base + iosapic_lists[index].num_rte - 1;
1055
1056                 if (gsi_end < base || end < gsi_base)
1057                         continue; /* OK */
1058
1059                 return -EBUSY;
1060         }
1061         return 0;
1062 }
1063
1064 int __devinit
1065 iosapic_init (unsigned long phys_addr, unsigned int gsi_base)
1066 {
1067         int num_rte, err, index;
1068         unsigned int isa_irq, ver;
1069         char __iomem *addr;
1070         unsigned long flags;
1071
1072         spin_lock_irqsave(&iosapic_lock, flags);
1073         addr = ioremap(phys_addr, 0);
1074         ver = iosapic_version(addr);
1075
1076         if ((err = iosapic_check_gsi_range(gsi_base, ver))) {
1077                 iounmap(addr);
1078                 spin_unlock_irqrestore(&iosapic_lock, flags);
1079                 return err;
1080         }
1081
1082         /*
1083          * The MAX_REDIR register holds the highest input pin number
1084          * (starting from 0).  We add 1 so that we can use it for
1085          * number of pins (= RTEs)
1086          */
1087         num_rte = ((ver >> 16) & 0xff) + 1;
1088
1089         index = iosapic_alloc();
1090         iosapic_lists[index].addr = addr;
1091         iosapic_lists[index].gsi_base = gsi_base;
1092         iosapic_lists[index].num_rte = num_rte;
1093 #ifdef CONFIG_NUMA
1094         iosapic_lists[index].node = MAX_NUMNODES;
1095 #endif
1096         spin_unlock_irqrestore(&iosapic_lock, flags);
1097
1098         if ((gsi_base == 0) && pcat_compat) {
1099                 /*
1100                  * Map the legacy ISA devices into the IOSAPIC data.  Some of
1101                  * these may get reprogrammed later on with data from the ACPI
1102                  * Interrupt Source Override table.
1103                  */
1104                 for (isa_irq = 0; isa_irq < 16; ++isa_irq)
1105                         iosapic_override_isa_irq(isa_irq, isa_irq,
1106                                                  IOSAPIC_POL_HIGH,
1107                                                  IOSAPIC_EDGE);
1108         }
1109         return 0;
1110 }
1111
1112 #ifdef CONFIG_HOTPLUG
1113 int
1114 iosapic_remove (unsigned int gsi_base)
1115 {
1116         int index, err = 0;
1117         unsigned long flags;
1118
1119         spin_lock_irqsave(&iosapic_lock, flags);
1120         index = find_iosapic(gsi_base);
1121         if (index < 0) {
1122                 printk(KERN_WARNING "%s: No IOSAPIC for GSI base %u\n",
1123                        __FUNCTION__, gsi_base);
1124                 goto out;
1125         }
1126
1127         if (iosapic_lists[index].rtes_inuse) {
1128                 err = -EBUSY;
1129                 printk(KERN_WARNING "%s: IOSAPIC for GSI base %u is busy\n",
1130                        __FUNCTION__, gsi_base);
1131                 goto out;
1132         }
1133
1134         iounmap(iosapic_lists[index].addr);
1135         iosapic_free(index);
1136  out:
1137         spin_unlock_irqrestore(&iosapic_lock, flags);
1138         return err;
1139 }
1140 #endif /* CONFIG_HOTPLUG */
1141
1142 #ifdef CONFIG_NUMA
1143 void __devinit
1144 map_iosapic_to_node(unsigned int gsi_base, int node)
1145 {
1146         int index;
1147
1148         index = find_iosapic(gsi_base);
1149         if (index < 0) {
1150                 printk(KERN_WARNING "%s: No IOSAPIC for GSI %u\n",
1151                        __FUNCTION__, gsi_base);
1152                 return;
1153         }
1154         iosapic_lists[index].node = node;
1155         return;
1156 }
1157 #endif
1158
1159 static int __init iosapic_enable_kmalloc (void)
1160 {
1161         iosapic_kmalloc_ok = 1;
1162         return 0;
1163 }
1164 core_initcall (iosapic_enable_kmalloc);