drivers/gpu/drm/i915/intel_ringbuffer.c

   1 /*
   2  * Copyright © 2008-2010 Intel Corporation
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  *
  23  * Authors:
  24  *    Eric Anholt <eric@anholt.net>
  25  *    Zou Nan hai <nanhai.zou@intel.com>
  26  *    Xiang Hai hao<haihao.xiang@intel.com>
  27  *
  28  */
  29
  30 #include <drm/drmP.h>
  31 #include "i915_drv.h"
  32 #include <drm/i915_drm.h>
  33 #include "i915_trace.h"
  34 #include "intel_drv.h"
  35
  36 /*
  37  * 965+ support PIPE_CONTROL commands, which provide finer grained control
  38  * over cache flushing.
  39  */
  40 struct pipe_control {
  41         struct drm_i915_gem_object *obj;
  42         volatile u32 *cpu_page;
  43         u32 gtt_offset;
  44 };
  45
  46 static inline int ring_space(struct intel_ring_buffer *ring)
  47 {
  48         int space = (ring->head & HEAD_ADDR) - (ring->tail + I915_RING_FREE_SPACE);
  49         if (space < 0)
  50                 space += ring->size;
  51         return space;
  52 }
  53
  54 static int
  55 gen2_render_ring_flush(struct intel_ring_buffer *ring,
  56                        u32      invalidate_domains,
  57                        u32      flush_domains)
  58 {
  59         u32 cmd;
  60         int ret;
  61
  62         cmd = MI_FLUSH;
  63         if (((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER) == 0)
  64                 cmd |= MI_NO_WRITE_FLUSH;
  65
  66         if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER)
  67                 cmd |= MI_READ_FLUSH;
  68
  69         ret = intel_ring_begin(ring, 2);
  70         if (ret)
  71                 return ret;
  72
  73         intel_ring_emit(ring, cmd);
  74         intel_ring_emit(ring, MI_NOOP);
  75         intel_ring_advance(ring);
  76
  77         return 0;
  78 }
  79
  80 static int
  81 gen4_render_ring_flush(struct intel_ring_buffer *ring,
  82                        u32      invalidate_domains,
  83                        u32      flush_domains)
  84 {
  85         struct drm_device *dev = ring->dev;
  86         u32 cmd;
  87         int ret;
  88
  89         /*
  90          * read/write caches:
  91          *
  92          * I915_GEM_DOMAIN_RENDER is always invalidated, but is
  93          * only flushed if MI_NO_WRITE_FLUSH is unset.  On 965, it is
  94          * also flushed at 2d versus 3d pipeline switches.
  95          *
  96          * read-only caches:
  97          *
  98          * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if
  99          * MI_READ_FLUSH is set, and is always flushed on 965.
 100          *
 101          * I915_GEM_DOMAIN_COMMAND may not exist?
 102          *
 103          * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is
 104          * invalidated when MI_EXE_FLUSH is set.
 105          *
 106          * I915_GEM_DOMAIN_VERTEX, which exists on 965, is
 107          * invalidated with every MI_FLUSH.
 108          *
 109          * TLBs:
 110          *
 111          * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND
 112          * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and
 113          * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER
 114          * are flushed at any MI_FLUSH.
 115          */
 116
 117         cmd = MI_FLUSH | MI_NO_WRITE_FLUSH;
 118         if ((invalidate_domains|flush_domains) & I915_GEM_DOMAIN_RENDER)
 119                 cmd &= ~MI_NO_WRITE_FLUSH;
 120         if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION)
 121                 cmd |= MI_EXE_FLUSH;
 122
 123         if (invalidate_domains & I915_GEM_DOMAIN_COMMAND &&
 124             (IS_G4X(dev) || IS_GEN5(dev)))
 125                 cmd |= MI_INVALIDATE_ISP;
 126
 127         ret = intel_ring_begin(ring, 2);
 128         if (ret)
 129                 return ret;
 130
 131         intel_ring_emit(ring, cmd);
 132         intel_ring_emit(ring, MI_NOOP);
 133         intel_ring_advance(ring);
 134
 135         return 0;
 136 }
 137
 138 /**
 139  * Emits a PIPE_CONTROL with a non-zero post-sync operation, for
 140  * implementing two workarounds on gen6.  From section 1.4.7.1
 141  * "PIPE_CONTROL" of the Sandy Bridge PRM volume 2 part 1:
 142  *
 143  * [DevSNB-C+{W/A}] Before any depth stall flush (including those
 144  * produced by non-pipelined state commands), software needs to first
 145  * send a PIPE_CONTROL with no bits set except Post-Sync Operation !=
 146  * 0.
 147  *
 148  * [Dev-SNB{W/A}]: Before a PIPE_CONTROL with Write Cache Flush Enable
 149  * =1, a PIPE_CONTROL with any non-zero post-sync-op is required.
 150  *
 151  * And the workaround for these two requires this workaround first:
 152  *
 153  * [Dev-SNB{W/A}]: Pipe-control with CS-stall bit set must be sent
 154  * BEFORE the pipe-control with a post-sync op and no write-cache
 155  * flushes.
 156  *
 157  * And this last workaround is tricky because of the requirements on
 158  * that bit.  From section 1.4.7.2.3 "Stall" of the Sandy Bridge PRM
 159  * volume 2 part 1:
 160  *
 161  *     "1 of the following must also be set:
 162  *      - Render Target Cache Flush Enable ([12] of DW1)
 163  *      - Depth Cache Flush Enable ([0] of DW1)
 164  *      - Stall at Pixel Scoreboard ([1] of DW1)
 165  *      - Depth Stall ([13] of DW1)
 166  *      - Post-Sync Operation ([13] of DW1)
 167  *      - Notify Enable ([8] of DW1)"
 168  *
 169  * The cache flushes require the workaround flush that triggered this
 170  * one, so we can't use it.  Depth stall would trigger the same.
 171  * Post-sync nonzero is what triggered this second workaround, so we
 172  * can't use that one either.  Notify enable is IRQs, which aren't
 173  * really our business.  That leaves only stall at scoreboard.
 174  */
 175 static int
 176 intel_emit_post_sync_nonzero_flush(struct intel_ring_buffer *ring)
 177 {
 178         struct pipe_control *pc = ring->private;
 179         u32 scratch_addr = pc->gtt_offset + 128;
 180         int ret;
 181
 182
 183         ret = intel_ring_begin(ring, 6);
 184         if (ret)
 185                 return ret;
 186
 187         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 188         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 189                         PIPE_CONTROL_STALL_AT_SCOREBOARD);
 190         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 191         intel_ring_emit(ring, 0); /* low dword */
 192         intel_ring_emit(ring, 0); /* high dword */
 193         intel_ring_emit(ring, MI_NOOP);
 194         intel_ring_advance(ring);
 195
 196         ret = intel_ring_begin(ring, 6);
 197         if (ret)
 198                 return ret;
 199
 200         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(5));
 201         intel_ring_emit(ring, PIPE_CONTROL_QW_WRITE);
 202         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT); /* address */
 203         intel_ring_emit(ring, 0);
 204         intel_ring_emit(ring, 0);
 205         intel_ring_emit(ring, MI_NOOP);
 206         intel_ring_advance(ring);
 207
 208         return 0;
 209 }
 210
 211 static int
 212 gen6_render_ring_flush(struct intel_ring_buffer *ring,
 213                          u32 invalidate_domains, u32 flush_domains)
 214 {
 215         u32 flags = 0;
 216         struct pipe_control *pc = ring->private;
 217         u32 scratch_addr = pc->gtt_offset + 128;
 218         int ret;
 219
 220         /* Force SNB workarounds for PIPE_CONTROL flushes */
 221         ret = intel_emit_post_sync_nonzero_flush(ring);
 222         if (ret)
 223                 return ret;
 224
 225         /* Just flush everything.  Experiments have shown that reducing the
 226          * number of bits based on the write domains has little performance
 227          * impact.
 228          */
 229         if (flush_domains) {
 230                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 231                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 232                 /*
 233                  * Ensure that any following seqno writes only happen
 234                  * when the render cache is indeed flushed.
 235                  */
 236                 flags |= PIPE_CONTROL_CS_STALL;
 237         }
 238         if (invalidate_domains) {
 239                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 240                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 241                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 242                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 243                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 244                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 245                 /*
 246                  * TLB invalidate requires a post-sync write.
 247                  */
 248                 flags |= PIPE_CONTROL_QW_WRITE | PIPE_CONTROL_CS_STALL;
 249         }
 250
 251         ret = intel_ring_begin(ring, 4);
 252         if (ret)
 253                 return ret;
 254
 255         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 256         intel_ring_emit(ring, flags);
 257         intel_ring_emit(ring, scratch_addr | PIPE_CONTROL_GLOBAL_GTT);
 258         intel_ring_emit(ring, 0);
 259         intel_ring_advance(ring);
 260
 261         return 0;
 262 }
 263
 264 static int
 265 gen7_render_ring_cs_stall_wa(struct intel_ring_buffer *ring)
 266 {
 267         int ret;
 268
 269         ret = intel_ring_begin(ring, 4);
 270         if (ret)
 271                 return ret;
 272
 273         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 274         intel_ring_emit(ring, PIPE_CONTROL_CS_STALL |
 275                               PIPE_CONTROL_STALL_AT_SCOREBOARD);
 276         intel_ring_emit(ring, 0);
 277         intel_ring_emit(ring, 0);
 278         intel_ring_advance(ring);
 279
 280         return 0;
 281 }
 282
 283 static int gen7_ring_fbc_flush(struct intel_ring_buffer *ring, u32 value)
 284 {
 285         int ret;
 286
 287         if (!ring->fbc_dirty)
 288                 return 0;
 289
 290         ret = intel_ring_begin(ring, 4);
 291         if (ret)
 292                 return ret;
 293         intel_ring_emit(ring, MI_NOOP);
 294         /* WaFbcNukeOn3DBlt:ivb/hsw */
 295         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 296         intel_ring_emit(ring, MSG_FBC_REND_STATE);
 297         intel_ring_emit(ring, value);
 298         intel_ring_advance(ring);
 299
 300         ring->fbc_dirty = false;
 301         return 0;
 302 }
 303
 304 static int
 305 gen7_render_ring_flush(struct intel_ring_buffer *ring,
 306                        u32 invalidate_domains, u32 flush_domains)
 307 {
 308         u32 flags = 0;
 309         struct pipe_control *pc = ring->private;
 310         u32 scratch_addr = pc->gtt_offset + 128;
 311         int ret;
 312
 313         /*
 314          * Ensure that any following seqno writes only happen when the render
 315          * cache is indeed flushed.
 316          *
 317          * Workaround: 4th PIPE_CONTROL command (except the ones with only
 318          * read-cache invalidate bits set) must have the CS_STALL bit set. We
 319          * don't try to be clever and just set it unconditionally.
 320          */
 321         flags |= PIPE_CONTROL_CS_STALL;
 322
 323         /* Just flush everything.  Experiments have shown that reducing the
 324          * number of bits based on the write domains has little performance
 325          * impact.
 326          */
 327         if (flush_domains) {
 328                 flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH;
 329                 flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH;
 330         }
 331         if (invalidate_domains) {
 332                 flags |= PIPE_CONTROL_TLB_INVALIDATE;
 333                 flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE;
 334                 flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
 335                 flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE;
 336                 flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE;
 337                 flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE;
 338                 /*
 339                  * TLB invalidate requires a post-sync write.
 340                  */
 341                 flags |= PIPE_CONTROL_QW_WRITE;
 342                 flags |= PIPE_CONTROL_GLOBAL_GTT_IVB;
 343
 344                 /* Workaround: we must issue a pipe_control with CS-stall bit
 345                  * set before a pipe_control command that has the state cache
 346                  * invalidate bit set. */
 347                 gen7_render_ring_cs_stall_wa(ring);
 348         }
 349
 350         ret = intel_ring_begin(ring, 4);
 351         if (ret)
 352                 return ret;
 353
 354         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4));
 355         intel_ring_emit(ring, flags);
 356         intel_ring_emit(ring, scratch_addr);
 357         intel_ring_emit(ring, 0);
 358         intel_ring_advance(ring);
 359
 360         if (flush_domains)
 361                 return gen7_ring_fbc_flush(ring, FBC_REND_NUKE);
 362
 363         return 0;
 364 }
 365
 366 static void ring_write_tail(struct intel_ring_buffer *ring,
 367                             u32 value)
 368 {
 369         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 370         I915_WRITE_TAIL(ring, value);
 371 }
 372
 373 u32 intel_ring_get_active_head(struct intel_ring_buffer *ring)
 374 {
 375         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 376         u32 acthd_reg = INTEL_INFO(ring->dev)->gen >= 4 ?
 377                         RING_ACTHD(ring->mmio_base) : ACTHD;
 378
 379         return I915_READ(acthd_reg);
 380 }
 381
 382 static int init_ring_common(struct intel_ring_buffer *ring)
 383 {
 384         struct drm_device *dev = ring->dev;
 385         drm_i915_private_t *dev_priv = dev->dev_private;
 386         struct drm_i915_gem_object *obj = ring->obj;
 387         int ret = 0;
 388         u32 head;
 389
 390         if (HAS_FORCE_WAKE(dev))
 391                 gen6_gt_force_wake_get(dev_priv);
 392
 393         /* Stop the ring if it's running. */
 394         I915_WRITE_CTL(ring, 0);
 395         I915_WRITE_HEAD(ring, 0);
 396         ring->write_tail(ring, 0);
 397
 398         head = I915_READ_HEAD(ring) & HEAD_ADDR;
 399
 400         /* G45 ring initialization fails to reset head to zero */
 401         if (head != 0) {
 402                 DRM_DEBUG_KMS("%s head not reset to zero "
 403                               "ctl %08x head %08x tail %08x start %08x\n",
 404                               ring->name,
 405                               I915_READ_CTL(ring),
 406                               I915_READ_HEAD(ring),
 407                               I915_READ_TAIL(ring),
 408                               I915_READ_START(ring));
 409
 410                 I915_WRITE_HEAD(ring, 0);
 411
 412                 if (I915_READ_HEAD(ring) & HEAD_ADDR) {
 413                         DRM_ERROR("failed to set %s head to zero "
 414                                   "ctl %08x head %08x tail %08x start %08x\n",
 415                                   ring->name,
 416                                   I915_READ_CTL(ring),
 417                                   I915_READ_HEAD(ring),
 418                                   I915_READ_TAIL(ring),
 419                                   I915_READ_START(ring));
 420                 }
 421         }
 422
 423         /* Initialize the ring. This must happen _after_ we've cleared the ring
 424          * registers with the above sequence (the readback of the HEAD registers
 425          * also enforces ordering), otherwise the hw might lose the new ring
 426          * register values. */
 427         I915_WRITE_START(ring, obj->gtt_offset);
 428         I915_WRITE_CTL(ring,
 429                         ((ring->size - PAGE_SIZE) & RING_NR_PAGES)
 430                         | RING_VALID);
 431
 432         /* If the head is still not zero, the ring is dead */
 433         if (wait_for((I915_READ_CTL(ring) & RING_VALID) != 0 &&
 434                      I915_READ_START(ring) == obj->gtt_offset &&
 435                      (I915_READ_HEAD(ring) & HEAD_ADDR) == 0, 50)) {
 436                 DRM_ERROR("%s initialization failed "
 437                                 "ctl %08x head %08x tail %08x start %08x\n",
 438                                 ring->name,
 439                                 I915_READ_CTL(ring),
 440                                 I915_READ_HEAD(ring),
 441                                 I915_READ_TAIL(ring),
 442                                 I915_READ_START(ring));
 443                 ret = -EIO;
 444                 goto out;
 445         }
 446
 447         if (!drm_core_check_feature(ring->dev, DRIVER_MODESET))
 448                 i915_kernel_lost_context(ring->dev);
 449         else {
 450                 ring->head = I915_READ_HEAD(ring);
 451                 ring->tail = I915_READ_TAIL(ring) & TAIL_ADDR;
 452                 ring->space = ring_space(ring);
 453                 ring->last_retired_head = -1;
 454         }
 455
 456 out:
 457         if (HAS_FORCE_WAKE(dev))
 458                 gen6_gt_force_wake_put(dev_priv);
 459
 460         return ret;
 461 }
 462
 463 static int
 464 init_pipe_control(struct intel_ring_buffer *ring)
 465 {
 466         struct pipe_control *pc;
 467         struct drm_i915_gem_object *obj;
 468         int ret;
 469
 470         if (ring->private)
 471                 return 0;
 472
 473         pc = kmalloc(sizeof(*pc), GFP_KERNEL);
 474         if (!pc)
 475                 return -ENOMEM;
 476
 477         obj = i915_gem_alloc_object(ring->dev, 4096);
 478         if (obj == NULL) {
 479                 DRM_ERROR("Failed to allocate seqno page\n");
 480                 ret = -ENOMEM;
 481                 goto err;
 482         }
 483
 484         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
 485
 486         ret = i915_gem_object_pin(obj, 4096, true, false);
 487         if (ret)
 488                 goto err_unref;
 489
 490         pc->gtt_offset = obj->gtt_offset;
 491         pc->cpu_page = kmap(sg_page(obj->pages->sgl));
 492         if (pc->cpu_page == NULL) {
 493                 ret = -ENOMEM;
 494                 goto err_unpin;
 495         }
 496
 497         DRM_DEBUG_DRIVER("%s pipe control offset: 0x%08x\n",
 498                          ring->name, pc->gtt_offset);
 499
 500         pc->obj = obj;
 501         ring->private = pc;
 502         return 0;
 503
 504 err_unpin:
 505         i915_gem_object_unpin(obj);
 506 err_unref:
 507         drm_gem_object_unreference(&obj->base);
 508 err:
 509         kfree(pc);
 510         return ret;
 511 }
 512
 513 static void
 514 cleanup_pipe_control(struct intel_ring_buffer *ring)
 515 {
 516         struct pipe_control *pc = ring->private;
 517         struct drm_i915_gem_object *obj;
 518
 519         if (!ring->private)
 520                 return;
 521
 522         obj = pc->obj;
 523
 524         kunmap(sg_page(obj->pages->sgl));
 525         i915_gem_object_unpin(obj);
 526         drm_gem_object_unreference(&obj->base);
 527
 528         kfree(pc);
 529         ring->private = NULL;
 530 }
 531
 532 static int init_render_ring(struct intel_ring_buffer *ring)
 533 {
 534         struct drm_device *dev = ring->dev;
 535         struct drm_i915_private *dev_priv = dev->dev_private;
 536         int ret = init_ring_common(ring);
 537
 538         if (INTEL_INFO(dev)->gen > 3)
 539                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(VS_TIMER_DISPATCH));
 540
 541         /* We need to disable the AsyncFlip performance optimisations in order
 542          * to use MI_WAIT_FOR_EVENT within the CS. It should already be
 543          * programmed to '1' on all products.
 544          *
 545          * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv
 546          */
 547         if (INTEL_INFO(dev)->gen >= 6)
 548                 I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE));
 549
 550         /* Required for the hardware to program scanline values for waiting */
 551         if (INTEL_INFO(dev)->gen == 6)
 552                 I915_WRITE(GFX_MODE,
 553                            _MASKED_BIT_ENABLE(GFX_TLB_INVALIDATE_ALWAYS));
 554
 555         if (IS_GEN7(dev))
 556                 I915_WRITE(GFX_MODE_GEN7,
 557                            _MASKED_BIT_DISABLE(GFX_TLB_INVALIDATE_ALWAYS) |
 558                            _MASKED_BIT_ENABLE(GFX_REPLAY_MODE));
 559
 560         if (INTEL_INFO(dev)->gen >= 5) {
 561                 ret = init_pipe_control(ring);
 562                 if (ret)
 563                         return ret;
 564         }
 565
 566         if (IS_GEN6(dev)) {
 567                 /* From the Sandybridge PRM, volume 1 part 3, page 24:
 568                  * "If this bit is set, STCunit will have LRA as replacement
 569                  *  policy. [...] This bit must be reset.  LRA replacement
 570                  *  policy is not supported."
 571                  */
 572                 I915_WRITE(CACHE_MODE_0,
 573                            _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
 574
 575                 /* This is not explicitly set for GEN6, so read the register.
 576                  * see intel_ring_mi_set_context() for why we care.
 577                  * TODO: consider explicitly setting the bit for GEN5
 578                  */
 579                 ring->itlb_before_ctx_switch =
 580                         !!(I915_READ(GFX_MODE) & GFX_TLB_INVALIDATE_ALWAYS);
 581         }
 582
 583         if (INTEL_INFO(dev)->gen >= 6)
 584                 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING));
 585
 586         if (HAS_L3_GPU_CACHE(dev))
 587                 I915_WRITE_IMR(ring, ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
 588
 589         return ret;
 590 }
 591
 592 static void render_ring_cleanup(struct intel_ring_buffer *ring)
 593 {
 594         struct drm_device *dev = ring->dev;
 595
 596         if (!ring->private)
 597                 return;
 598
 599         if (HAS_BROKEN_CS_TLB(dev))
 600                 drm_gem_object_unreference(to_gem_object(ring->private));
 601
 602         cleanup_pipe_control(ring);
 603 }
 604
 605 static void
 606 update_mboxes(struct intel_ring_buffer *ring,
 607               u32 mmio_offset)
 608 {
 609 /* NB: In order to be able to do semaphore MBOX updates for varying number
 610  * of rings, it's easiest if we round up each individual update to a
 611  * multiple of 2 (since ring updates must always be a multiple of 2)
 612  * even though the actual update only requires 3 dwords.
 613  */
 614 #define MBOX_UPDATE_DWORDS 4
 615         intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(1));
 616         intel_ring_emit(ring, mmio_offset);
 617         intel_ring_emit(ring, ring->outstanding_lazy_request);
 618         intel_ring_emit(ring, MI_NOOP);
 619 }
 620
 621 /**
 622  * gen6_add_request - Update the semaphore mailbox registers
 623  *
 624  * @ring - ring that is adding a request
 625  * @seqno - return seqno stuck into the ring
 626  *
 627  * Update the mailbox registers in the *other* rings with the current seqno.
 628  * This acts like a signal in the canonical semaphore.
 629  */
 630 static int
 631 gen6_add_request(struct intel_ring_buffer *ring)
 632 {
 633         struct drm_device *dev = ring->dev;
 634         struct drm_i915_private *dev_priv = dev->dev_private;
 635         struct intel_ring_buffer *useless;
 636         int i, ret;
 637
 638         ret = intel_ring_begin(ring, ((I915_NUM_RINGS-1) *
 639                                       MBOX_UPDATE_DWORDS) +
 640                                       4);
 641         if (ret)
 642                 return ret;
 643 #undef MBOX_UPDATE_DWORDS
 644
 645         for_each_ring(useless, dev_priv, i) {
 646                 u32 mbox_reg = ring->signal_mbox[i];
 647                 if (mbox_reg != GEN6_NOSYNC)
 648                         update_mboxes(ring, mbox_reg);
 649         }
 650
 651         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 652         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 653         intel_ring_emit(ring, ring->outstanding_lazy_request);
 654         intel_ring_emit(ring, MI_USER_INTERRUPT);
 655         intel_ring_advance(ring);
 656
 657         return 0;
 658 }
 659
 660 static inline bool i915_gem_has_seqno_wrapped(struct drm_device *dev,
 661                                               u32 seqno)
 662 {
 663         struct drm_i915_private *dev_priv = dev->dev_private;
 664         return dev_priv->last_seqno < seqno;
 665 }
 666
 667 /**
 668  * intel_ring_sync - sync the waiter to the signaller on seqno
 669  *
 670  * @waiter - ring that is waiting
 671  * @signaller - ring which has, or will signal
 672  * @seqno - seqno which the waiter will block on
 673  */
 674 static int
 675 gen6_ring_sync(struct intel_ring_buffer *waiter,
 676                struct intel_ring_buffer *signaller,
 677                u32 seqno)
 678 {
 679         int ret;
 680         u32 dw1 = MI_SEMAPHORE_MBOX |
 681                   MI_SEMAPHORE_COMPARE |
 682                   MI_SEMAPHORE_REGISTER;
 683
 684         /* Throughout all of the GEM code, seqno passed implies our current
 685          * seqno is >= the last seqno executed. However for hardware the
 686          * comparison is strictly greater than.
 687          */
 688         seqno -= 1;
 689
 690         WARN_ON(signaller->semaphore_register[waiter->id] ==
 691                 MI_SEMAPHORE_SYNC_INVALID);
 692
 693         ret = intel_ring_begin(waiter, 4);
 694         if (ret)
 695                 return ret;
 696
 697         /* If seqno wrap happened, omit the wait with no-ops */
 698         if (likely(!i915_gem_has_seqno_wrapped(waiter->dev, seqno))) {
 699                 intel_ring_emit(waiter,
 700                                 dw1 |
 701                                 signaller->semaphore_register[waiter->id]);
 702                 intel_ring_emit(waiter, seqno);
 703                 intel_ring_emit(waiter, 0);
 704                 intel_ring_emit(waiter, MI_NOOP);
 705         } else {
 706                 intel_ring_emit(waiter, MI_NOOP);
 707                 intel_ring_emit(waiter, MI_NOOP);
 708                 intel_ring_emit(waiter, MI_NOOP);
 709                 intel_ring_emit(waiter, MI_NOOP);
 710         }
 711         intel_ring_advance(waiter);
 712
 713         return 0;
 714 }
 715
 716 #define PIPE_CONTROL_FLUSH(ring__, addr__)                                      \
 717 do {                                                                    \
 718         intel_ring_emit(ring__, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |                \
 719                  PIPE_CONTROL_DEPTH_STALL);                             \
 720         intel_ring_emit(ring__, (addr__) | PIPE_CONTROL_GLOBAL_GTT);                    \
 721         intel_ring_emit(ring__, 0);                                                     \
 722         intel_ring_emit(ring__, 0);                                                     \
 723 } while (0)
 724
 725 static int
 726 pc_render_add_request(struct intel_ring_buffer *ring)
 727 {
 728         struct pipe_control *pc = ring->private;
 729         u32 scratch_addr = pc->gtt_offset + 128;
 730         int ret;
 731
 732         /* For Ironlake, MI_USER_INTERRUPT was deprecated and apparently
 733          * incoherent with writes to memory, i.e. completely fubar,
 734          * so we need to use PIPE_NOTIFY instead.
 735          *
 736          * However, we also need to workaround the qword write
 737          * incoherence by flushing the 6 PIPE_NOTIFY buffers out to
 738          * memory before requesting an interrupt.
 739          */
 740         ret = intel_ring_begin(ring, 32);
 741         if (ret)
 742                 return ret;
 743
 744         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 745                         PIPE_CONTROL_WRITE_FLUSH |
 746                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE);
 747         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 748         intel_ring_emit(ring, ring->outstanding_lazy_request);
 749         intel_ring_emit(ring, 0);
 750         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 751         scratch_addr += 128; /* write to separate cachelines */
 752         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 753         scratch_addr += 128;
 754         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 755         scratch_addr += 128;
 756         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 757         scratch_addr += 128;
 758         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 759         scratch_addr += 128;
 760         PIPE_CONTROL_FLUSH(ring, scratch_addr);
 761
 762         intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE |
 763                         PIPE_CONTROL_WRITE_FLUSH |
 764                         PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
 765                         PIPE_CONTROL_NOTIFY);
 766         intel_ring_emit(ring, pc->gtt_offset | PIPE_CONTROL_GLOBAL_GTT);
 767         intel_ring_emit(ring, ring->outstanding_lazy_request);
 768         intel_ring_emit(ring, 0);
 769         intel_ring_advance(ring);
 770
 771         return 0;
 772 }
 773
 774 static u32
 775 gen6_ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 776 {
 777         /* Workaround to force correct ordering between irq and seqno writes on
 778          * ivb (and maybe also on snb) by reading from a CS register (like
 779          * ACTHD) before reading the status page. */
 780         if (!lazy_coherency)
 781                 intel_ring_get_active_head(ring);
 782         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 783 }
 784
 785 static u32
 786 ring_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 787 {
 788         return intel_read_status_page(ring, I915_GEM_HWS_INDEX);
 789 }
 790
 791 static void
 792 ring_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 793 {
 794         intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno);
 795 }
 796
 797 static u32
 798 pc_render_get_seqno(struct intel_ring_buffer *ring, bool lazy_coherency)
 799 {
 800         struct pipe_control *pc = ring->private;
 801         return pc->cpu_page[0];
 802 }
 803
 804 static void
 805 pc_render_set_seqno(struct intel_ring_buffer *ring, u32 seqno)
 806 {
 807         struct pipe_control *pc = ring->private;
 808         pc->cpu_page[0] = seqno;
 809 }
 810
 811 static bool
 812 gen5_ring_get_irq(struct intel_ring_buffer *ring)
 813 {
 814         struct drm_device *dev = ring->dev;
 815         drm_i915_private_t *dev_priv = dev->dev_private;
 816         unsigned long flags;
 817
 818         if (!dev->irq_enabled)
 819                 return false;
 820
 821         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 822         if (ring->irq_refcount.gt++ == 0) {
 823                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
 824                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 825                 POSTING_READ(GTIMR);
 826         }
 827         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 828
 829         return true;
 830 }
 831
 832 static void
 833 gen5_ring_put_irq(struct intel_ring_buffer *ring)
 834 {
 835         struct drm_device *dev = ring->dev;
 836         drm_i915_private_t *dev_priv = dev->dev_private;
 837         unsigned long flags;
 838
 839         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 840         if (--ring->irq_refcount.gt == 0) {
 841                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
 842                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
 843                 POSTING_READ(GTIMR);
 844         }
 845         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 846 }
 847
 848 static bool
 849 i9xx_ring_get_irq(struct intel_ring_buffer *ring)
 850 {
 851         struct drm_device *dev = ring->dev;
 852         drm_i915_private_t *dev_priv = dev->dev_private;
 853         unsigned long flags;
 854
 855         if (!dev->irq_enabled)
 856                 return false;
 857
 858         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 859         if (ring->irq_refcount.gt++ == 0) {
 860                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 861                 I915_WRITE(IMR, dev_priv->irq_mask);
 862                 POSTING_READ(IMR);
 863         }
 864         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 865
 866         return true;
 867 }
 868
 869 static void
 870 i9xx_ring_put_irq(struct intel_ring_buffer *ring)
 871 {
 872         struct drm_device *dev = ring->dev;
 873         drm_i915_private_t *dev_priv = dev->dev_private;
 874         unsigned long flags;
 875
 876         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 877         if (--ring->irq_refcount.gt == 0) {
 878                 dev_priv->irq_mask |= ring->irq_enable_mask;
 879                 I915_WRITE(IMR, dev_priv->irq_mask);
 880                 POSTING_READ(IMR);
 881         }
 882         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 883 }
 884
 885 static bool
 886 i8xx_ring_get_irq(struct intel_ring_buffer *ring)
 887 {
 888         struct drm_device *dev = ring->dev;
 889         drm_i915_private_t *dev_priv = dev->dev_private;
 890         unsigned long flags;
 891
 892         if (!dev->irq_enabled)
 893                 return false;
 894
 895         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 896         if (ring->irq_refcount.gt++ == 0) {
 897                 dev_priv->irq_mask &= ~ring->irq_enable_mask;
 898                 I915_WRITE16(IMR, dev_priv->irq_mask);
 899                 POSTING_READ16(IMR);
 900         }
 901         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 902
 903         return true;
 904 }
 905
 906 static void
 907 i8xx_ring_put_irq(struct intel_ring_buffer *ring)
 908 {
 909         struct drm_device *dev = ring->dev;
 910         drm_i915_private_t *dev_priv = dev->dev_private;
 911         unsigned long flags;
 912
 913         spin_lock_irqsave(&dev_priv->irq_lock, flags);
 914         if (--ring->irq_refcount.gt == 0) {
 915                 dev_priv->irq_mask |= ring->irq_enable_mask;
 916                 I915_WRITE16(IMR, dev_priv->irq_mask);
 917                 POSTING_READ16(IMR);
 918         }
 919         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
 920 }
 921
 922 void intel_ring_setup_status_page(struct intel_ring_buffer *ring)
 923 {
 924         struct drm_device *dev = ring->dev;
 925         drm_i915_private_t *dev_priv = ring->dev->dev_private;
 926         u32 mmio = 0;
 927
 928         /* The ring status page addresses are no longer next to the rest of
 929          * the ring registers as of gen7.
 930          */
 931         if (IS_GEN7(dev)) {
 932                 switch (ring->id) {
 933                 case RCS:
 934                         mmio = RENDER_HWS_PGA_GEN7;
 935                         break;
 936                 case BCS:
 937                         mmio = BLT_HWS_PGA_GEN7;
 938                         break;
 939                 case VCS:
 940                         mmio = BSD_HWS_PGA_GEN7;
 941                         break;
 942                 case VECS:
 943                         mmio = VEBOX_HWS_PGA_GEN7;
 944                         break;
 945                 }
 946         } else if (IS_GEN6(ring->dev)) {
 947                 mmio = RING_HWS_PGA_GEN6(ring->mmio_base);
 948         } else {
 949                 mmio = RING_HWS_PGA(ring->mmio_base);
 950         }
 951
 952         I915_WRITE(mmio, (u32)ring->status_page.gfx_addr);
 953         POSTING_READ(mmio);
 954 }
 955
 956 static int
 957 bsd_ring_flush(struct intel_ring_buffer *ring,
 958                u32     invalidate_domains,
 959                u32     flush_domains)
 960 {
 961         int ret;
 962
 963         ret = intel_ring_begin(ring, 2);
 964         if (ret)
 965                 return ret;
 966
 967         intel_ring_emit(ring, MI_FLUSH);
 968         intel_ring_emit(ring, MI_NOOP);
 969         intel_ring_advance(ring);
 970         return 0;
 971 }
 972
 973 static int
 974 i9xx_add_request(struct intel_ring_buffer *ring)
 975 {
 976         int ret;
 977
 978         ret = intel_ring_begin(ring, 4);
 979         if (ret)
 980                 return ret;
 981
 982         intel_ring_emit(ring, MI_STORE_DWORD_INDEX);
 983         intel_ring_emit(ring, I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT);
 984         intel_ring_emit(ring, ring->outstanding_lazy_request);
 985         intel_ring_emit(ring, MI_USER_INTERRUPT);
 986         intel_ring_advance(ring);
 987
 988         return 0;
 989 }
 990
 991 static bool
 992 gen6_ring_get_irq(struct intel_ring_buffer *ring)
 993 {
 994         struct drm_device *dev = ring->dev;
 995         drm_i915_private_t *dev_priv = dev->dev_private;
 996         unsigned long flags;
 997
 998         if (!dev->irq_enabled)
 999                return false;
1000
1001         /* It looks like we need to prevent the gt from suspending while waiting
1002          * for an notifiy irq, otherwise irqs seem to get lost on at least the
1003          * blt/bsd rings on ivb. */
1004         gen6_gt_force_wake_get(dev_priv);
1005
1006         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1007         if (ring->irq_refcount.gt++ == 0) {
1008                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1009                         I915_WRITE_IMR(ring,
1010                                        ~(ring->irq_enable_mask |
1011                                          GT_RENDER_L3_PARITY_ERROR_INTERRUPT));
1012                 else
1013                         I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1014                 dev_priv->gt_irq_mask &= ~ring->irq_enable_mask;
1015                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1016                 POSTING_READ(GTIMR);
1017         }
1018         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1019
1020         return true;
1021 }
1022
1023 static void
1024 gen6_ring_put_irq(struct intel_ring_buffer *ring)
1025 {
1026         struct drm_device *dev = ring->dev;
1027         drm_i915_private_t *dev_priv = dev->dev_private;
1028         unsigned long flags;
1029
1030         spin_lock_irqsave(&dev_priv->irq_lock, flags);
1031         if (--ring->irq_refcount.gt == 0) {
1032                 if (HAS_L3_GPU_CACHE(dev) && ring->id == RCS)
1033                         I915_WRITE_IMR(ring,
1034                                        ~GT_RENDER_L3_PARITY_ERROR_INTERRUPT);
1035                 else
1036                         I915_WRITE_IMR(ring, ~0);
1037                 dev_priv->gt_irq_mask |= ring->irq_enable_mask;
1038                 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
1039                 POSTING_READ(GTIMR);
1040         }
1041         spin_unlock_irqrestore(&dev_priv->irq_lock, flags);
1042
1043         gen6_gt_force_wake_put(dev_priv);
1044 }
1045
1046 static bool
1047 hsw_vebox_get_irq(struct intel_ring_buffer *ring)
1048 {
1049         struct drm_device *dev = ring->dev;
1050         struct drm_i915_private *dev_priv = dev->dev_private;
1051         unsigned long flags;
1052
1053         if (!dev->irq_enabled)
1054                 return false;
1055
1056         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1057         if (ring->irq_refcount.pm++ == 0) {
1058                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1059                 I915_WRITE_IMR(ring, ~ring->irq_enable_mask);
1060                 I915_WRITE(GEN6_PMIMR, pm_imr & ~ring->irq_enable_mask);
1061                 POSTING_READ(GEN6_PMIMR);
1062         }
1063         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1064
1065         return true;
1066 }
1067
1068 static void
1069 hsw_vebox_put_irq(struct intel_ring_buffer *ring)
1070 {
1071         struct drm_device *dev = ring->dev;
1072         struct drm_i915_private *dev_priv = dev->dev_private;
1073         unsigned long flags;
1074
1075         if (!dev->irq_enabled)
1076                 return;
1077
1078         spin_lock_irqsave(&dev_priv->rps.lock, flags);
1079         if (--ring->irq_refcount.pm == 0) {
1080                 u32 pm_imr = I915_READ(GEN6_PMIMR);
1081                 I915_WRITE_IMR(ring, ~0);
1082                 I915_WRITE(GEN6_PMIMR, pm_imr | ring->irq_enable_mask);
1083                 POSTING_READ(GEN6_PMIMR);
1084         }
1085         spin_unlock_irqrestore(&dev_priv->rps.lock, flags);
1086 }
1087
1088 static int
1089 i965_dispatch_execbuffer(struct intel_ring_buffer *ring,
1090                          u32 offset, u32 length,
1091                          unsigned flags)
1092 {
1093         int ret;
1094
1095         ret = intel_ring_begin(ring, 2);
1096         if (ret)
1097                 return ret;
1098
1099         intel_ring_emit(ring,
1100                         MI_BATCH_BUFFER_START |
1101                         MI_BATCH_GTT |
1102                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1103         intel_ring_emit(ring, offset);
1104         intel_ring_advance(ring);
1105
1106         return 0;
1107 }
1108
1109 /* Just userspace ABI convention to limit the wa batch bo to a resonable size */
1110 #define I830_BATCH_LIMIT (256*1024)
1111 static int
1112 i830_dispatch_execbuffer(struct intel_ring_buffer *ring,
1113                                 u32 offset, u32 len,
1114                                 unsigned flags)
1115 {
1116         int ret;
1117
1118         if (flags & I915_DISPATCH_PINNED) {
1119                 ret = intel_ring_begin(ring, 4);
1120                 if (ret)
1121                         return ret;
1122
1123                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1124                 intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1125                 intel_ring_emit(ring, offset + len - 8);
1126                 intel_ring_emit(ring, MI_NOOP);
1127                 intel_ring_advance(ring);
1128         } else {
1129                 struct drm_i915_gem_object *obj = ring->private;
1130                 u32 cs_offset = obj->gtt_offset;
1131
1132                 if (len > I830_BATCH_LIMIT)
1133                         return -ENOSPC;
1134
1135                 ret = intel_ring_begin(ring, 9+3);
1136                 if (ret)
1137                         return ret;
1138                 /* Blit the batch (which has now all relocs applied) to the stable batch
1139                  * scratch bo area (so that the CS never stumbles over its tlb
1140                  * invalidation bug) ... */
1141                 intel_ring_emit(ring, XY_SRC_COPY_BLT_CMD |
1142                                 XY_SRC_COPY_BLT_WRITE_ALPHA |
1143                                 XY_SRC_COPY_BLT_WRITE_RGB);
1144                 intel_ring_emit(ring, BLT_DEPTH_32 | BLT_ROP_GXCOPY | 4096);
1145                 intel_ring_emit(ring, 0);
1146                 intel_ring_emit(ring, (DIV_ROUND_UP(len, 4096) << 16) | 1024);
1147                 intel_ring_emit(ring, cs_offset);
1148                 intel_ring_emit(ring, 0);
1149                 intel_ring_emit(ring, 4096);
1150                 intel_ring_emit(ring, offset);
1151                 intel_ring_emit(ring, MI_FLUSH);
1152
1153                 /* ... and execute it. */
1154                 intel_ring_emit(ring, MI_BATCH_BUFFER);
1155                 intel_ring_emit(ring, cs_offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1156                 intel_ring_emit(ring, cs_offset + len - 8);
1157                 intel_ring_advance(ring);
1158         }
1159
1160         return 0;
1161 }
1162
1163 static int
1164 i915_dispatch_execbuffer(struct intel_ring_buffer *ring,
1165                          u32 offset, u32 len,
1166                          unsigned flags)
1167 {
1168         int ret;
1169
1170         ret = intel_ring_begin(ring, 2);
1171         if (ret)
1172                 return ret;
1173
1174         intel_ring_emit(ring, MI_BATCH_BUFFER_START | MI_BATCH_GTT);
1175         intel_ring_emit(ring, offset | (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE));
1176         intel_ring_advance(ring);
1177
1178         return 0;
1179 }
1180
1181 static void cleanup_status_page(struct intel_ring_buffer *ring)
1182 {
1183         struct drm_i915_gem_object *obj;
1184
1185         obj = ring->status_page.obj;
1186         if (obj == NULL)
1187                 return;
1188
1189         kunmap(sg_page(obj->pages->sgl));
1190         i915_gem_object_unpin(obj);
1191         drm_gem_object_unreference(&obj->base);
1192         ring->status_page.obj = NULL;
1193 }
1194
1195 static int init_status_page(struct intel_ring_buffer *ring)
1196 {
1197         struct drm_device *dev = ring->dev;
1198         struct drm_i915_gem_object *obj;
1199         int ret;
1200
1201         obj = i915_gem_alloc_object(dev, 4096);
1202         if (obj == NULL) {
1203                 DRM_ERROR("Failed to allocate status page\n");
1204                 ret = -ENOMEM;
1205                 goto err;
1206         }
1207
1208         i915_gem_object_set_cache_level(obj, I915_CACHE_LLC);
1209
1210         ret = i915_gem_object_pin(obj, 4096, true, false);
1211         if (ret != 0) {
1212                 goto err_unref;
1213         }
1214
1215         ring->status_page.gfx_addr = obj->gtt_offset;
1216         ring->status_page.page_addr = kmap(sg_page(obj->pages->sgl));
1217         if (ring->status_page.page_addr == NULL) {
1218                 ret = -ENOMEM;
1219                 goto err_unpin;
1220         }
1221         ring->status_page.obj = obj;
1222         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1223
1224         intel_ring_setup_status_page(ring);
1225         DRM_DEBUG_DRIVER("%s hws offset: 0x%08x\n",
1226                         ring->name, ring->status_page.gfx_addr);
1227
1228         return 0;
1229
1230 err_unpin:
1231         i915_gem_object_unpin(obj);
1232 err_unref:
1233         drm_gem_object_unreference(&obj->base);
1234 err:
1235         return ret;
1236 }
1237
1238 static int init_phys_hws_pga(struct intel_ring_buffer *ring)
1239 {
1240         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1241         u32 addr;
1242
1243         if (!dev_priv->status_page_dmah) {
1244                 dev_priv->status_page_dmah =
1245                         drm_pci_alloc(ring->dev, PAGE_SIZE, PAGE_SIZE);
1246                 if (!dev_priv->status_page_dmah)
1247                         return -ENOMEM;
1248         }
1249
1250         addr = dev_priv->status_page_dmah->busaddr;
1251         if (INTEL_INFO(ring->dev)->gen >= 4)
1252                 addr |= (dev_priv->status_page_dmah->busaddr >> 28) & 0xf0;
1253         I915_WRITE(HWS_PGA, addr);
1254
1255         ring->status_page.page_addr = dev_priv->status_page_dmah->vaddr;
1256         memset(ring->status_page.page_addr, 0, PAGE_SIZE);
1257
1258         return 0;
1259 }
1260
1261 static int intel_init_ring_buffer(struct drm_device *dev,
1262                                   struct intel_ring_buffer *ring)
1263 {
1264         struct drm_i915_gem_object *obj;
1265         struct drm_i915_private *dev_priv = dev->dev_private;
1266         int ret;
1267
1268         ring->dev = dev;
1269         INIT_LIST_HEAD(&ring->active_list);
1270         INIT_LIST_HEAD(&ring->request_list);
1271         ring->size = 32 * PAGE_SIZE;
1272         memset(ring->sync_seqno, 0, sizeof(ring->sync_seqno));
1273
1274         init_waitqueue_head(&ring->irq_queue);
1275
1276         if (I915_NEED_GFX_HWS(dev)) {
1277                 ret = init_status_page(ring);
1278                 if (ret)
1279                         return ret;
1280         } else {
1281                 BUG_ON(ring->id != RCS);
1282                 ret = init_phys_hws_pga(ring);
1283                 if (ret)
1284                         return ret;
1285         }
1286
1287         obj = NULL;
1288         if (!HAS_LLC(dev))
1289                 obj = i915_gem_object_create_stolen(dev, ring->size);
1290         if (obj == NULL)
1291                 obj = i915_gem_alloc_object(dev, ring->size);
1292         if (obj == NULL) {
1293                 DRM_ERROR("Failed to allocate ringbuffer\n");
1294                 ret = -ENOMEM;
1295                 goto err_hws;
1296         }
1297
1298         ring->obj = obj;
1299
1300         ret = i915_gem_object_pin(obj, PAGE_SIZE, true, false);
1301         if (ret)
1302                 goto err_unref;
1303
1304         ret = i915_gem_object_set_to_gtt_domain(obj, true);
1305         if (ret)
1306                 goto err_unpin;
1307
1308         ring->virtual_start =
1309                 ioremap_wc(dev_priv->gtt.mappable_base + obj->gtt_offset,
1310                            ring->size);
1311         if (ring->virtual_start == NULL) {
1312                 DRM_ERROR("Failed to map ringbuffer.\n");
1313                 ret = -EINVAL;
1314                 goto err_unpin;
1315         }
1316
1317         ret = ring->init(ring);
1318         if (ret)
1319                 goto err_unmap;
1320
1321         /* Workaround an erratum on the i830 which causes a hang if
1322          * the TAIL pointer points to within the last 2 cachelines
1323          * of the buffer.
1324          */
1325         ring->effective_size = ring->size;
1326         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1327                 ring->effective_size -= 128;
1328
1329         return 0;
1330
1331 err_unmap:
1332         iounmap(ring->virtual_start);
1333 err_unpin:
1334         i915_gem_object_unpin(obj);
1335 err_unref:
1336         drm_gem_object_unreference(&obj->base);
1337         ring->obj = NULL;
1338 err_hws:
1339         cleanup_status_page(ring);
1340         return ret;
1341 }
1342
1343 void intel_cleanup_ring_buffer(struct intel_ring_buffer *ring)
1344 {
1345         struct drm_i915_private *dev_priv;
1346         int ret;
1347
1348         if (ring->obj == NULL)
1349                 return;
1350
1351         /* Disable the ring buffer. The ring must be idle at this point */
1352         dev_priv = ring->dev->dev_private;
1353         ret = intel_ring_idle(ring);
1354         if (ret)
1355                 DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n",
1356                           ring->name, ret);
1357
1358         I915_WRITE_CTL(ring, 0);
1359
1360         iounmap(ring->virtual_start);
1361
1362         i915_gem_object_unpin(ring->obj);
1363         drm_gem_object_unreference(&ring->obj->base);
1364         ring->obj = NULL;
1365
1366         if (ring->cleanup)
1367                 ring->cleanup(ring);
1368
1369         cleanup_status_page(ring);
1370 }
1371
1372 static int intel_ring_wait_seqno(struct intel_ring_buffer *ring, u32 seqno)
1373 {
1374         int ret;
1375
1376         ret = i915_wait_seqno(ring, seqno);
1377         if (!ret)
1378                 i915_gem_retire_requests_ring(ring);
1379
1380         return ret;
1381 }
1382
1383 static int intel_ring_wait_request(struct intel_ring_buffer *ring, int n)
1384 {
1385         struct drm_i915_gem_request *request;
1386         u32 seqno = 0;
1387         int ret;
1388
1389         i915_gem_retire_requests_ring(ring);
1390
1391         if (ring->last_retired_head != -1) {
1392                 ring->head = ring->last_retired_head;
1393                 ring->last_retired_head = -1;
1394                 ring->space = ring_space(ring);
1395                 if (ring->space >= n)
1396                         return 0;
1397         }
1398
1399         list_for_each_entry(request, &ring->request_list, list) {
1400                 int space;
1401
1402                 if (request->tail == -1)
1403                         continue;
1404
1405                 space = request->tail - (ring->tail + I915_RING_FREE_SPACE);
1406                 if (space < 0)
1407                         space += ring->size;
1408                 if (space >= n) {
1409                         seqno = request->seqno;
1410                         break;
1411                 }
1412
1413                 /* Consume this request in case we need more space than
1414                  * is available and so need to prevent a race between
1415                  * updating last_retired_head and direct reads of
1416                  * I915_RING_HEAD. It also provides a nice sanity check.
1417                  */
1418                 request->tail = -1;
1419         }
1420
1421         if (seqno == 0)
1422                 return -ENOSPC;
1423
1424         ret = intel_ring_wait_seqno(ring, seqno);
1425         if (ret)
1426                 return ret;
1427
1428         if (WARN_ON(ring->last_retired_head == -1))
1429                 return -ENOSPC;
1430
1431         ring->head = ring->last_retired_head;
1432         ring->last_retired_head = -1;
1433         ring->space = ring_space(ring);
1434         if (WARN_ON(ring->space < n))
1435                 return -ENOSPC;
1436
1437         return 0;
1438 }
1439
1440 static int ring_wait_for_space(struct intel_ring_buffer *ring, int n)
1441 {
1442         struct drm_device *dev = ring->dev;
1443         struct drm_i915_private *dev_priv = dev->dev_private;
1444         unsigned long end;
1445         int ret;
1446
1447         ret = intel_ring_wait_request(ring, n);
1448         if (ret != -ENOSPC)
1449                 return ret;
1450
1451         trace_i915_ring_wait_begin(ring);
1452         /* With GEM the hangcheck timer should kick us out of the loop,
1453          * leaving it early runs the risk of corrupting GEM state (due
1454          * to running on almost untested codepaths). But on resume
1455          * timers don't work yet, so prevent a complete hang in that
1456          * case by choosing an insanely large timeout. */
1457         end = jiffies + 60 * HZ;
1458
1459         do {
1460                 ring->head = I915_READ_HEAD(ring);
1461                 ring->space = ring_space(ring);
1462                 if (ring->space >= n) {
1463                         trace_i915_ring_wait_end(ring);
1464                         return 0;
1465                 }
1466
1467                 if (dev->primary->master) {
1468                         struct drm_i915_master_private *master_priv = dev->primary->master->driver_priv;
1469                         if (master_priv->sarea_priv)
1470                                 master_priv->sarea_priv->perf_boxes |= I915_BOX_WAIT;
1471                 }
1472
1473                 msleep(1);
1474
1475                 ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1476                                            dev_priv->mm.interruptible);
1477                 if (ret)
1478                         return ret;
1479         } while (!time_after(jiffies, end));
1480         trace_i915_ring_wait_end(ring);
1481         return -EBUSY;
1482 }
1483
1484 static int intel_wrap_ring_buffer(struct intel_ring_buffer *ring)
1485 {
1486         uint32_t __iomem *virt;
1487         int rem = ring->size - ring->tail;
1488
1489         if (ring->space < rem) {
1490                 int ret = ring_wait_for_space(ring, rem);
1491                 if (ret)
1492                         return ret;
1493         }
1494
1495         virt = ring->virtual_start + ring->tail;
1496         rem /= 4;
1497         while (rem--)
1498                 iowrite32(MI_NOOP, virt++);
1499
1500         ring->tail = 0;
1501         ring->space = ring_space(ring);
1502
1503         return 0;
1504 }
1505
1506 int intel_ring_idle(struct intel_ring_buffer *ring)
1507 {
1508         u32 seqno;
1509         int ret;
1510
1511         /* We need to add any requests required to flush the objects and ring */
1512         if (ring->outstanding_lazy_request) {
1513                 ret = i915_add_request(ring, NULL, NULL);
1514                 if (ret)
1515                         return ret;
1516         }
1517
1518         /* Wait upon the last request to be completed */
1519         if (list_empty(&ring->request_list))
1520                 return 0;
1521
1522         seqno = list_entry(ring->request_list.prev,
1523                            struct drm_i915_gem_request,
1524                            list)->seqno;
1525
1526         return i915_wait_seqno(ring, seqno);
1527 }
1528
1529 static int
1530 intel_ring_alloc_seqno(struct intel_ring_buffer *ring)
1531 {
1532         if (ring->outstanding_lazy_request)
1533                 return 0;
1534
1535         return i915_gem_get_seqno(ring->dev, &ring->outstanding_lazy_request);
1536 }
1537
1538 static int __intel_ring_begin(struct intel_ring_buffer *ring,
1539                               int bytes)
1540 {
1541         int ret;
1542
1543         if (unlikely(ring->tail + bytes > ring->effective_size)) {
1544                 ret = intel_wrap_ring_buffer(ring);
1545                 if (unlikely(ret))
1546                         return ret;
1547         }
1548
1549         if (unlikely(ring->space < bytes)) {
1550                 ret = ring_wait_for_space(ring, bytes);
1551                 if (unlikely(ret))
1552                         return ret;
1553         }
1554
1555         ring->space -= bytes;
1556         return 0;
1557 }
1558
1559 int intel_ring_begin(struct intel_ring_buffer *ring,
1560                      int num_dwords)
1561 {
1562         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1563         int ret;
1564
1565         ret = i915_gem_check_wedge(&dev_priv->gpu_error,
1566                                    dev_priv->mm.interruptible);
1567         if (ret)
1568                 return ret;
1569
1570         /* Preallocate the olr before touching the ring */
1571         ret = intel_ring_alloc_seqno(ring);
1572         if (ret)
1573                 return ret;
1574
1575         return __intel_ring_begin(ring, num_dwords * sizeof(uint32_t));
1576 }
1577
1578 void intel_ring_init_seqno(struct intel_ring_buffer *ring, u32 seqno)
1579 {
1580         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1581
1582         BUG_ON(ring->outstanding_lazy_request);
1583
1584         if (INTEL_INFO(ring->dev)->gen >= 6) {
1585                 I915_WRITE(RING_SYNC_0(ring->mmio_base), 0);
1586                 I915_WRITE(RING_SYNC_1(ring->mmio_base), 0);
1587         }
1588
1589         ring->set_seqno(ring, seqno);
1590         ring->hangcheck.seqno = seqno;
1591 }
1592
1593 void intel_ring_advance(struct intel_ring_buffer *ring)
1594 {
1595         struct drm_i915_private *dev_priv = ring->dev->dev_private;
1596
1597         ring->tail &= ring->size - 1;
1598         if (dev_priv->gpu_error.stop_rings & intel_ring_flag(ring))
1599                 return;
1600         ring->write_tail(ring, ring->tail);
1601 }
1602
1603
1604 static void gen6_bsd_ring_write_tail(struct intel_ring_buffer *ring,
1605                                      u32 value)
1606 {
1607         drm_i915_private_t *dev_priv = ring->dev->dev_private;
1608
1609        /* Every tail move must follow the sequence below */
1610
1611         /* Disable notification that the ring is IDLE. The GT
1612          * will then assume that it is busy and bring it out of rc6.
1613          */
1614         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1615                    _MASKED_BIT_ENABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1616
1617         /* Clear the context id. Here be magic! */
1618         I915_WRITE64(GEN6_BSD_RNCID, 0x0);
1619
1620         /* Wait for the ring not to be idle, i.e. for it to wake up. */
1621         if (wait_for((I915_READ(GEN6_BSD_SLEEP_PSMI_CONTROL) &
1622                       GEN6_BSD_SLEEP_INDICATOR) == 0,
1623                      50))
1624                 DRM_ERROR("timed out waiting for the BSD ring to wake up\n");
1625
1626         /* Now that the ring is fully powered up, update the tail */
1627         I915_WRITE_TAIL(ring, value);
1628         POSTING_READ(RING_TAIL(ring->mmio_base));
1629
1630         /* Let the ring send IDLE messages to the GT again,
1631          * and so let it sleep to conserve power when idle.
1632          */
1633         I915_WRITE(GEN6_BSD_SLEEP_PSMI_CONTROL,
1634                    _MASKED_BIT_DISABLE(GEN6_BSD_SLEEP_MSG_DISABLE));
1635 }
1636
1637 static int gen6_bsd_ring_flush(struct intel_ring_buffer *ring,
1638                                u32 invalidate, u32 flush)
1639 {
1640         uint32_t cmd;
1641         int ret;
1642
1643         ret = intel_ring_begin(ring, 4);
1644         if (ret)
1645                 return ret;
1646
1647         cmd = MI_FLUSH_DW;
1648         /*
1649          * Bspec vol 1c.5 - video engine command streamer:
1650          * "If ENABLED, all TLBs will be invalidated once the flush
1651          * operation is complete. This bit is only valid when the
1652          * Post-Sync Operation field is a value of 1h or 3h."
1653          */
1654         if (invalidate & I915_GEM_GPU_DOMAINS)
1655                 cmd |= MI_INVALIDATE_TLB | MI_INVALIDATE_BSD |
1656                         MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW;
1657         intel_ring_emit(ring, cmd);
1658         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1659         intel_ring_emit(ring, 0);
1660         intel_ring_emit(ring, MI_NOOP);
1661         intel_ring_advance(ring);
1662         return 0;
1663 }
1664
1665 static int
1666 hsw_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1667                               u32 offset, u32 len,
1668                               unsigned flags)
1669 {
1670         int ret;
1671
1672         ret = intel_ring_begin(ring, 2);
1673         if (ret)
1674                 return ret;
1675
1676         intel_ring_emit(ring,
1677                         MI_BATCH_BUFFER_START | MI_BATCH_PPGTT_HSW |
1678                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_HSW));
1679         /* bit0-7 is the length on GEN6+ */
1680         intel_ring_emit(ring, offset);
1681         intel_ring_advance(ring);
1682
1683         return 0;
1684 }
1685
1686 static int
1687 gen6_ring_dispatch_execbuffer(struct intel_ring_buffer *ring,
1688                               u32 offset, u32 len,
1689                               unsigned flags)
1690 {
1691         int ret;
1692
1693         ret = intel_ring_begin(ring, 2);
1694         if (ret)
1695                 return ret;
1696
1697         intel_ring_emit(ring,
1698                         MI_BATCH_BUFFER_START |
1699                         (flags & I915_DISPATCH_SECURE ? 0 : MI_BATCH_NON_SECURE_I965));
1700         /* bit0-7 is the length on GEN6+ */
1701         intel_ring_emit(ring, offset);
1702         intel_ring_advance(ring);
1703
1704         return 0;
1705 }
1706
1707 /* Blitter support (SandyBridge+) */
1708
1709 static int gen6_ring_flush(struct intel_ring_buffer *ring,
1710                            u32 invalidate, u32 flush)
1711 {
1712         struct drm_device *dev = ring->dev;
1713         uint32_t cmd;
1714         int ret;
1715
1716         ret = intel_ring_begin(ring, 4);
1717         if (ret)
1718                 return ret;
1719
1720         cmd = MI_FLUSH_DW;
1721         /*
1722          * Bspec vol 1c.3 - blitter engine command streamer:
1723          * "If ENABLED, all TLBs will be invalidated once the flush
1724          * operation is complete. This bit is only valid when the
1725          * Post-Sync Operation field is a value of 1h or 3h."
1726          */
1727         if (invalidate & I915_GEM_DOMAIN_RENDER)
1728                 cmd |= MI_INVALIDATE_TLB | MI_FLUSH_DW_STORE_INDEX |
1729                         MI_FLUSH_DW_OP_STOREDW;
1730         intel_ring_emit(ring, cmd);
1731         intel_ring_emit(ring, I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT);
1732         intel_ring_emit(ring, 0);
1733         intel_ring_emit(ring, MI_NOOP);
1734         intel_ring_advance(ring);
1735
1736         if (IS_GEN7(dev) && flush)
1737                 return gen7_ring_fbc_flush(ring, FBC_REND_CACHE_CLEAN);
1738
1739         return 0;
1740 }
1741
1742 int intel_init_render_ring_buffer(struct drm_device *dev)
1743 {
1744         drm_i915_private_t *dev_priv = dev->dev_private;
1745         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1746
1747         ring->name = "render ring";
1748         ring->id = RCS;
1749         ring->mmio_base = RENDER_RING_BASE;
1750
1751         if (INTEL_INFO(dev)->gen >= 6) {
1752                 ring->add_request = gen6_add_request;
1753                 ring->flush = gen7_render_ring_flush;
1754                 if (INTEL_INFO(dev)->gen == 6)
1755                         ring->flush = gen6_render_ring_flush;
1756                 ring->irq_get = gen6_ring_get_irq;
1757                 ring->irq_put = gen6_ring_put_irq;
1758                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT;
1759                 ring->get_seqno = gen6_ring_get_seqno;
1760                 ring->set_seqno = ring_set_seqno;
1761                 ring->sync_to = gen6_ring_sync;
1762                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_INVALID;
1763                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_RV;
1764                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_RB;
1765                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_RVE;
1766                 ring->signal_mbox[RCS] = GEN6_NOSYNC;
1767                 ring->signal_mbox[VCS] = GEN6_VRSYNC;
1768                 ring->signal_mbox[BCS] = GEN6_BRSYNC;
1769                 ring->signal_mbox[VECS] = GEN6_VERSYNC;
1770         } else if (IS_GEN5(dev)) {
1771                 ring->add_request = pc_render_add_request;
1772                 ring->flush = gen4_render_ring_flush;
1773                 ring->get_seqno = pc_render_get_seqno;
1774                 ring->set_seqno = pc_render_set_seqno;
1775                 ring->irq_get = gen5_ring_get_irq;
1776                 ring->irq_put = gen5_ring_put_irq;
1777                 ring->irq_enable_mask = GT_RENDER_USER_INTERRUPT |
1778                                         GT_RENDER_PIPECTL_NOTIFY_INTERRUPT;
1779         } else {
1780                 ring->add_request = i9xx_add_request;
1781                 if (INTEL_INFO(dev)->gen < 4)
1782                         ring->flush = gen2_render_ring_flush;
1783                 else
1784                         ring->flush = gen4_render_ring_flush;
1785                 ring->get_seqno = ring_get_seqno;
1786                 ring->set_seqno = ring_set_seqno;
1787                 if (IS_GEN2(dev)) {
1788                         ring->irq_get = i8xx_ring_get_irq;
1789                         ring->irq_put = i8xx_ring_put_irq;
1790                 } else {
1791                         ring->irq_get = i9xx_ring_get_irq;
1792                         ring->irq_put = i9xx_ring_put_irq;
1793                 }
1794                 ring->irq_enable_mask = I915_USER_INTERRUPT;
1795         }
1796         ring->write_tail = ring_write_tail;
1797         if (IS_HASWELL(dev))
1798                 ring->dispatch_execbuffer = hsw_ring_dispatch_execbuffer;
1799         else if (INTEL_INFO(dev)->gen >= 6)
1800                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1801         else if (INTEL_INFO(dev)->gen >= 4)
1802                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1803         else if (IS_I830(dev) || IS_845G(dev))
1804                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1805         else
1806                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1807         ring->init = init_render_ring;
1808         ring->cleanup = render_ring_cleanup;
1809
1810         /* Workaround batchbuffer to combat CS tlb bug. */
1811         if (HAS_BROKEN_CS_TLB(dev)) {
1812                 struct drm_i915_gem_object *obj;
1813                 int ret;
1814
1815                 obj = i915_gem_alloc_object(dev, I830_BATCH_LIMIT);
1816                 if (obj == NULL) {
1817                         DRM_ERROR("Failed to allocate batch bo\n");
1818                         return -ENOMEM;
1819                 }
1820
1821                 ret = i915_gem_object_pin(obj, 0, true, false);
1822                 if (ret != 0) {
1823                         drm_gem_object_unreference(&obj->base);
1824                         DRM_ERROR("Failed to ping batch bo\n");
1825                         return ret;
1826                 }
1827
1828                 ring->private = obj;
1829         }
1830
1831         return intel_init_ring_buffer(dev, ring);
1832 }
1833
1834 int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size)
1835 {
1836         drm_i915_private_t *dev_priv = dev->dev_private;
1837         struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
1838         int ret;
1839
1840         ring->name = "render ring";
1841         ring->id = RCS;
1842         ring->mmio_base = RENDER_RING_BASE;
1843
1844         if (INTEL_INFO(dev)->gen >= 6) {
1845                 /* non-kms not supported on gen6+ */
1846                 return -ENODEV;
1847         }
1848
1849         /* Note: gem is not supported on gen5/ilk without kms (the corresponding
1850          * gem_init ioctl returns with -ENODEV). Hence we do not need to set up
1851          * the special gen5 functions. */
1852         ring->add_request = i9xx_add_request;
1853         if (INTEL_INFO(dev)->gen < 4)
1854                 ring->flush = gen2_render_ring_flush;
1855         else
1856                 ring->flush = gen4_render_ring_flush;
1857         ring->get_seqno = ring_get_seqno;
1858         ring->set_seqno = ring_set_seqno;
1859         if (IS_GEN2(dev)) {
1860                 ring->irq_get = i8xx_ring_get_irq;
1861                 ring->irq_put = i8xx_ring_put_irq;
1862         } else {
1863                 ring->irq_get = i9xx_ring_get_irq;
1864                 ring->irq_put = i9xx_ring_put_irq;
1865         }
1866         ring->irq_enable_mask = I915_USER_INTERRUPT;
1867         ring->write_tail = ring_write_tail;
1868         if (INTEL_INFO(dev)->gen >= 4)
1869                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1870         else if (IS_I830(dev) || IS_845G(dev))
1871                 ring->dispatch_execbuffer = i830_dispatch_execbuffer;
1872         else
1873                 ring->dispatch_execbuffer = i915_dispatch_execbuffer;
1874         ring->init = init_render_ring;
1875         ring->cleanup = render_ring_cleanup;
1876
1877         ring->dev = dev;
1878         INIT_LIST_HEAD(&ring->active_list);
1879         INIT_LIST_HEAD(&ring->request_list);
1880
1881         ring->size = size;
1882         ring->effective_size = ring->size;
1883         if (IS_I830(ring->dev) || IS_845G(ring->dev))
1884                 ring->effective_size -= 128;
1885
1886         ring->virtual_start = ioremap_wc(start, size);
1887         if (ring->virtual_start == NULL) {
1888                 DRM_ERROR("can not ioremap virtual address for"
1889                           " ring buffer\n");
1890                 return -ENOMEM;
1891         }
1892
1893         if (!I915_NEED_GFX_HWS(dev)) {
1894                 ret = init_phys_hws_pga(ring);
1895                 if (ret)
1896                         return ret;
1897         }
1898
1899         return 0;
1900 }
1901
1902 int intel_init_bsd_ring_buffer(struct drm_device *dev)
1903 {
1904         drm_i915_private_t *dev_priv = dev->dev_private;
1905         struct intel_ring_buffer *ring = &dev_priv->ring[VCS];
1906
1907         ring->name = "bsd ring";
1908         ring->id = VCS;
1909
1910         ring->write_tail = ring_write_tail;
1911         if (IS_GEN6(dev) || IS_GEN7(dev)) {
1912                 ring->mmio_base = GEN6_BSD_RING_BASE;
1913                 /* gen6 bsd needs a special wa for tail updates */
1914                 if (IS_GEN6(dev))
1915                         ring->write_tail = gen6_bsd_ring_write_tail;
1916                 ring->flush = gen6_bsd_ring_flush;
1917                 ring->add_request = gen6_add_request;
1918                 ring->get_seqno = gen6_ring_get_seqno;
1919                 ring->set_seqno = ring_set_seqno;
1920                 ring->irq_enable_mask = GT_BSD_USER_INTERRUPT;
1921                 ring->irq_get = gen6_ring_get_irq;
1922                 ring->irq_put = gen6_ring_put_irq;
1923                 ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1924                 ring->sync_to = gen6_ring_sync;
1925                 ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VR;
1926                 ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_INVALID;
1927                 ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VB;
1928                 ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_VVE;
1929                 ring->signal_mbox[RCS] = GEN6_RVSYNC;
1930                 ring->signal_mbox[VCS] = GEN6_NOSYNC;
1931                 ring->signal_mbox[BCS] = GEN6_BVSYNC;
1932                 ring->signal_mbox[VECS] = GEN6_VEVSYNC;
1933         } else {
1934                 ring->mmio_base = BSD_RING_BASE;
1935                 ring->flush = bsd_ring_flush;
1936                 ring->add_request = i9xx_add_request;
1937                 ring->get_seqno = ring_get_seqno;
1938                 ring->set_seqno = ring_set_seqno;
1939                 if (IS_GEN5(dev)) {
1940                         ring->irq_enable_mask = ILK_BSD_USER_INTERRUPT;
1941                         ring->irq_get = gen5_ring_get_irq;
1942                         ring->irq_put = gen5_ring_put_irq;
1943                 } else {
1944                         ring->irq_enable_mask = I915_BSD_USER_INTERRUPT;
1945                         ring->irq_get = i9xx_ring_get_irq;
1946                         ring->irq_put = i9xx_ring_put_irq;
1947                 }
1948                 ring->dispatch_execbuffer = i965_dispatch_execbuffer;
1949         }
1950         ring->init = init_ring_common;
1951
1952         return intel_init_ring_buffer(dev, ring);
1953 }
1954
1955 int intel_init_blt_ring_buffer(struct drm_device *dev)
1956 {
1957         drm_i915_private_t *dev_priv = dev->dev_private;
1958         struct intel_ring_buffer *ring = &dev_priv->ring[BCS];
1959
1960         ring->name = "blitter ring";
1961         ring->id = BCS;
1962
1963         ring->mmio_base = BLT_RING_BASE;
1964         ring->write_tail = ring_write_tail;
1965         ring->flush = gen6_ring_flush;
1966         ring->add_request = gen6_add_request;
1967         ring->get_seqno = gen6_ring_get_seqno;
1968         ring->set_seqno = ring_set_seqno;
1969         ring->irq_enable_mask = GT_BLT_USER_INTERRUPT;
1970         ring->irq_get = gen6_ring_get_irq;
1971         ring->irq_put = gen6_ring_put_irq;
1972         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
1973         ring->sync_to = gen6_ring_sync;
1974         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_BR;
1975         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_BV;
1976         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_INVALID;
1977         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_BVE;
1978         ring->signal_mbox[RCS] = GEN6_RBSYNC;
1979         ring->signal_mbox[VCS] = GEN6_VBSYNC;
1980         ring->signal_mbox[BCS] = GEN6_NOSYNC;
1981         ring->signal_mbox[VECS] = GEN6_VEBSYNC;
1982         ring->init = init_ring_common;
1983
1984         return intel_init_ring_buffer(dev, ring);
1985 }
1986
1987 int intel_init_vebox_ring_buffer(struct drm_device *dev)
1988 {
1989         drm_i915_private_t *dev_priv = dev->dev_private;
1990         struct intel_ring_buffer *ring = &dev_priv->ring[VECS];
1991
1992         ring->name = "video enhancement ring";
1993         ring->id = VECS;
1994
1995         ring->mmio_base = VEBOX_RING_BASE;
1996         ring->write_tail = ring_write_tail;
1997         ring->flush = gen6_ring_flush;
1998         ring->add_request = gen6_add_request;
1999         ring->get_seqno = gen6_ring_get_seqno;
2000         ring->set_seqno = ring_set_seqno;
2001         ring->irq_enable_mask = PM_VEBOX_USER_INTERRUPT |
2002                 PM_VEBOX_CS_ERROR_INTERRUPT;
2003         ring->irq_get = hsw_vebox_get_irq;
2004         ring->irq_put = hsw_vebox_put_irq;
2005         ring->dispatch_execbuffer = gen6_ring_dispatch_execbuffer;
2006         ring->sync_to = gen6_ring_sync;
2007         ring->semaphore_register[RCS] = MI_SEMAPHORE_SYNC_VER;
2008         ring->semaphore_register[VCS] = MI_SEMAPHORE_SYNC_VEV;
2009         ring->semaphore_register[BCS] = MI_SEMAPHORE_SYNC_VEB;
2010         ring->semaphore_register[VECS] = MI_SEMAPHORE_SYNC_INVALID;
2011         ring->signal_mbox[RCS] = GEN6_RVESYNC;
2012         ring->signal_mbox[VCS] = GEN6_VVESYNC;
2013         ring->signal_mbox[BCS] = GEN6_BVESYNC;
2014         ring->signal_mbox[VECS] = GEN6_NOSYNC;
2015         ring->init = init_ring_common;
2016
2017         return intel_init_ring_buffer(dev, ring);
2018 }
2019
2020 int
2021 intel_ring_flush_all_caches(struct intel_ring_buffer *ring)
2022 {
2023         int ret;
2024
2025         if (!ring->gpu_caches_dirty)
2026                 return 0;
2027
2028         ret = ring->flush(ring, 0, I915_GEM_GPU_DOMAINS);
2029         if (ret)
2030                 return ret;
2031
2032         trace_i915_gem_ring_flush(ring, 0, I915_GEM_GPU_DOMAINS);
2033
2034         ring->gpu_caches_dirty = false;
2035         return 0;
2036 }
2037
2038 int
2039 intel_ring_invalidate_all_caches(struct intel_ring_buffer *ring)
2040 {
2041         uint32_t flush_domains;
2042         int ret;
2043
2044         flush_domains = 0;
2045         if (ring->gpu_caches_dirty)
2046                 flush_domains = I915_GEM_GPU_DOMAINS;
2047
2048         ret = ring->flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2049         if (ret)
2050                 return ret;
2051
2052         trace_i915_gem_ring_flush(ring, I915_GEM_GPU_DOMAINS, flush_domains);
2053
2054         ring->gpu_caches_dirty = false;
2055         return 0;
2056 }