drivers/firewire/ohci.c

   1 /*
   2  * Driver for OHCI 1394 controllers
   3  *
   4  * Copyright (C) 2003-2006 Kristian Hoegsberg <krh@bitplanet.net>
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software Foundation,
  18  * Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
  19  */
  20
  21 #include <linux/bitops.h>
  22 #include <linux/bug.h>
  23 #include <linux/compiler.h>
  24 #include <linux/delay.h>
  25 #include <linux/device.h>
  26 #include <linux/dma-mapping.h>
  27 #include <linux/firewire.h>
  28 #include <linux/firewire-constants.h>
  29 #include <linux/init.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/io.h>
  32 #include <linux/kernel.h>
  33 #include <linux/list.h>
  34 #include <linux/mm.h>
  35 #include <linux/module.h>
  36 #include <linux/moduleparam.h>
  37 #include <linux/mutex.h>
  38 #include <linux/pci.h>
  39 #include <linux/pci_ids.h>
  40 #include <linux/slab.h>
  41 #include <linux/spinlock.h>
  42 #include <linux/string.h>
  43 #include <linux/time.h>
  44 #include <linux/vmalloc.h>
  45 #include <linux/workqueue.h>
  46
  47 #include <asm/byteorder.h>
  48 #include <asm/page.h>
  49 #include <asm/system.h>
  50
  51 #ifdef CONFIG_PPC_PMAC
  52 #include <asm/pmac_feature.h>
  53 #endif
  54
  55 #include "core.h"
  56 #include "ohci.h"
  57
  58 #define DESCRIPTOR_OUTPUT_MORE          0
  59 #define DESCRIPTOR_OUTPUT_LAST          (1 << 12)
  60 #define DESCRIPTOR_INPUT_MORE           (2 << 12)
  61 #define DESCRIPTOR_INPUT_LAST           (3 << 12)
  62 #define DESCRIPTOR_STATUS               (1 << 11)
  63 #define DESCRIPTOR_KEY_IMMEDIATE        (2 << 8)
  64 #define DESCRIPTOR_PING                 (1 << 7)
  65 #define DESCRIPTOR_YY                   (1 << 6)
  66 #define DESCRIPTOR_NO_IRQ               (0 << 4)
  67 #define DESCRIPTOR_IRQ_ERROR            (1 << 4)
  68 #define DESCRIPTOR_IRQ_ALWAYS           (3 << 4)
  69 #define DESCRIPTOR_BRANCH_ALWAYS        (3 << 2)
  70 #define DESCRIPTOR_WAIT                 (3 << 0)
  71
  72 struct descriptor {
  73         __le16 req_count;
  74         __le16 control;
  75         __le32 data_address;
  76         __le32 branch_address;
  77         __le16 res_count;
  78         __le16 transfer_status;
  79 } __attribute__((aligned(16)));
  80
  81 #define CONTROL_SET(regs)       (regs)
  82 #define CONTROL_CLEAR(regs)     ((regs) + 4)
  83 #define COMMAND_PTR(regs)       ((regs) + 12)
  84 #define CONTEXT_MATCH(regs)     ((regs) + 16)
  85
  86 #define AR_BUFFER_SIZE  (32*1024)
  87 #define AR_BUFFERS_MIN  DIV_ROUND_UP(AR_BUFFER_SIZE, PAGE_SIZE)
  88 /* we need at least two pages for proper list management */
  89 #define AR_BUFFERS      (AR_BUFFERS_MIN >= 2 ? AR_BUFFERS_MIN : 2)
  90
  91 #define MAX_ASYNC_PAYLOAD       4096
  92 #define MAX_AR_PACKET_SIZE      (16 + MAX_ASYNC_PAYLOAD + 4)
  93 #define AR_WRAPAROUND_PAGES     DIV_ROUND_UP(MAX_AR_PACKET_SIZE, PAGE_SIZE)
  94
  95 struct ar_context {
  96         struct fw_ohci *ohci;
  97         struct page *pages[AR_BUFFERS];
  98         void *buffer;
  99         struct descriptor *descriptors;
 100         dma_addr_t descriptors_bus;
 101         void *pointer;
 102         unsigned int last_buffer_index;
 103         u32 regs;
 104         struct tasklet_struct tasklet;
 105 };
 106
 107 struct context;
 108
 109 typedef int (*descriptor_callback_t)(struct context *ctx,
 110                                      struct descriptor *d,
 111                                      struct descriptor *last);
 112
 113 /*
 114  * A buffer that contains a block of DMA-able coherent memory used for
 115  * storing a portion of a DMA descriptor program.
 116  */
 117 struct descriptor_buffer {
 118         struct list_head list;
 119         dma_addr_t buffer_bus;
 120         size_t buffer_size;
 121         size_t used;
 122         struct descriptor buffer[0];
 123 };
 124
 125 struct context {
 126         struct fw_ohci *ohci;
 127         u32 regs;
 128         int total_allocation;
 129         u32 current_bus;
 130         bool running;
 131         bool flushing;
 132
 133         /*
 134          * List of page-sized buffers for storing DMA descriptors.
 135          * Head of list contains buffers in use and tail of list contains
 136          * free buffers.
 137          */
 138         struct list_head buffer_list;
 139
 140         /*
 141          * Pointer to a buffer inside buffer_list that contains the tail
 142          * end of the current DMA program.
 143          */
 144         struct descriptor_buffer *buffer_tail;
 145
 146         /*
 147          * The descriptor containing the branch address of the first
 148          * descriptor that has not yet been filled by the device.
 149          */
 150         struct descriptor *last;
 151
 152         /*
 153          * The last descriptor in the DMA program.  It contains the branch
 154          * address that must be updated upon appending a new descriptor.
 155          */
 156         struct descriptor *prev;
 157
 158         descriptor_callback_t callback;
 159
 160         struct tasklet_struct tasklet;
 161 };
 162
 163 #define IT_HEADER_SY(v)          ((v) <<  0)
 164 #define IT_HEADER_TCODE(v)       ((v) <<  4)
 165 #define IT_HEADER_CHANNEL(v)     ((v) <<  8)
 166 #define IT_HEADER_TAG(v)         ((v) << 14)
 167 #define IT_HEADER_SPEED(v)       ((v) << 16)
 168 #define IT_HEADER_DATA_LENGTH(v) ((v) << 16)
 169
 170 struct iso_context {
 171         struct fw_iso_context base;
 172         struct context context;
 173         void *header;
 174         size_t header_length;
 175         u16 last_timestamp;
 176         u8 sync;
 177         u8 tags;
 178 };
 179
 180 #define CONFIG_ROM_SIZE 1024
 181
 182 struct fw_ohci {
 183         struct fw_card card;
 184
 185         __iomem char *registers;
 186         int node_id;
 187         int generation;
 188         int request_generation; /* for timestamping incoming requests */
 189         unsigned quirks;
 190         unsigned int pri_req_max;
 191         u32 bus_time;
 192         bool is_root;
 193         bool csr_state_setclear_abdicate;
 194         int n_ir;
 195         int n_it;
 196         /*
 197          * Spinlock for accessing fw_ohci data.  Never call out of
 198          * this driver with this lock held.
 199          */
 200         spinlock_t lock;
 201
 202         struct mutex phy_reg_mutex;
 203
 204         void *misc_buffer;
 205         dma_addr_t misc_buffer_bus;
 206
 207         struct ar_context ar_request_ctx;
 208         struct ar_context ar_response_ctx;
 209         struct context at_request_ctx;
 210         struct context at_response_ctx;
 211
 212         u32 it_context_support;
 213         u32 it_context_mask;     /* unoccupied IT contexts */
 214         struct iso_context *it_context_list;
 215         u64 ir_context_channels; /* unoccupied channels */
 216         u32 ir_context_support;
 217         u32 ir_context_mask;     /* unoccupied IR contexts */
 218         struct iso_context *ir_context_list;
 219         u64 mc_channels; /* channels in use by the multichannel IR context */
 220         bool mc_allocated;
 221
 222         __be32    *config_rom;
 223         dma_addr_t config_rom_bus;
 224         __be32    *next_config_rom;
 225         dma_addr_t next_config_rom_bus;
 226         __be32     next_header;
 227
 228         __le32    *self_id_cpu;
 229         dma_addr_t self_id_bus;
 230         struct work_struct bus_reset_work;
 231
 232         u32 self_id_buffer[512];
 233 };
 234
 235 static inline struct fw_ohci *fw_ohci(struct fw_card *card)
 236 {
 237         return container_of(card, struct fw_ohci, card);
 238 }
 239
 240 #define IT_CONTEXT_CYCLE_MATCH_ENABLE   0x80000000
 241 #define IR_CONTEXT_BUFFER_FILL          0x80000000
 242 #define IR_CONTEXT_ISOCH_HEADER         0x40000000
 243 #define IR_CONTEXT_CYCLE_MATCH_ENABLE   0x20000000
 244 #define IR_CONTEXT_MULTI_CHANNEL_MODE   0x10000000
 245 #define IR_CONTEXT_DUAL_BUFFER_MODE     0x08000000
 246
 247 #define CONTEXT_RUN     0x8000
 248 #define CONTEXT_WAKE    0x1000
 249 #define CONTEXT_DEAD    0x0800
 250 #define CONTEXT_ACTIVE  0x0400
 251
 252 #define OHCI1394_MAX_AT_REQ_RETRIES     0xf
 253 #define OHCI1394_MAX_AT_RESP_RETRIES    0x2
 254 #define OHCI1394_MAX_PHYS_RESP_RETRIES  0x8
 255
 256 #define OHCI1394_REGISTER_SIZE          0x800
 257 #define OHCI1394_PCI_HCI_Control        0x40
 258 #define SELF_ID_BUF_SIZE                0x800
 259 #define OHCI_TCODE_PHY_PACKET           0x0e
 260 #define OHCI_VERSION_1_1                0x010010
 261
 262 static char ohci_driver_name[] = KBUILD_MODNAME;
 263
 264 #define PCI_DEVICE_ID_AGERE_FW643       0x5901
 265 #define PCI_DEVICE_ID_JMICRON_JMB38X_FW 0x2380
 266 #define PCI_DEVICE_ID_TI_TSB12LV22      0x8009
 267 #define PCI_DEVICE_ID_TI_TSB12LV26      0x8020
 268 #define PCI_DEVICE_ID_TI_TSB82AA2       0x8025
 269 #define PCI_VENDOR_ID_PINNACLE_SYSTEMS  0x11bd
 270
 271 #define QUIRK_CYCLE_TIMER               1
 272 #define QUIRK_RESET_PACKET              2
 273 #define QUIRK_BE_HEADERS                4
 274 #define QUIRK_NO_1394A                  8
 275 #define QUIRK_NO_MSI                    16
 276 #define QUIRK_TI_SLLZ059                32
 277
 278 /* In case of multiple matches in ohci_quirks[], only the first one is used. */
 279 static const struct {
 280         unsigned short vendor, device, revision, flags;
 281 } ohci_quirks[] = {
 282         {PCI_VENDOR_ID_AL, PCI_ANY_ID, PCI_ANY_ID,
 283                 QUIRK_CYCLE_TIMER},
 284
 285         {PCI_VENDOR_ID_APPLE, PCI_DEVICE_ID_APPLE_UNI_N_FW, PCI_ANY_ID,
 286                 QUIRK_BE_HEADERS},
 287
 288         {PCI_VENDOR_ID_ATT, PCI_DEVICE_ID_AGERE_FW643, 6,
 289                 QUIRK_NO_MSI},
 290
 291         {PCI_VENDOR_ID_JMICRON, PCI_DEVICE_ID_JMICRON_JMB38X_FW, PCI_ANY_ID,
 292                 QUIRK_NO_MSI},
 293
 294         {PCI_VENDOR_ID_NEC, PCI_ANY_ID, PCI_ANY_ID,
 295                 QUIRK_CYCLE_TIMER},
 296
 297         {PCI_VENDOR_ID_O2, PCI_ANY_ID, PCI_ANY_ID,
 298                 QUIRK_NO_MSI},
 299
 300         {PCI_VENDOR_ID_RICOH, PCI_ANY_ID, PCI_ANY_ID,
 301                 QUIRK_CYCLE_TIMER},
 302
 303         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV22, PCI_ANY_ID,
 304                 QUIRK_CYCLE_TIMER | QUIRK_RESET_PACKET | QUIRK_NO_1394A},
 305
 306         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB12LV26, PCI_ANY_ID,
 307                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 308
 309         {PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TSB82AA2, PCI_ANY_ID,
 310                 QUIRK_RESET_PACKET | QUIRK_TI_SLLZ059},
 311
 312         {PCI_VENDOR_ID_TI, PCI_ANY_ID, PCI_ANY_ID,
 313                 QUIRK_RESET_PACKET},
 314
 315         {PCI_VENDOR_ID_VIA, PCI_ANY_ID, PCI_ANY_ID,
 316                 QUIRK_CYCLE_TIMER | QUIRK_NO_MSI},
 317 };
 318
 319 /* This overrides anything that was found in ohci_quirks[]. */
 320 static int param_quirks;
 321 module_param_named(quirks, param_quirks, int, 0644);
 322 MODULE_PARM_DESC(quirks, "Chip quirks (default = 0"
 323         ", nonatomic cycle timer = "    __stringify(QUIRK_CYCLE_TIMER)
 324         ", reset packet generation = "  __stringify(QUIRK_RESET_PACKET)
 325         ", AR/selfID endianess = "      __stringify(QUIRK_BE_HEADERS)
 326         ", no 1394a enhancements = "    __stringify(QUIRK_NO_1394A)
 327         ", disable MSI = "              __stringify(QUIRK_NO_MSI)
 328         ", TI SLLZ059 erratum = "       __stringify(QUIRK_TI_SLLZ059)
 329         ")");
 330
 331 #define OHCI_PARAM_DEBUG_AT_AR          1
 332 #define OHCI_PARAM_DEBUG_SELFIDS        2
 333 #define OHCI_PARAM_DEBUG_IRQS           4
 334 #define OHCI_PARAM_DEBUG_BUSRESETS      8 /* only effective before chip init */
 335
 336 static int param_debug;
 337 module_param_named(debug, param_debug, int, 0644);
 338 MODULE_PARM_DESC(debug, "Verbose logging (default = 0"
 339         ", AT/AR events = "     __stringify(OHCI_PARAM_DEBUG_AT_AR)
 340         ", self-IDs = "         __stringify(OHCI_PARAM_DEBUG_SELFIDS)
 341         ", IRQs = "             __stringify(OHCI_PARAM_DEBUG_IRQS)
 342         ", busReset events = "  __stringify(OHCI_PARAM_DEBUG_BUSRESETS)
 343         ", or a combination, or all = -1)");
 344
 345 static void log_irqs(struct fw_ohci *ohci, u32 evt)
 346 {
 347         if (likely(!(param_debug &
 348                         (OHCI_PARAM_DEBUG_IRQS | OHCI_PARAM_DEBUG_BUSRESETS))))
 349                 return;
 350
 351         if (!(param_debug & OHCI_PARAM_DEBUG_IRQS) &&
 352             !(evt & OHCI1394_busReset))
 353                 return;
 354
 355         dev_notice(ohci->card.device,
 356             "IRQ %08x%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s\n", evt,
 357             evt & OHCI1394_selfIDComplete       ? " selfID"             : "",
 358             evt & OHCI1394_RQPkt                ? " AR_req"             : "",
 359             evt & OHCI1394_RSPkt                ? " AR_resp"            : "",
 360             evt & OHCI1394_reqTxComplete        ? " AT_req"             : "",
 361             evt & OHCI1394_respTxComplete       ? " AT_resp"            : "",
 362             evt & OHCI1394_isochRx              ? " IR"                 : "",
 363             evt & OHCI1394_isochTx              ? " IT"                 : "",
 364             evt & OHCI1394_postedWriteErr       ? " postedWriteErr"     : "",
 365             evt & OHCI1394_cycleTooLong         ? " cycleTooLong"       : "",
 366             evt & OHCI1394_cycle64Seconds       ? " cycle64Seconds"     : "",
 367             evt & OHCI1394_cycleInconsistent    ? " cycleInconsistent"  : "",
 368             evt & OHCI1394_regAccessFail        ? " regAccessFail"      : "",
 369             evt & OHCI1394_unrecoverableError   ? " unrecoverableError" : "",
 370             evt & OHCI1394_busReset             ? " busReset"           : "",
 371             evt & ~(OHCI1394_selfIDComplete | OHCI1394_RQPkt |
 372                     OHCI1394_RSPkt | OHCI1394_reqTxComplete |
 373                     OHCI1394_respTxComplete | OHCI1394_isochRx |
 374                     OHCI1394_isochTx | OHCI1394_postedWriteErr |
 375                     OHCI1394_cycleTooLong | OHCI1394_cycle64Seconds |
 376                     OHCI1394_cycleInconsistent |
 377                     OHCI1394_regAccessFail | OHCI1394_busReset)
 378                                                 ? " ?"                  : "");
 379 }
 380
 381 static const char *speed[] = {
 382         [0] = "S100", [1] = "S200", [2] = "S400",    [3] = "beta",
 383 };
 384 static const char *power[] = {
 385         [0] = "+0W",  [1] = "+15W", [2] = "+30W",    [3] = "+45W",
 386         [4] = "-3W",  [5] = " ?W",  [6] = "-3..-6W", [7] = "-3..-10W",
 387 };
 388 static const char port[] = { '.', '-', 'p', 'c', };
 389
 390 static char _p(u32 *s, int shift)
 391 {
 392         return port[*s >> shift & 3];
 393 }
 394
 395 static void log_selfids(struct fw_ohci *ohci, int generation, int self_id_count)
 396 {
 397         u32 *s;
 398
 399         if (likely(!(param_debug & OHCI_PARAM_DEBUG_SELFIDS)))
 400                 return;
 401
 402         dev_notice(ohci->card.device,
 403                    "%d selfIDs, generation %d, local node ID %04x\n",
 404                    self_id_count, generation, ohci->node_id);
 405
 406         for (s = ohci->self_id_buffer; self_id_count--; ++s)
 407                 if ((*s & 1 << 23) == 0)
 408                         dev_notice(ohci->card.device,
 409                             "selfID 0: %08x, phy %d [%c%c%c] "
 410                             "%s gc=%d %s %s%s%s\n",
 411                             *s, *s >> 24 & 63, _p(s, 6), _p(s, 4), _p(s, 2),
 412                             speed[*s >> 14 & 3], *s >> 16 & 63,
 413                             power[*s >> 8 & 7], *s >> 22 & 1 ? "L" : "",
 414                             *s >> 11 & 1 ? "c" : "", *s & 2 ? "i" : "");
 415                 else
 416                         dev_notice(ohci->card.device,
 417                             "selfID n: %08x, phy %d [%c%c%c%c%c%c%c%c]\n",
 418                             *s, *s >> 24 & 63,
 419                             _p(s, 16), _p(s, 14), _p(s, 12), _p(s, 10),
 420                             _p(s,  8), _p(s,  6), _p(s,  4), _p(s,  2));
 421 }
 422
 423 static const char *evts[] = {
 424         [0x00] = "evt_no_status",       [0x01] = "-reserved-",
 425         [0x02] = "evt_long_packet",     [0x03] = "evt_missing_ack",
 426         [0x04] = "evt_underrun",        [0x05] = "evt_overrun",
 427         [0x06] = "evt_descriptor_read", [0x07] = "evt_data_read",
 428         [0x08] = "evt_data_write",      [0x09] = "evt_bus_reset",
 429         [0x0a] = "evt_timeout",         [0x0b] = "evt_tcode_err",
 430         [0x0c] = "-reserved-",          [0x0d] = "-reserved-",
 431         [0x0e] = "evt_unknown",         [0x0f] = "evt_flushed",
 432         [0x10] = "-reserved-",          [0x11] = "ack_complete",
 433         [0x12] = "ack_pending ",        [0x13] = "-reserved-",
 434         [0x14] = "ack_busy_X",          [0x15] = "ack_busy_A",
 435         [0x16] = "ack_busy_B",          [0x17] = "-reserved-",
 436         [0x18] = "-reserved-",          [0x19] = "-reserved-",
 437         [0x1a] = "-reserved-",          [0x1b] = "ack_tardy",
 438         [0x1c] = "-reserved-",          [0x1d] = "ack_data_error",
 439         [0x1e] = "ack_type_error",      [0x1f] = "-reserved-",
 440         [0x20] = "pending/cancelled",
 441 };
 442 static const char *tcodes[] = {
 443         [0x0] = "QW req",               [0x1] = "BW req",
 444         [0x2] = "W resp",               [0x3] = "-reserved-",
 445         [0x4] = "QR req",               [0x5] = "BR req",
 446         [0x6] = "QR resp",              [0x7] = "BR resp",
 447         [0x8] = "cycle start",          [0x9] = "Lk req",
 448         [0xa] = "async stream packet",  [0xb] = "Lk resp",
 449         [0xc] = "-reserved-",           [0xd] = "-reserved-",
 450         [0xe] = "link internal",        [0xf] = "-reserved-",
 451 };
 452
 453 static void log_ar_at_event(struct fw_ohci *ohci,
 454                             char dir, int speed, u32 *header, int evt)
 455 {
 456         int tcode = header[0] >> 4 & 0xf;
 457         char specific[12];
 458
 459         if (likely(!(param_debug & OHCI_PARAM_DEBUG_AT_AR)))
 460                 return;
 461
 462         if (unlikely(evt >= ARRAY_SIZE(evts)))
 463                         evt = 0x1f;
 464
 465         if (evt == OHCI1394_evt_bus_reset) {
 466                 dev_notice(ohci->card.device,
 467                            "A%c evt_bus_reset, generation %d\n",
 468                            dir, (header[2] >> 16) & 0xff);
 469                 return;
 470         }
 471
 472         switch (tcode) {
 473         case 0x0: case 0x6: case 0x8:
 474                 snprintf(specific, sizeof(specific), " = %08x",
 475                          be32_to_cpu((__force __be32)header[3]));
 476                 break;
 477         case 0x1: case 0x5: case 0x7: case 0x9: case 0xb:
 478                 snprintf(specific, sizeof(specific), " %x,%x",
 479                          header[3] >> 16, header[3] & 0xffff);
 480                 break;
 481         default:
 482                 specific[0] = '\0';
 483         }
 484
 485         switch (tcode) {
 486         case 0xa:
 487                 dev_notice(ohci->card.device,
 488                            "A%c %s, %s\n",
 489                            dir, evts[evt], tcodes[tcode]);
 490                 break;
 491         case 0xe:
 492                 dev_notice(ohci->card.device,
 493                            "A%c %s, PHY %08x %08x\n",
 494                            dir, evts[evt], header[1], header[2]);
 495                 break;
 496         case 0x0: case 0x1: case 0x4: case 0x5: case 0x9:
 497                 dev_notice(ohci->card.device,
 498                            "A%c spd %x tl %02x, "
 499                            "%04x -> %04x, %s, "
 500                            "%s, %04x%08x%s\n",
 501                            dir, speed, header[0] >> 10 & 0x3f,
 502                            header[1] >> 16, header[0] >> 16, evts[evt],
 503                            tcodes[tcode], header[1] & 0xffff, header[2], specific);
 504                 break;
 505         default:
 506                 dev_notice(ohci->card.device,
 507                            "A%c spd %x tl %02x, "
 508                            "%04x -> %04x, %s, "
 509                            "%s%s\n",
 510                            dir, speed, header[0] >> 10 & 0x3f,
 511                            header[1] >> 16, header[0] >> 16, evts[evt],
 512                            tcodes[tcode], specific);
 513         }
 514 }
 515
 516 static inline void reg_write(const struct fw_ohci *ohci, int offset, u32 data)
 517 {
 518         writel(data, ohci->registers + offset);
 519 }
 520
 521 static inline u32 reg_read(const struct fw_ohci *ohci, int offset)
 522 {
 523         return readl(ohci->registers + offset);
 524 }
 525
 526 static inline void flush_writes(const struct fw_ohci *ohci)
 527 {
 528         /* Do a dummy read to flush writes. */
 529         reg_read(ohci, OHCI1394_Version);
 530 }
 531
 532 /*
 533  * Beware!  read_phy_reg(), write_phy_reg(), update_phy_reg(), and
 534  * read_paged_phy_reg() require the caller to hold ohci->phy_reg_mutex.
 535  * In other words, only use ohci_read_phy_reg() and ohci_update_phy_reg()
 536  * directly.  Exceptions are intrinsically serialized contexts like pci_probe.
 537  */
 538 static int read_phy_reg(struct fw_ohci *ohci, int addr)
 539 {
 540         u32 val;
 541         int i;
 542
 543         reg_write(ohci, OHCI1394_PhyControl, OHCI1394_PhyControl_Read(addr));
 544         for (i = 0; i < 3 + 100; i++) {
 545                 val = reg_read(ohci, OHCI1394_PhyControl);
 546                 if (!~val)
 547                         return -ENODEV; /* Card was ejected. */
 548
 549                 if (val & OHCI1394_PhyControl_ReadDone)
 550                         return OHCI1394_PhyControl_ReadData(val);
 551
 552                 /*
 553                  * Try a few times without waiting.  Sleeping is necessary
 554                  * only when the link/PHY interface is busy.
 555                  */
 556                 if (i >= 3)
 557                         msleep(1);
 558         }
 559         dev_err(ohci->card.device, "failed to read phy reg\n");
 560
 561         return -EBUSY;
 562 }
 563
 564 static int write_phy_reg(const struct fw_ohci *ohci, int addr, u32 val)
 565 {
 566         int i;
 567
 568         reg_write(ohci, OHCI1394_PhyControl,
 569                   OHCI1394_PhyControl_Write(addr, val));
 570         for (i = 0; i < 3 + 100; i++) {
 571                 val = reg_read(ohci, OHCI1394_PhyControl);
 572                 if (!~val)
 573                         return -ENODEV; /* Card was ejected. */
 574
 575                 if (!(val & OHCI1394_PhyControl_WritePending))
 576                         return 0;
 577
 578                 if (i >= 3)
 579                         msleep(1);
 580         }
 581         dev_err(ohci->card.device, "failed to write phy reg\n");
 582
 583         return -EBUSY;
 584 }
 585
 586 static int update_phy_reg(struct fw_ohci *ohci, int addr,
 587                           int clear_bits, int set_bits)
 588 {
 589         int ret = read_phy_reg(ohci, addr);
 590         if (ret < 0)
 591                 return ret;
 592
 593         /*
 594          * The interrupt status bits are cleared by writing a one bit.
 595          * Avoid clearing them unless explicitly requested in set_bits.
 596          */
 597         if (addr == 5)
 598                 clear_bits |= PHY_INT_STATUS_BITS;
 599
 600         return write_phy_reg(ohci, addr, (ret & ~clear_bits) | set_bits);
 601 }
 602
 603 static int read_paged_phy_reg(struct fw_ohci *ohci, int page, int addr)
 604 {
 605         int ret;
 606
 607         ret = update_phy_reg(ohci, 7, PHY_PAGE_SELECT, page << 5);
 608         if (ret < 0)
 609                 return ret;
 610
 611         return read_phy_reg(ohci, addr);
 612 }
 613
 614 static int ohci_read_phy_reg(struct fw_card *card, int addr)
 615 {
 616         struct fw_ohci *ohci = fw_ohci(card);
 617         int ret;
 618
 619         mutex_lock(&ohci->phy_reg_mutex);
 620         ret = read_phy_reg(ohci, addr);
 621         mutex_unlock(&ohci->phy_reg_mutex);
 622
 623         return ret;
 624 }
 625
 626 static int ohci_update_phy_reg(struct fw_card *card, int addr,
 627                                int clear_bits, int set_bits)
 628 {
 629         struct fw_ohci *ohci = fw_ohci(card);
 630         int ret;
 631
 632         mutex_lock(&ohci->phy_reg_mutex);
 633         ret = update_phy_reg(ohci, addr, clear_bits, set_bits);
 634         mutex_unlock(&ohci->phy_reg_mutex);
 635
 636         return ret;
 637 }
 638
 639 static inline dma_addr_t ar_buffer_bus(struct ar_context *ctx, unsigned int i)
 640 {
 641         return page_private(ctx->pages[i]);
 642 }
 643
 644 static void ar_context_link_page(struct ar_context *ctx, unsigned int index)
 645 {
 646         struct descriptor *d;
 647
 648         d = &ctx->descriptors[index];
 649         d->branch_address  &= cpu_to_le32(~0xf);
 650         d->res_count       =  cpu_to_le16(PAGE_SIZE);
 651         d->transfer_status =  0;
 652
 653         wmb(); /* finish init of new descriptors before branch_address update */
 654         d = &ctx->descriptors[ctx->last_buffer_index];
 655         d->branch_address  |= cpu_to_le32(1);
 656
 657         ctx->last_buffer_index = index;
 658
 659         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
 660 }
 661
 662 static void ar_context_release(struct ar_context *ctx)
 663 {
 664         unsigned int i;
 665
 666         if (ctx->buffer)
 667                 vm_unmap_ram(ctx->buffer, AR_BUFFERS + AR_WRAPAROUND_PAGES);
 668
 669         for (i = 0; i < AR_BUFFERS; i++)
 670                 if (ctx->pages[i]) {
 671                         dma_unmap_page(ctx->ohci->card.device,
 672                                        ar_buffer_bus(ctx, i),
 673                                        PAGE_SIZE, DMA_FROM_DEVICE);
 674                         __free_page(ctx->pages[i]);
 675                 }
 676 }
 677
 678 static void ar_context_abort(struct ar_context *ctx, const char *error_msg)
 679 {
 680         struct fw_ohci *ohci = ctx->ohci;
 681
 682         if (reg_read(ohci, CONTROL_CLEAR(ctx->regs)) & CONTEXT_RUN) {
 683                 reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
 684                 flush_writes(ohci);
 685
 686                 dev_err(ohci->card.device, "AR error: %s; DMA stopped\n",
 687                         error_msg);
 688         }
 689         /* FIXME: restart? */
 690 }
 691
 692 static inline unsigned int ar_next_buffer_index(unsigned int index)
 693 {
 694         return (index + 1) % AR_BUFFERS;
 695 }
 696
 697 static inline unsigned int ar_prev_buffer_index(unsigned int index)
 698 {
 699         return (index - 1 + AR_BUFFERS) % AR_BUFFERS;
 700 }
 701
 702 static inline unsigned int ar_first_buffer_index(struct ar_context *ctx)
 703 {
 704         return ar_next_buffer_index(ctx->last_buffer_index);
 705 }
 706
 707 /*
 708  * We search for the buffer that contains the last AR packet DMA data written
 709  * by the controller.
 710  */
 711 static unsigned int ar_search_last_active_buffer(struct ar_context *ctx,
 712                                                  unsigned int *buffer_offset)
 713 {
 714         unsigned int i, next_i, last = ctx->last_buffer_index;
 715         __le16 res_count, next_res_count;
 716
 717         i = ar_first_buffer_index(ctx);
 718         res_count = ACCESS_ONCE(ctx->descriptors[i].res_count);
 719
 720         /* A buffer that is not yet completely filled must be the last one. */
 721         while (i != last && res_count == 0) {
 722
 723                 /* Peek at the next descriptor. */
 724                 next_i = ar_next_buffer_index(i);
 725                 rmb(); /* read descriptors in order */
 726                 next_res_count = ACCESS_ONCE(
 727                                 ctx->descriptors[next_i].res_count);
 728                 /*
 729                  * If the next descriptor is still empty, we must stop at this
 730                  * descriptor.
 731                  */
 732                 if (next_res_count == cpu_to_le16(PAGE_SIZE)) {
 733                         /*
 734                          * The exception is when the DMA data for one packet is
 735                          * split over three buffers; in this case, the middle
 736                          * buffer's descriptor might be never updated by the
 737                          * controller and look still empty, and we have to peek
 738                          * at the third one.
 739                          */
 740                         if (MAX_AR_PACKET_SIZE > PAGE_SIZE && i != last) {
 741                                 next_i = ar_next_buffer_index(next_i);
 742                                 rmb();
 743                                 next_res_count = ACCESS_ONCE(
 744                                         ctx->descriptors[next_i].res_count);
 745                                 if (next_res_count != cpu_to_le16(PAGE_SIZE))
 746                                         goto next_buffer_is_active;
 747                         }
 748
 749                         break;
 750                 }
 751
 752 next_buffer_is_active:
 753                 i = next_i;
 754                 res_count = next_res_count;
 755         }
 756
 757         rmb(); /* read res_count before the DMA data */
 758
 759         *buffer_offset = PAGE_SIZE - le16_to_cpu(res_count);
 760         if (*buffer_offset > PAGE_SIZE) {
 761                 *buffer_offset = 0;
 762                 ar_context_abort(ctx, "corrupted descriptor");
 763         }
 764
 765         return i;
 766 }
 767
 768 static void ar_sync_buffers_for_cpu(struct ar_context *ctx,
 769                                     unsigned int end_buffer_index,
 770                                     unsigned int end_buffer_offset)
 771 {
 772         unsigned int i;
 773
 774         i = ar_first_buffer_index(ctx);
 775         while (i != end_buffer_index) {
 776                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 777                                         ar_buffer_bus(ctx, i),
 778                                         PAGE_SIZE, DMA_FROM_DEVICE);
 779                 i = ar_next_buffer_index(i);
 780         }
 781         if (end_buffer_offset > 0)
 782                 dma_sync_single_for_cpu(ctx->ohci->card.device,
 783                                         ar_buffer_bus(ctx, i),
 784                                         end_buffer_offset, DMA_FROM_DEVICE);
 785 }
 786
 787 #if defined(CONFIG_PPC_PMAC) && defined(CONFIG_PPC32)
 788 #define cond_le32_to_cpu(v) \
 789         (ohci->quirks & QUIRK_BE_HEADERS ? (__force __u32)(v) : le32_to_cpu(v))
 790 #else
 791 #define cond_le32_to_cpu(v) le32_to_cpu(v)
 792 #endif
 793
 794 static __le32 *handle_ar_packet(struct ar_context *ctx, __le32 *buffer)
 795 {
 796         struct fw_ohci *ohci = ctx->ohci;
 797         struct fw_packet p;
 798         u32 status, length, tcode;
 799         int evt;
 800
 801         p.header[0] = cond_le32_to_cpu(buffer[0]);
 802         p.header[1] = cond_le32_to_cpu(buffer[1]);
 803         p.header[2] = cond_le32_to_cpu(buffer[2]);
 804
 805         tcode = (p.header[0] >> 4) & 0x0f;
 806         switch (tcode) {
 807         case TCODE_WRITE_QUADLET_REQUEST:
 808         case TCODE_READ_QUADLET_RESPONSE:
 809                 p.header[3] = (__force __u32) buffer[3];
 810                 p.header_length = 16;
 811                 p.payload_length = 0;
 812                 break;
 813
 814         case TCODE_READ_BLOCK_REQUEST :
 815                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 816                 p.header_length = 16;
 817                 p.payload_length = 0;
 818                 break;
 819
 820         case TCODE_WRITE_BLOCK_REQUEST:
 821         case TCODE_READ_BLOCK_RESPONSE:
 822         case TCODE_LOCK_REQUEST:
 823         case TCODE_LOCK_RESPONSE:
 824                 p.header[3] = cond_le32_to_cpu(buffer[3]);
 825                 p.header_length = 16;
 826                 p.payload_length = p.header[3] >> 16;
 827                 if (p.payload_length > MAX_ASYNC_PAYLOAD) {
 828                         ar_context_abort(ctx, "invalid packet length");
 829                         return NULL;
 830                 }
 831                 break;
 832
 833         case TCODE_WRITE_RESPONSE:
 834         case TCODE_READ_QUADLET_REQUEST:
 835         case OHCI_TCODE_PHY_PACKET:
 836                 p.header_length = 12;
 837                 p.payload_length = 0;
 838                 break;
 839
 840         default:
 841                 ar_context_abort(ctx, "invalid tcode");
 842                 return NULL;
 843         }
 844
 845         p.payload = (void *) buffer + p.header_length;
 846
 847         /* FIXME: What to do about evt_* errors? */
 848         length = (p.header_length + p.payload_length + 3) / 4;
 849         status = cond_le32_to_cpu(buffer[length]);
 850         evt    = (status >> 16) & 0x1f;
 851
 852         p.ack        = evt - 16;
 853         p.speed      = (status >> 21) & 0x7;
 854         p.timestamp  = status & 0xffff;
 855         p.generation = ohci->request_generation;
 856
 857         log_ar_at_event(ohci, 'R', p.speed, p.header, evt);
 858
 859         /*
 860          * Several controllers, notably from NEC and VIA, forget to
 861          * write ack_complete status at PHY packet reception.
 862          */
 863         if (evt == OHCI1394_evt_no_status &&
 864             (p.header[0] & 0xff) == (OHCI1394_phy_tcode << 4))
 865                 p.ack = ACK_COMPLETE;
 866
 867         /*
 868          * The OHCI bus reset handler synthesizes a PHY packet with
 869          * the new generation number when a bus reset happens (see
 870          * section 8.4.2.3).  This helps us determine when a request
 871          * was received and make sure we send the response in the same
 872          * generation.  We only need this for requests; for responses
 873          * we use the unique tlabel for finding the matching
 874          * request.
 875          *
 876          * Alas some chips sometimes emit bus reset packets with a
 877          * wrong generation.  We set the correct generation for these
 878          * at a slightly incorrect time (in bus_reset_work).
 879          */
 880         if (evt == OHCI1394_evt_bus_reset) {
 881                 if (!(ohci->quirks & QUIRK_RESET_PACKET))
 882                         ohci->request_generation = (p.header[2] >> 16) & 0xff;
 883         } else if (ctx == &ohci->ar_request_ctx) {
 884                 fw_core_handle_request(&ohci->card, &p);
 885         } else {
 886                 fw_core_handle_response(&ohci->card, &p);
 887         }
 888
 889         return buffer + length + 1;
 890 }
 891
 892 static void *handle_ar_packets(struct ar_context *ctx, void *p, void *end)
 893 {
 894         void *next;
 895
 896         while (p < end) {
 897                 next = handle_ar_packet(ctx, p);
 898                 if (!next)
 899                         return p;
 900                 p = next;
 901         }
 902
 903         return p;
 904 }
 905
 906 static void ar_recycle_buffers(struct ar_context *ctx, unsigned int end_buffer)
 907 {
 908         unsigned int i;
 909
 910         i = ar_first_buffer_index(ctx);
 911         while (i != end_buffer) {
 912                 dma_sync_single_for_device(ctx->ohci->card.device,
 913                                            ar_buffer_bus(ctx, i),
 914                                            PAGE_SIZE, DMA_FROM_DEVICE);
 915                 ar_context_link_page(ctx, i);
 916                 i = ar_next_buffer_index(i);
 917         }
 918 }
 919
 920 static void ar_context_tasklet(unsigned long data)
 921 {
 922         struct ar_context *ctx = (struct ar_context *)data;
 923         unsigned int end_buffer_index, end_buffer_offset;
 924         void *p, *end;
 925
 926         p = ctx->pointer;
 927         if (!p)
 928                 return;
 929
 930         end_buffer_index = ar_search_last_active_buffer(ctx,
 931                                                         &end_buffer_offset);
 932         ar_sync_buffers_for_cpu(ctx, end_buffer_index, end_buffer_offset);
 933         end = ctx->buffer + end_buffer_index * PAGE_SIZE + end_buffer_offset;
 934
 935         if (end_buffer_index < ar_first_buffer_index(ctx)) {
 936                 /*
 937                  * The filled part of the overall buffer wraps around; handle
 938                  * all packets up to the buffer end here.  If the last packet
 939                  * wraps around, its tail will be visible after the buffer end
 940                  * because the buffer start pages are mapped there again.
 941                  */
 942                 void *buffer_end = ctx->buffer + AR_BUFFERS * PAGE_SIZE;
 943                 p = handle_ar_packets(ctx, p, buffer_end);
 944                 if (p < buffer_end)
 945                         goto error;
 946                 /* adjust p to point back into the actual buffer */
 947                 p -= AR_BUFFERS * PAGE_SIZE;
 948         }
 949
 950         p = handle_ar_packets(ctx, p, end);
 951         if (p != end) {
 952                 if (p > end)
 953                         ar_context_abort(ctx, "inconsistent descriptor");
 954                 goto error;
 955         }
 956
 957         ctx->pointer = p;
 958         ar_recycle_buffers(ctx, end_buffer_index);
 959
 960         return;
 961
 962 error:
 963         ctx->pointer = NULL;
 964 }
 965
 966 static int ar_context_init(struct ar_context *ctx, struct fw_ohci *ohci,
 967                            unsigned int descriptors_offset, u32 regs)
 968 {
 969         unsigned int i;
 970         dma_addr_t dma_addr;
 971         struct page *pages[AR_BUFFERS + AR_WRAPAROUND_PAGES];
 972         struct descriptor *d;
 973
 974         ctx->regs        = regs;
 975         ctx->ohci        = ohci;
 976         tasklet_init(&ctx->tasklet, ar_context_tasklet, (unsigned long)ctx);
 977
 978         for (i = 0; i < AR_BUFFERS; i++) {
 979                 ctx->pages[i] = alloc_page(GFP_KERNEL | GFP_DMA32);
 980                 if (!ctx->pages[i])
 981                         goto out_of_memory;
 982                 dma_addr = dma_map_page(ohci->card.device, ctx->pages[i],
 983                                         0, PAGE_SIZE, DMA_FROM_DEVICE);
 984                 if (dma_mapping_error(ohci->card.device, dma_addr)) {
 985                         __free_page(ctx->pages[i]);
 986                         ctx->pages[i] = NULL;
 987                         goto out_of_memory;
 988                 }
 989                 set_page_private(ctx->pages[i], dma_addr);
 990         }
 991
 992         for (i = 0; i < AR_BUFFERS; i++)
 993                 pages[i]              = ctx->pages[i];
 994         for (i = 0; i < AR_WRAPAROUND_PAGES; i++)
 995                 pages[AR_BUFFERS + i] = ctx->pages[i];
 996         ctx->buffer = vm_map_ram(pages, AR_BUFFERS + AR_WRAPAROUND_PAGES,
 997                                  -1, PAGE_KERNEL);
 998         if (!ctx->buffer)
 999                 goto out_of_memory;
1000
1001         ctx->descriptors     = ohci->misc_buffer     + descriptors_offset;
1002         ctx->descriptors_bus = ohci->misc_buffer_bus + descriptors_offset;
1003
1004         for (i = 0; i < AR_BUFFERS; i++) {
1005                 d = &ctx->descriptors[i];
1006                 d->req_count      = cpu_to_le16(PAGE_SIZE);
1007                 d->control        = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
1008                                                 DESCRIPTOR_STATUS |
1009                                                 DESCRIPTOR_BRANCH_ALWAYS);
1010                 d->data_address   = cpu_to_le32(ar_buffer_bus(ctx, i));
1011                 d->branch_address = cpu_to_le32(ctx->descriptors_bus +
1012                         ar_next_buffer_index(i) * sizeof(struct descriptor));
1013         }
1014
1015         return 0;
1016
1017 out_of_memory:
1018         ar_context_release(ctx);
1019
1020         return -ENOMEM;
1021 }
1022
1023 static void ar_context_run(struct ar_context *ctx)
1024 {
1025         unsigned int i;
1026
1027         for (i = 0; i < AR_BUFFERS; i++)
1028                 ar_context_link_page(ctx, i);
1029
1030         ctx->pointer = ctx->buffer;
1031
1032         reg_write(ctx->ohci, COMMAND_PTR(ctx->regs), ctx->descriptors_bus | 1);
1033         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN);
1034 }
1035
1036 static struct descriptor *find_branch_descriptor(struct descriptor *d, int z)
1037 {
1038         __le16 branch;
1039
1040         branch = d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS);
1041
1042         /* figure out which descriptor the branch address goes in */
1043         if (z == 2 && branch == cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
1044                 return d;
1045         else
1046                 return d + z - 1;
1047 }
1048
1049 static void context_tasklet(unsigned long data)
1050 {
1051         struct context *ctx = (struct context *) data;
1052         struct descriptor *d, *last;
1053         u32 address;
1054         int z;
1055         struct descriptor_buffer *desc;
1056
1057         desc = list_entry(ctx->buffer_list.next,
1058                         struct descriptor_buffer, list);
1059         last = ctx->last;
1060         while (last->branch_address != 0) {
1061                 struct descriptor_buffer *old_desc = desc;
1062                 address = le32_to_cpu(last->branch_address);
1063                 z = address & 0xf;
1064                 address &= ~0xf;
1065                 ctx->current_bus = address;
1066
1067                 /* If the branch address points to a buffer outside of the
1068                  * current buffer, advance to the next buffer. */
1069                 if (address < desc->buffer_bus ||
1070                                 address >= desc->buffer_bus + desc->used)
1071                         desc = list_entry(desc->list.next,
1072                                         struct descriptor_buffer, list);
1073                 d = desc->buffer + (address - desc->buffer_bus) / sizeof(*d);
1074                 last = find_branch_descriptor(d, z);
1075
1076                 if (!ctx->callback(ctx, d, last))
1077                         break;
1078
1079                 if (old_desc != desc) {
1080                         /* If we've advanced to the next buffer, move the
1081                          * previous buffer to the free list. */
1082                         unsigned long flags;
1083                         old_desc->used = 0;
1084                         spin_lock_irqsave(&ctx->ohci->lock, flags);
1085                         list_move_tail(&old_desc->list, &ctx->buffer_list);
1086                         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1087                 }
1088                 ctx->last = last;
1089         }
1090 }
1091
1092 /*
1093  * Allocate a new buffer and add it to the list of free buffers for this
1094  * context.  Must be called with ohci->lock held.
1095  */
1096 static int context_add_buffer(struct context *ctx)
1097 {
1098         struct descriptor_buffer *desc;
1099         dma_addr_t uninitialized_var(bus_addr);
1100         int offset;
1101
1102         /*
1103          * 16MB of descriptors should be far more than enough for any DMA
1104          * program.  This will catch run-away userspace or DoS attacks.
1105          */
1106         if (ctx->total_allocation >= 16*1024*1024)
1107                 return -ENOMEM;
1108
1109         desc = dma_alloc_coherent(ctx->ohci->card.device, PAGE_SIZE,
1110                         &bus_addr, GFP_ATOMIC);
1111         if (!desc)
1112                 return -ENOMEM;
1113
1114         offset = (void *)&desc->buffer - (void *)desc;
1115         desc->buffer_size = PAGE_SIZE - offset;
1116         desc->buffer_bus = bus_addr + offset;
1117         desc->used = 0;
1118
1119         list_add_tail(&desc->list, &ctx->buffer_list);
1120         ctx->total_allocation += PAGE_SIZE;
1121
1122         return 0;
1123 }
1124
1125 static int context_init(struct context *ctx, struct fw_ohci *ohci,
1126                         u32 regs, descriptor_callback_t callback)
1127 {
1128         ctx->ohci = ohci;
1129         ctx->regs = regs;
1130         ctx->total_allocation = 0;
1131
1132         INIT_LIST_HEAD(&ctx->buffer_list);
1133         if (context_add_buffer(ctx) < 0)
1134                 return -ENOMEM;
1135
1136         ctx->buffer_tail = list_entry(ctx->buffer_list.next,
1137                         struct descriptor_buffer, list);
1138
1139         tasklet_init(&ctx->tasklet, context_tasklet, (unsigned long)ctx);
1140         ctx->callback = callback;
1141
1142         /*
1143          * We put a dummy descriptor in the buffer that has a NULL
1144          * branch address and looks like it's been sent.  That way we
1145          * have a descriptor to append DMA programs to.
1146          */
1147         memset(ctx->buffer_tail->buffer, 0, sizeof(*ctx->buffer_tail->buffer));
1148         ctx->buffer_tail->buffer->control = cpu_to_le16(DESCRIPTOR_OUTPUT_LAST);
1149         ctx->buffer_tail->buffer->transfer_status = cpu_to_le16(0x8011);
1150         ctx->buffer_tail->used += sizeof(*ctx->buffer_tail->buffer);
1151         ctx->last = ctx->buffer_tail->buffer;
1152         ctx->prev = ctx->buffer_tail->buffer;
1153
1154         return 0;
1155 }
1156
1157 static void context_release(struct context *ctx)
1158 {
1159         struct fw_card *card = &ctx->ohci->card;
1160         struct descriptor_buffer *desc, *tmp;
1161
1162         list_for_each_entry_safe(desc, tmp, &ctx->buffer_list, list)
1163                 dma_free_coherent(card->device, PAGE_SIZE, desc,
1164                         desc->buffer_bus -
1165                         ((void *)&desc->buffer - (void *)desc));
1166 }
1167
1168 /* Must be called with ohci->lock held */
1169 static struct descriptor *context_get_descriptors(struct context *ctx,
1170                                                   int z, dma_addr_t *d_bus)
1171 {
1172         struct descriptor *d = NULL;
1173         struct descriptor_buffer *desc = ctx->buffer_tail;
1174
1175         if (z * sizeof(*d) > desc->buffer_size)
1176                 return NULL;
1177
1178         if (z * sizeof(*d) > desc->buffer_size - desc->used) {
1179                 /* No room for the descriptor in this buffer, so advance to the
1180                  * next one. */
1181
1182                 if (desc->list.next == &ctx->buffer_list) {
1183                         /* If there is no free buffer next in the list,
1184                          * allocate one. */
1185                         if (context_add_buffer(ctx) < 0)
1186                                 return NULL;
1187                 }
1188                 desc = list_entry(desc->list.next,
1189                                 struct descriptor_buffer, list);
1190                 ctx->buffer_tail = desc;
1191         }
1192
1193         d = desc->buffer + desc->used / sizeof(*d);
1194         memset(d, 0, z * sizeof(*d));
1195         *d_bus = desc->buffer_bus + desc->used;
1196
1197         return d;
1198 }
1199
1200 static void context_run(struct context *ctx, u32 extra)
1201 {
1202         struct fw_ohci *ohci = ctx->ohci;
1203
1204         reg_write(ohci, COMMAND_PTR(ctx->regs),
1205                   le32_to_cpu(ctx->last->branch_address));
1206         reg_write(ohci, CONTROL_CLEAR(ctx->regs), ~0);
1207         reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_RUN | extra);
1208         ctx->running = true;
1209         flush_writes(ohci);
1210 }
1211
1212 static void context_append(struct context *ctx,
1213                            struct descriptor *d, int z, int extra)
1214 {
1215         dma_addr_t d_bus;
1216         struct descriptor_buffer *desc = ctx->buffer_tail;
1217
1218         d_bus = desc->buffer_bus + (d - desc->buffer) * sizeof(*d);
1219
1220         desc->used += (z + extra) * sizeof(*d);
1221
1222         wmb(); /* finish init of new descriptors before branch_address update */
1223         ctx->prev->branch_address = cpu_to_le32(d_bus | z);
1224         ctx->prev = find_branch_descriptor(d, z);
1225 }
1226
1227 static void context_stop(struct context *ctx)
1228 {
1229         struct fw_ohci *ohci = ctx->ohci;
1230         u32 reg;
1231         int i;
1232
1233         reg_write(ohci, CONTROL_CLEAR(ctx->regs), CONTEXT_RUN);
1234         ctx->running = false;
1235
1236         for (i = 0; i < 1000; i++) {
1237                 reg = reg_read(ohci, CONTROL_SET(ctx->regs));
1238                 if ((reg & CONTEXT_ACTIVE) == 0)
1239                         return;
1240
1241                 if (i)
1242                         udelay(10);
1243         }
1244         dev_err(ohci->card.device, "DMA context still active (0x%08x)\n", reg);
1245 }
1246
1247 struct driver_data {
1248         u8 inline_data[8];
1249         struct fw_packet *packet;
1250 };
1251
1252 /*
1253  * This function apppends a packet to the DMA queue for transmission.
1254  * Must always be called with the ochi->lock held to ensure proper
1255  * generation handling and locking around packet queue manipulation.
1256  */
1257 static int at_context_queue_packet(struct context *ctx,
1258                                    struct fw_packet *packet)
1259 {
1260         struct fw_ohci *ohci = ctx->ohci;
1261         dma_addr_t d_bus, uninitialized_var(payload_bus);
1262         struct driver_data *driver_data;
1263         struct descriptor *d, *last;
1264         __le32 *header;
1265         int z, tcode;
1266
1267         d = context_get_descriptors(ctx, 4, &d_bus);
1268         if (d == NULL) {
1269                 packet->ack = RCODE_SEND_ERROR;
1270                 return -1;
1271         }
1272
1273         d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
1274         d[0].res_count = cpu_to_le16(packet->timestamp);
1275
1276         /*
1277          * The DMA format for asyncronous link packets is different
1278          * from the IEEE1394 layout, so shift the fields around
1279          * accordingly.
1280          */
1281
1282         tcode = (packet->header[0] >> 4) & 0x0f;
1283         header = (__le32 *) &d[1];
1284         switch (tcode) {
1285         case TCODE_WRITE_QUADLET_REQUEST:
1286         case TCODE_WRITE_BLOCK_REQUEST:
1287         case TCODE_WRITE_RESPONSE:
1288         case TCODE_READ_QUADLET_REQUEST:
1289         case TCODE_READ_BLOCK_REQUEST:
1290         case TCODE_READ_QUADLET_RESPONSE:
1291         case TCODE_READ_BLOCK_RESPONSE:
1292         case TCODE_LOCK_REQUEST:
1293         case TCODE_LOCK_RESPONSE:
1294                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1295                                         (packet->speed << 16));
1296                 header[1] = cpu_to_le32((packet->header[1] & 0xffff) |
1297                                         (packet->header[0] & 0xffff0000));
1298                 header[2] = cpu_to_le32(packet->header[2]);
1299
1300                 if (TCODE_IS_BLOCK_PACKET(tcode))
1301                         header[3] = cpu_to_le32(packet->header[3]);
1302                 else
1303                         header[3] = (__force __le32) packet->header[3];
1304
1305                 d[0].req_count = cpu_to_le16(packet->header_length);
1306                 break;
1307
1308         case TCODE_LINK_INTERNAL:
1309                 header[0] = cpu_to_le32((OHCI1394_phy_tcode << 4) |
1310                                         (packet->speed << 16));
1311                 header[1] = cpu_to_le32(packet->header[1]);
1312                 header[2] = cpu_to_le32(packet->header[2]);
1313                 d[0].req_count = cpu_to_le16(12);
1314
1315                 if (is_ping_packet(&packet->header[1]))
1316                         d[0].control |= cpu_to_le16(DESCRIPTOR_PING);
1317                 break;
1318
1319         case TCODE_STREAM_DATA:
1320                 header[0] = cpu_to_le32((packet->header[0] & 0xffff) |
1321                                         (packet->speed << 16));
1322                 header[1] = cpu_to_le32(packet->header[0] & 0xffff0000);
1323                 d[0].req_count = cpu_to_le16(8);
1324                 break;
1325
1326         default:
1327                 /* BUG(); */
1328                 packet->ack = RCODE_SEND_ERROR;
1329                 return -1;
1330         }
1331
1332         BUILD_BUG_ON(sizeof(struct driver_data) > sizeof(struct descriptor));
1333         driver_data = (struct driver_data *) &d[3];
1334         driver_data->packet = packet;
1335         packet->driver_data = driver_data;
1336
1337         if (packet->payload_length > 0) {
1338                 if (packet->payload_length > sizeof(driver_data->inline_data)) {
1339                         payload_bus = dma_map_single(ohci->card.device,
1340                                                      packet->payload,
1341                                                      packet->payload_length,
1342                                                      DMA_TO_DEVICE);
1343                         if (dma_mapping_error(ohci->card.device, payload_bus)) {
1344                                 packet->ack = RCODE_SEND_ERROR;
1345                                 return -1;
1346                         }
1347                         packet->payload_bus     = payload_bus;
1348                         packet->payload_mapped  = true;
1349                 } else {
1350                         memcpy(driver_data->inline_data, packet->payload,
1351                                packet->payload_length);
1352                         payload_bus = d_bus + 3 * sizeof(*d);
1353                 }
1354
1355                 d[2].req_count    = cpu_to_le16(packet->payload_length);
1356                 d[2].data_address = cpu_to_le32(payload_bus);
1357                 last = &d[2];
1358                 z = 3;
1359         } else {
1360                 last = &d[0];
1361                 z = 2;
1362         }
1363
1364         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
1365                                      DESCRIPTOR_IRQ_ALWAYS |
1366                                      DESCRIPTOR_BRANCH_ALWAYS);
1367
1368         /* FIXME: Document how the locking works. */
1369         if (ohci->generation != packet->generation) {
1370                 if (packet->payload_mapped)
1371                         dma_unmap_single(ohci->card.device, payload_bus,
1372                                          packet->payload_length, DMA_TO_DEVICE);
1373                 packet->ack = RCODE_GENERATION;
1374                 return -1;
1375         }
1376
1377         context_append(ctx, d, z, 4 - z);
1378
1379         if (ctx->running)
1380                 reg_write(ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
1381         else
1382                 context_run(ctx, 0);
1383
1384         return 0;
1385 }
1386
1387 static void at_context_flush(struct context *ctx)
1388 {
1389         tasklet_disable(&ctx->tasklet);
1390
1391         ctx->flushing = true;
1392         context_tasklet((unsigned long)ctx);
1393         ctx->flushing = false;
1394
1395         tasklet_enable(&ctx->tasklet);
1396 }
1397
1398 static int handle_at_packet(struct context *context,
1399                             struct descriptor *d,
1400                             struct descriptor *last)
1401 {
1402         struct driver_data *driver_data;
1403         struct fw_packet *packet;
1404         struct fw_ohci *ohci = context->ohci;
1405         int evt;
1406
1407         if (last->transfer_status == 0 && !context->flushing)
1408                 /* This descriptor isn't done yet, stop iteration. */
1409                 return 0;
1410
1411         driver_data = (struct driver_data *) &d[3];
1412         packet = driver_data->packet;
1413         if (packet == NULL)
1414                 /* This packet was cancelled, just continue. */
1415                 return 1;
1416
1417         if (packet->payload_mapped)
1418                 dma_unmap_single(ohci->card.device, packet->payload_bus,
1419                                  packet->payload_length, DMA_TO_DEVICE);
1420
1421         evt = le16_to_cpu(last->transfer_status) & 0x1f;
1422         packet->timestamp = le16_to_cpu(last->res_count);
1423
1424         log_ar_at_event(ohci, 'T', packet->speed, packet->header, evt);
1425
1426         switch (evt) {
1427         case OHCI1394_evt_timeout:
1428                 /* Async response transmit timed out. */
1429                 packet->ack = RCODE_CANCELLED;
1430                 break;
1431
1432         case OHCI1394_evt_flushed:
1433                 /*
1434                  * The packet was flushed should give same error as
1435                  * when we try to use a stale generation count.
1436                  */
1437                 packet->ack = RCODE_GENERATION;
1438                 break;
1439
1440         case OHCI1394_evt_missing_ack:
1441                 if (context->flushing)
1442                         packet->ack = RCODE_GENERATION;
1443                 else {
1444                         /*
1445                          * Using a valid (current) generation count, but the
1446                          * node is not on the bus or not sending acks.
1447                          */
1448                         packet->ack = RCODE_NO_ACK;
1449                 }
1450                 break;
1451
1452         case ACK_COMPLETE + 0x10:
1453         case ACK_PENDING + 0x10:
1454         case ACK_BUSY_X + 0x10:
1455         case ACK_BUSY_A + 0x10:
1456         case ACK_BUSY_B + 0x10:
1457         case ACK_DATA_ERROR + 0x10:
1458         case ACK_TYPE_ERROR + 0x10:
1459                 packet->ack = evt - 0x10;
1460                 break;
1461
1462         case OHCI1394_evt_no_status:
1463                 if (context->flushing) {
1464                         packet->ack = RCODE_GENERATION;
1465                         break;
1466                 }
1467                 /* fall through */
1468
1469         default:
1470                 packet->ack = RCODE_SEND_ERROR;
1471                 break;
1472         }
1473
1474         packet->callback(packet, &ohci->card, packet->ack);
1475
1476         return 1;
1477 }
1478
1479 #define HEADER_GET_DESTINATION(q)       (((q) >> 16) & 0xffff)
1480 #define HEADER_GET_TCODE(q)             (((q) >> 4) & 0x0f)
1481 #define HEADER_GET_OFFSET_HIGH(q)       (((q) >> 0) & 0xffff)
1482 #define HEADER_GET_DATA_LENGTH(q)       (((q) >> 16) & 0xffff)
1483 #define HEADER_GET_EXTENDED_TCODE(q)    (((q) >> 0) & 0xffff)
1484
1485 static void handle_local_rom(struct fw_ohci *ohci,
1486                              struct fw_packet *packet, u32 csr)
1487 {
1488         struct fw_packet response;
1489         int tcode, length, i;
1490
1491         tcode = HEADER_GET_TCODE(packet->header[0]);
1492         if (TCODE_IS_BLOCK_PACKET(tcode))
1493                 length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1494         else
1495                 length = 4;
1496
1497         i = csr - CSR_CONFIG_ROM;
1498         if (i + length > CONFIG_ROM_SIZE) {
1499                 fw_fill_response(&response, packet->header,
1500                                  RCODE_ADDRESS_ERROR, NULL, 0);
1501         } else if (!TCODE_IS_READ_REQUEST(tcode)) {
1502                 fw_fill_response(&response, packet->header,
1503                                  RCODE_TYPE_ERROR, NULL, 0);
1504         } else {
1505                 fw_fill_response(&response, packet->header, RCODE_COMPLETE,
1506                                  (void *) ohci->config_rom + i, length);
1507         }
1508
1509         fw_core_handle_response(&ohci->card, &response);
1510 }
1511
1512 static void handle_local_lock(struct fw_ohci *ohci,
1513                               struct fw_packet *packet, u32 csr)
1514 {
1515         struct fw_packet response;
1516         int tcode, length, ext_tcode, sel, try;
1517         __be32 *payload, lock_old;
1518         u32 lock_arg, lock_data;
1519
1520         tcode = HEADER_GET_TCODE(packet->header[0]);
1521         length = HEADER_GET_DATA_LENGTH(packet->header[3]);
1522         payload = packet->payload;
1523         ext_tcode = HEADER_GET_EXTENDED_TCODE(packet->header[3]);
1524
1525         if (tcode == TCODE_LOCK_REQUEST &&
1526             ext_tcode == EXTCODE_COMPARE_SWAP && length == 8) {
1527                 lock_arg = be32_to_cpu(payload[0]);
1528                 lock_data = be32_to_cpu(payload[1]);
1529         } else if (tcode == TCODE_READ_QUADLET_REQUEST) {
1530                 lock_arg = 0;
1531                 lock_data = 0;
1532         } else {
1533                 fw_fill_response(&response, packet->header,
1534                                  RCODE_TYPE_ERROR, NULL, 0);
1535                 goto out;
1536         }
1537
1538         sel = (csr - CSR_BUS_MANAGER_ID) / 4;
1539         reg_write(ohci, OHCI1394_CSRData, lock_data);
1540         reg_write(ohci, OHCI1394_CSRCompareData, lock_arg);
1541         reg_write(ohci, OHCI1394_CSRControl, sel);
1542
1543         for (try = 0; try < 20; try++)
1544                 if (reg_read(ohci, OHCI1394_CSRControl) & 0x80000000) {
1545                         lock_old = cpu_to_be32(reg_read(ohci,
1546                                                         OHCI1394_CSRData));
1547                         fw_fill_response(&response, packet->header,
1548                                          RCODE_COMPLETE,
1549                                          &lock_old, sizeof(lock_old));
1550                         goto out;
1551                 }
1552
1553         dev_err(ohci->card.device, "swap not done (CSR lock timeout)\n");
1554         fw_fill_response(&response, packet->header, RCODE_BUSY, NULL, 0);
1555
1556  out:
1557         fw_core_handle_response(&ohci->card, &response);
1558 }
1559
1560 static void handle_local_request(struct context *ctx, struct fw_packet *packet)
1561 {
1562         u64 offset, csr;
1563
1564         if (ctx == &ctx->ohci->at_request_ctx) {
1565                 packet->ack = ACK_PENDING;
1566                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1567         }
1568
1569         offset =
1570                 ((unsigned long long)
1571                  HEADER_GET_OFFSET_HIGH(packet->header[1]) << 32) |
1572                 packet->header[2];
1573         csr = offset - CSR_REGISTER_BASE;
1574
1575         /* Handle config rom reads. */
1576         if (csr >= CSR_CONFIG_ROM && csr < CSR_CONFIG_ROM_END)
1577                 handle_local_rom(ctx->ohci, packet, csr);
1578         else switch (csr) {
1579         case CSR_BUS_MANAGER_ID:
1580         case CSR_BANDWIDTH_AVAILABLE:
1581         case CSR_CHANNELS_AVAILABLE_HI:
1582         case CSR_CHANNELS_AVAILABLE_LO:
1583                 handle_local_lock(ctx->ohci, packet, csr);
1584                 break;
1585         default:
1586                 if (ctx == &ctx->ohci->at_request_ctx)
1587                         fw_core_handle_request(&ctx->ohci->card, packet);
1588                 else
1589                         fw_core_handle_response(&ctx->ohci->card, packet);
1590                 break;
1591         }
1592
1593         if (ctx == &ctx->ohci->at_response_ctx) {
1594                 packet->ack = ACK_COMPLETE;
1595                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1596         }
1597 }
1598
1599 static void at_context_transmit(struct context *ctx, struct fw_packet *packet)
1600 {
1601         unsigned long flags;
1602         int ret;
1603
1604         spin_lock_irqsave(&ctx->ohci->lock, flags);
1605
1606         if (HEADER_GET_DESTINATION(packet->header[0]) == ctx->ohci->node_id &&
1607             ctx->ohci->generation == packet->generation) {
1608                 spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1609                 handle_local_request(ctx, packet);
1610                 return;
1611         }
1612
1613         ret = at_context_queue_packet(ctx, packet);
1614         spin_unlock_irqrestore(&ctx->ohci->lock, flags);
1615
1616         if (ret < 0)
1617                 packet->callback(packet, &ctx->ohci->card, packet->ack);
1618
1619 }
1620
1621 static void detect_dead_context(struct fw_ohci *ohci,
1622                                 const char *name, unsigned int regs)
1623 {
1624         u32 ctl;
1625
1626         ctl = reg_read(ohci, CONTROL_SET(regs));
1627         if (ctl & CONTEXT_DEAD)
1628                 dev_err(ohci->card.device,
1629                         "DMA context %s has stopped, error code: %s\n",
1630                         name, evts[ctl & 0x1f]);
1631 }
1632
1633 static void handle_dead_contexts(struct fw_ohci *ohci)
1634 {
1635         unsigned int i;
1636         char name[8];
1637
1638         detect_dead_context(ohci, "ATReq", OHCI1394_AsReqTrContextBase);
1639         detect_dead_context(ohci, "ATRsp", OHCI1394_AsRspTrContextBase);
1640         detect_dead_context(ohci, "ARReq", OHCI1394_AsReqRcvContextBase);
1641         detect_dead_context(ohci, "ARRsp", OHCI1394_AsRspRcvContextBase);
1642         for (i = 0; i < 32; ++i) {
1643                 if (!(ohci->it_context_support & (1 << i)))
1644                         continue;
1645                 sprintf(name, "IT%u", i);
1646                 detect_dead_context(ohci, name, OHCI1394_IsoXmitContextBase(i));
1647         }
1648         for (i = 0; i < 32; ++i) {
1649                 if (!(ohci->ir_context_support & (1 << i)))
1650                         continue;
1651                 sprintf(name, "IR%u", i);
1652                 detect_dead_context(ohci, name, OHCI1394_IsoRcvContextBase(i));
1653         }
1654         /* TODO: maybe try to flush and restart the dead contexts */
1655 }
1656
1657 static u32 cycle_timer_ticks(u32 cycle_timer)
1658 {
1659         u32 ticks;
1660
1661         ticks = cycle_timer & 0xfff;
1662         ticks += 3072 * ((cycle_timer >> 12) & 0x1fff);
1663         ticks += (3072 * 8000) * (cycle_timer >> 25);
1664
1665         return ticks;
1666 }
1667
1668 /*
1669  * Some controllers exhibit one or more of the following bugs when updating the
1670  * iso cycle timer register:
1671  *  - When the lowest six bits are wrapping around to zero, a read that happens
1672  *    at the same time will return garbage in the lowest ten bits.
1673  *  - When the cycleOffset field wraps around to zero, the cycleCount field is
1674  *    not incremented for about 60 ns.
1675  *  - Occasionally, the entire register reads zero.
1676  *
1677  * To catch these, we read the register three times and ensure that the
1678  * difference between each two consecutive reads is approximately the same, i.e.
1679  * less than twice the other.  Furthermore, any negative difference indicates an
1680  * error.  (A PCI read should take at least 20 ticks of the 24.576 MHz timer to
1681  * execute, so we have enough precision to compute the ratio of the differences.)
1682  */
1683 static u32 get_cycle_time(struct fw_ohci *ohci)
1684 {
1685         u32 c0, c1, c2;
1686         u32 t0, t1, t2;
1687         s32 diff01, diff12;
1688         int i;
1689
1690         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1691
1692         if (ohci->quirks & QUIRK_CYCLE_TIMER) {
1693                 i = 0;
1694                 c1 = c2;
1695                 c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1696                 do {
1697                         c0 = c1;
1698                         c1 = c2;
1699                         c2 = reg_read(ohci, OHCI1394_IsochronousCycleTimer);
1700                         t0 = cycle_timer_ticks(c0);
1701                         t1 = cycle_timer_ticks(c1);
1702                         t2 = cycle_timer_ticks(c2);
1703                         diff01 = t1 - t0;
1704                         diff12 = t2 - t1;
1705                 } while ((diff01 <= 0 || diff12 <= 0 ||
1706                           diff01 / diff12 >= 2 || diff12 / diff01 >= 2)
1707                          && i++ < 20);
1708         }
1709
1710         return c2;
1711 }
1712
1713 /*
1714  * This function has to be called at least every 64 seconds.  The bus_time
1715  * field stores not only the upper 25 bits of the BUS_TIME register but also
1716  * the most significant bit of the cycle timer in bit 6 so that we can detect
1717  * changes in this bit.
1718  */
1719 static u32 update_bus_time(struct fw_ohci *ohci)
1720 {
1721         u32 cycle_time_seconds = get_cycle_time(ohci) >> 25;
1722
1723         if ((ohci->bus_time & 0x40) != (cycle_time_seconds & 0x40))
1724                 ohci->bus_time += 0x40;
1725
1726         return ohci->bus_time | cycle_time_seconds;
1727 }
1728
1729 static int get_status_for_port(struct fw_ohci *ohci, int port_index)
1730 {
1731         int reg;
1732
1733         mutex_lock(&ohci->phy_reg_mutex);
1734         reg = write_phy_reg(ohci, 7, port_index);
1735         if (reg >= 0)
1736                 reg = read_phy_reg(ohci, 8);
1737         mutex_unlock(&ohci->phy_reg_mutex);
1738         if (reg < 0)
1739                 return reg;
1740
1741         switch (reg & 0x0f) {
1742         case 0x06:
1743                 return 2;       /* is child node (connected to parent node) */
1744         case 0x0e:
1745                 return 3;       /* is parent node (connected to child node) */
1746         }
1747         return 1;               /* not connected */
1748 }
1749
1750 static int get_self_id_pos(struct fw_ohci *ohci, u32 self_id,
1751         int self_id_count)
1752 {
1753         int i;
1754         u32 entry;
1755
1756         for (i = 0; i < self_id_count; i++) {
1757                 entry = ohci->self_id_buffer[i];
1758                 if ((self_id & 0xff000000) == (entry & 0xff000000))
1759                         return -1;
1760                 if ((self_id & 0xff000000) < (entry & 0xff000000))
1761                         return i;
1762         }
1763         return i;
1764 }
1765
1766 /*
1767  * TI TSB82AA2B and TSB12LV26 do not receive the selfID of a locally
1768  * attached TSB41BA3D phy; see http://www.ti.com/litv/pdf/sllz059.
1769  * Construct the selfID from phy register contents.
1770  * FIXME:  How to determine the selfID.i flag?
1771  */
1772 static int find_and_insert_self_id(struct fw_ohci *ohci, int self_id_count)
1773 {
1774         int reg, i, pos, status;
1775         /* link active 1, speed 3, bridge 0, contender 1, more packets 0 */
1776         u32 self_id = 0x8040c800;
1777
1778         reg = reg_read(ohci, OHCI1394_NodeID);
1779         if (!(reg & OHCI1394_NodeID_idValid)) {
1780                 dev_notice(ohci->card.device,
1781                            "node ID not valid, new bus reset in progress\n");
1782                 return -EBUSY;
1783         }
1784         self_id |= ((reg & 0x3f) << 24); /* phy ID */
1785
1786         reg = ohci_read_phy_reg(&ohci->card, 4);
1787         if (reg < 0)
1788                 return reg;
1789         self_id |= ((reg & 0x07) << 8); /* power class */
1790
1791         reg = ohci_read_phy_reg(&ohci->card, 1);
1792         if (reg < 0)
1793                 return reg;
1794         self_id |= ((reg & 0x3f) << 16); /* gap count */
1795
1796         for (i = 0; i < 3; i++) {
1797                 status = get_status_for_port(ohci, i);
1798                 if (status < 0)
1799                         return status;
1800                 self_id |= ((status & 0x3) << (6 - (i * 2)));
1801         }
1802
1803         pos = get_self_id_pos(ohci, self_id, self_id_count);
1804         if (pos >= 0) {
1805                 memmove(&(ohci->self_id_buffer[pos+1]),
1806                         &(ohci->self_id_buffer[pos]),
1807                         (self_id_count - pos) * sizeof(*ohci->self_id_buffer));
1808                 ohci->self_id_buffer[pos] = self_id;
1809                 self_id_count++;
1810         }
1811         return self_id_count;
1812 }
1813
1814 static void bus_reset_work(struct work_struct *work)
1815 {
1816         struct fw_ohci *ohci =
1817                 container_of(work, struct fw_ohci, bus_reset_work);
1818         int self_id_count, i, j, reg;
1819         int generation, new_generation;
1820         unsigned long flags;
1821         void *free_rom = NULL;
1822         dma_addr_t free_rom_bus = 0;
1823         bool is_new_root;
1824
1825         reg = reg_read(ohci, OHCI1394_NodeID);
1826         if (!(reg & OHCI1394_NodeID_idValid)) {
1827                 dev_notice(ohci->card.device,
1828                            "node ID not valid, new bus reset in progress\n");
1829                 return;
1830         }
1831         if ((reg & OHCI1394_NodeID_nodeNumber) == 63) {
1832                 dev_notice(ohci->card.device, "malconfigured bus\n");
1833                 return;
1834         }
1835         ohci->node_id = reg & (OHCI1394_NodeID_busNumber |
1836                                OHCI1394_NodeID_nodeNumber);
1837
1838         is_new_root = (reg & OHCI1394_NodeID_root) != 0;
1839         if (!(ohci->is_root && is_new_root))
1840                 reg_write(ohci, OHCI1394_LinkControlSet,
1841                           OHCI1394_LinkControl_cycleMaster);
1842         ohci->is_root = is_new_root;
1843
1844         reg = reg_read(ohci, OHCI1394_SelfIDCount);
1845         if (reg & OHCI1394_SelfIDCount_selfIDError) {
1846                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1847                 return;
1848         }
1849         /*
1850          * The count in the SelfIDCount register is the number of
1851          * bytes in the self ID receive buffer.  Since we also receive
1852          * the inverted quadlets and a header quadlet, we shift one
1853          * bit extra to get the actual number of self IDs.
1854          */
1855         self_id_count = (reg >> 3) & 0xff;
1856
1857         if (self_id_count > 252) {
1858                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1859                 return;
1860         }
1861
1862         generation = (cond_le32_to_cpu(ohci->self_id_cpu[0]) >> 16) & 0xff;
1863         rmb();
1864
1865         for (i = 1, j = 0; j < self_id_count; i += 2, j++) {
1866                 if (ohci->self_id_cpu[i] != ~ohci->self_id_cpu[i + 1]) {
1867                         /*
1868                          * If the invalid data looks like a cycle start packet,
1869                          * it's likely to be the result of the cycle master
1870                          * having a wrong gap count.  In this case, the self IDs
1871                          * so far are valid and should be processed so that the
1872                          * bus manager can then correct the gap count.
1873                          */
1874                         if (cond_le32_to_cpu(ohci->self_id_cpu[i])
1875                                                         == 0xffff008f) {
1876                                 dev_notice(ohci->card.device,
1877                                            "ignoring spurious self IDs\n");
1878                                 self_id_count = j;
1879                                 break;
1880                         } else {
1881                                 dev_notice(ohci->card.device,
1882                                            "inconsistent self IDs\n");
1883                                 return;
1884                         }
1885                 }
1886                 ohci->self_id_buffer[j] =
1887                                 cond_le32_to_cpu(ohci->self_id_cpu[i]);
1888         }
1889
1890         if (ohci->quirks & QUIRK_TI_SLLZ059) {
1891                 self_id_count = find_and_insert_self_id(ohci, self_id_count);
1892                 if (self_id_count < 0) {
1893                         dev_notice(ohci->card.device,
1894                                    "could not construct local self ID\n");
1895                         return;
1896                 }
1897         }
1898
1899         if (self_id_count == 0) {
1900                 dev_notice(ohci->card.device, "inconsistent self IDs\n");
1901                 return;
1902         }
1903         rmb();
1904
1905         /*
1906          * Check the consistency of the self IDs we just read.  The
1907          * problem we face is that a new bus reset can start while we
1908          * read out the self IDs from the DMA buffer. If this happens,
1909          * the DMA buffer will be overwritten with new self IDs and we
1910          * will read out inconsistent data.  The OHCI specification
1911          * (section 11.2) recommends a technique similar to
1912          * linux/seqlock.h, where we remember the generation of the
1913          * self IDs in the buffer before reading them out and compare
1914          * it to the current generation after reading them out.  If
1915          * the two generations match we know we have a consistent set
1916          * of self IDs.
1917          */
1918
1919         new_generation = (reg_read(ohci, OHCI1394_SelfIDCount) >> 16) & 0xff;
1920         if (new_generation != generation) {
1921                 dev_notice(ohci->card.device,
1922                            "new bus reset, discarding self ids\n");
1923                 return;
1924         }
1925
1926         /* FIXME: Document how the locking works. */
1927         spin_lock_irqsave(&ohci->lock, flags);
1928
1929         ohci->generation = -1; /* prevent AT packet queueing */
1930         context_stop(&ohci->at_request_ctx);
1931         context_stop(&ohci->at_response_ctx);
1932
1933         spin_unlock_irqrestore(&ohci->lock, flags);
1934
1935         /*
1936          * Per OHCI 1.2 draft, clause 7.2.3.3, hardware may leave unsent
1937          * packets in the AT queues and software needs to drain them.
1938          * Some OHCI 1.1 controllers (JMicron) apparently require this too.
1939          */
1940         at_context_flush(&ohci->at_request_ctx);
1941         at_context_flush(&ohci->at_response_ctx);
1942
1943         spin_lock_irqsave(&ohci->lock, flags);
1944
1945         ohci->generation = generation;
1946         reg_write(ohci, OHCI1394_IntEventClear, OHCI1394_busReset);
1947
1948         if (ohci->quirks & QUIRK_RESET_PACKET)
1949                 ohci->request_generation = generation;
1950
1951         /*
1952          * This next bit is unrelated to the AT context stuff but we
1953          * have to do it under the spinlock also.  If a new config rom
1954          * was set up before this reset, the old one is now no longer
1955          * in use and we can free it. Update the config rom pointers
1956          * to point to the current config rom and clear the
1957          * next_config_rom pointer so a new update can take place.
1958          */
1959
1960         if (ohci->next_config_rom != NULL) {
1961                 if (ohci->next_config_rom != ohci->config_rom) {
1962                         free_rom      = ohci->config_rom;
1963                         free_rom_bus  = ohci->config_rom_bus;
1964                 }
1965                 ohci->config_rom      = ohci->next_config_rom;
1966                 ohci->config_rom_bus  = ohci->next_config_rom_bus;
1967                 ohci->next_config_rom = NULL;
1968
1969                 /*
1970                  * Restore config_rom image and manually update
1971                  * config_rom registers.  Writing the header quadlet
1972                  * will indicate that the config rom is ready, so we
1973                  * do that last.
1974                  */
1975                 reg_write(ohci, OHCI1394_BusOptions,
1976                           be32_to_cpu(ohci->config_rom[2]));
1977                 ohci->config_rom[0] = ohci->next_header;
1978                 reg_write(ohci, OHCI1394_ConfigROMhdr,
1979                           be32_to_cpu(ohci->next_header));
1980         }
1981
1982 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
1983         reg_write(ohci, OHCI1394_PhyReqFilterHiSet, ~0);
1984         reg_write(ohci, OHCI1394_PhyReqFilterLoSet, ~0);
1985 #endif
1986
1987         spin_unlock_irqrestore(&ohci->lock, flags);
1988
1989         if (free_rom)
1990                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
1991                                   free_rom, free_rom_bus);
1992
1993         log_selfids(ohci, generation, self_id_count);
1994
1995         fw_core_handle_bus_reset(&ohci->card, ohci->node_id, generation,
1996                                  self_id_count, ohci->self_id_buffer,
1997                                  ohci->csr_state_setclear_abdicate);
1998         ohci->csr_state_setclear_abdicate = false;
1999 }
2000
2001 static irqreturn_t irq_handler(int irq, void *data)
2002 {
2003         struct fw_ohci *ohci = data;
2004         u32 event, iso_event;
2005         int i;
2006
2007         event = reg_read(ohci, OHCI1394_IntEventClear);
2008
2009         if (!event || !~event)
2010                 return IRQ_NONE;
2011
2012         /*
2013          * busReset and postedWriteErr must not be cleared yet
2014          * (OHCI 1.1 clauses 7.2.3.2 and 13.2.8.1)
2015          */
2016         reg_write(ohci, OHCI1394_IntEventClear,
2017                   event & ~(OHCI1394_busReset | OHCI1394_postedWriteErr));
2018         log_irqs(ohci, event);
2019
2020         if (event & OHCI1394_selfIDComplete)
2021                 queue_work(fw_workqueue, &ohci->bus_reset_work);
2022
2023         if (event & OHCI1394_RQPkt)
2024                 tasklet_schedule(&ohci->ar_request_ctx.tasklet);
2025
2026         if (event & OHCI1394_RSPkt)
2027                 tasklet_schedule(&ohci->ar_response_ctx.tasklet);
2028
2029         if (event & OHCI1394_reqTxComplete)
2030                 tasklet_schedule(&ohci->at_request_ctx.tasklet);
2031
2032         if (event & OHCI1394_respTxComplete)
2033                 tasklet_schedule(&ohci->at_response_ctx.tasklet);
2034
2035         if (event & OHCI1394_isochRx) {
2036                 iso_event = reg_read(ohci, OHCI1394_IsoRecvIntEventClear);
2037                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, iso_event);
2038
2039                 while (iso_event) {
2040                         i = ffs(iso_event) - 1;
2041                         tasklet_schedule(
2042                                 &ohci->ir_context_list[i].context.tasklet);
2043                         iso_event &= ~(1 << i);
2044                 }
2045         }
2046
2047         if (event & OHCI1394_isochTx) {
2048                 iso_event = reg_read(ohci, OHCI1394_IsoXmitIntEventClear);
2049                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, iso_event);
2050
2051                 while (iso_event) {
2052                         i = ffs(iso_event) - 1;
2053                         tasklet_schedule(
2054                                 &ohci->it_context_list[i].context.tasklet);
2055                         iso_event &= ~(1 << i);
2056                 }
2057         }
2058
2059         if (unlikely(event & OHCI1394_regAccessFail))
2060                 dev_err(ohci->card.device, "register access failure\n");
2061
2062         if (unlikely(event & OHCI1394_postedWriteErr)) {
2063                 reg_read(ohci, OHCI1394_PostedWriteAddressHi);
2064                 reg_read(ohci, OHCI1394_PostedWriteAddressLo);
2065                 reg_write(ohci, OHCI1394_IntEventClear,
2066                           OHCI1394_postedWriteErr);
2067                 if (printk_ratelimit())
2068                         dev_err(ohci->card.device, "PCI posted write error\n");
2069         }
2070
2071         if (unlikely(event & OHCI1394_cycleTooLong)) {
2072                 if (printk_ratelimit())
2073                         dev_notice(ohci->card.device,
2074                                    "isochronous cycle too long\n");
2075                 reg_write(ohci, OHCI1394_LinkControlSet,
2076                           OHCI1394_LinkControl_cycleMaster);
2077         }
2078
2079         if (unlikely(event & OHCI1394_cycleInconsistent)) {
2080                 /*
2081                  * We need to clear this event bit in order to make
2082                  * cycleMatch isochronous I/O work.  In theory we should
2083                  * stop active cycleMatch iso contexts now and restart
2084                  * them at least two cycles later.  (FIXME?)
2085                  */
2086                 if (printk_ratelimit())
2087                         dev_notice(ohci->card.device,
2088                                    "isochronous cycle inconsistent\n");
2089         }
2090
2091         if (unlikely(event & OHCI1394_unrecoverableError))
2092                 handle_dead_contexts(ohci);
2093
2094         if (event & OHCI1394_cycle64Seconds) {
2095                 spin_lock(&ohci->lock);
2096                 update_bus_time(ohci);
2097                 spin_unlock(&ohci->lock);
2098         } else
2099                 flush_writes(ohci);
2100
2101         return IRQ_HANDLED;
2102 }
2103
2104 static int software_reset(struct fw_ohci *ohci)
2105 {
2106         u32 val;
2107         int i;
2108
2109         reg_write(ohci, OHCI1394_HCControlSet, OHCI1394_HCControl_softReset);
2110         for (i = 0; i < 500; i++) {
2111                 val = reg_read(ohci, OHCI1394_HCControlSet);
2112                 if (!~val)
2113                         return -ENODEV; /* Card was ejected. */
2114
2115                 if (!(val & OHCI1394_HCControl_softReset))
2116                         return 0;
2117
2118                 msleep(1);
2119         }
2120
2121         return -EBUSY;
2122 }
2123
2124 static void copy_config_rom(__be32 *dest, const __be32 *src, size_t length)
2125 {
2126         size_t size = length * 4;
2127
2128         memcpy(dest, src, size);
2129         if (size < CONFIG_ROM_SIZE)
2130                 memset(&dest[length], 0, CONFIG_ROM_SIZE - size);
2131 }
2132
2133 static int configure_1394a_enhancements(struct fw_ohci *ohci)
2134 {
2135         bool enable_1394a;
2136         int ret, clear, set, offset;
2137
2138         /* Check if the driver should configure link and PHY. */
2139         if (!(reg_read(ohci, OHCI1394_HCControlSet) &
2140               OHCI1394_HCControl_programPhyEnable))
2141                 return 0;
2142
2143         /* Paranoia: check whether the PHY supports 1394a, too. */
2144         enable_1394a = false;
2145         ret = read_phy_reg(ohci, 2);
2146         if (ret < 0)
2147                 return ret;
2148         if ((ret & PHY_EXTENDED_REGISTERS) == PHY_EXTENDED_REGISTERS) {
2149                 ret = read_paged_phy_reg(ohci, 1, 8);
2150                 if (ret < 0)
2151                         return ret;
2152                 if (ret >= 1)
2153                         enable_1394a = true;
2154         }
2155
2156         if (ohci->quirks & QUIRK_NO_1394A)
2157                 enable_1394a = false;
2158
2159         /* Configure PHY and link consistently. */
2160         if (enable_1394a) {
2161                 clear = 0;
2162                 set = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2163         } else {
2164                 clear = PHY_ENABLE_ACCEL | PHY_ENABLE_MULTI;
2165                 set = 0;
2166         }
2167         ret = update_phy_reg(ohci, 5, clear, set);
2168         if (ret < 0)
2169                 return ret;
2170
2171         if (enable_1394a)
2172                 offset = OHCI1394_HCControlSet;
2173         else
2174                 offset = OHCI1394_HCControlClear;
2175         reg_write(ohci, offset, OHCI1394_HCControl_aPhyEnhanceEnable);
2176
2177         /* Clean up: configuration has been taken care of. */
2178         reg_write(ohci, OHCI1394_HCControlClear,
2179                   OHCI1394_HCControl_programPhyEnable);
2180
2181         return 0;
2182 }
2183
2184 static int probe_tsb41ba3d(struct fw_ohci *ohci)
2185 {
2186         /* TI vendor ID = 0x080028, TSB41BA3D product ID = 0x833005 (sic) */
2187         static const u8 id[] = { 0x08, 0x00, 0x28, 0x83, 0x30, 0x05, };
2188         int reg, i;
2189
2190         reg = read_phy_reg(ohci, 2);
2191         if (reg < 0)
2192                 return reg;
2193         if ((reg & PHY_EXTENDED_REGISTERS) != PHY_EXTENDED_REGISTERS)
2194                 return 0;
2195
2196         for (i = ARRAY_SIZE(id) - 1; i >= 0; i--) {
2197                 reg = read_paged_phy_reg(ohci, 1, i + 10);
2198                 if (reg < 0)
2199                         return reg;
2200                 if (reg != id[i])
2201                         return 0;
2202         }
2203         return 1;
2204 }
2205
2206 static int ohci_enable(struct fw_card *card,
2207                        const __be32 *config_rom, size_t length)
2208 {
2209         struct fw_ohci *ohci = fw_ohci(card);
2210         struct pci_dev *dev = to_pci_dev(card->device);
2211         u32 lps, seconds, version, irqs;
2212         int i, ret;
2213
2214         if (software_reset(ohci)) {
2215                 dev_err(card->device, "failed to reset ohci card\n");
2216                 return -EBUSY;
2217         }
2218
2219         /*
2220          * Now enable LPS, which we need in order to start accessing
2221          * most of the registers.  In fact, on some cards (ALI M5251),
2222          * accessing registers in the SClk domain without LPS enabled
2223          * will lock up the machine.  Wait 50msec to make sure we have
2224          * full link enabled.  However, with some cards (well, at least
2225          * a JMicron PCIe card), we have to try again sometimes.
2226          */
2227         reg_write(ohci, OHCI1394_HCControlSet,
2228                   OHCI1394_HCControl_LPS |
2229                   OHCI1394_HCControl_postedWriteEnable);
2230         flush_writes(ohci);
2231
2232         for (lps = 0, i = 0; !lps && i < 3; i++) {
2233                 msleep(50);
2234                 lps = reg_read(ohci, OHCI1394_HCControlSet) &
2235                       OHCI1394_HCControl_LPS;
2236         }
2237
2238         if (!lps) {
2239                 dev_err(card->device, "failed to set Link Power Status\n");
2240                 return -EIO;
2241         }
2242
2243         if (ohci->quirks & QUIRK_TI_SLLZ059) {
2244                 ret = probe_tsb41ba3d(ohci);
2245                 if (ret < 0)
2246                         return ret;
2247                 if (ret)
2248                         dev_notice(card->device, "local TSB41BA3D phy\n");
2249                 else
2250                         ohci->quirks &= ~QUIRK_TI_SLLZ059;
2251         }
2252
2253         reg_write(ohci, OHCI1394_HCControlClear,
2254                   OHCI1394_HCControl_noByteSwapData);
2255
2256         reg_write(ohci, OHCI1394_SelfIDBuffer, ohci->self_id_bus);
2257         reg_write(ohci, OHCI1394_LinkControlSet,
2258                   OHCI1394_LinkControl_cycleTimerEnable |
2259                   OHCI1394_LinkControl_cycleMaster);
2260
2261         reg_write(ohci, OHCI1394_ATRetries,
2262                   OHCI1394_MAX_AT_REQ_RETRIES |
2263                   (OHCI1394_MAX_AT_RESP_RETRIES << 4) |
2264                   (OHCI1394_MAX_PHYS_RESP_RETRIES << 8) |
2265                   (200 << 16));
2266
2267         seconds = lower_32_bits(get_seconds());
2268         reg_write(ohci, OHCI1394_IsochronousCycleTimer, seconds << 25);
2269         ohci->bus_time = seconds & ~0x3f;
2270
2271         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
2272         if (version >= OHCI_VERSION_1_1) {
2273                 reg_write(ohci, OHCI1394_InitialChannelsAvailableHi,
2274                           0xfffffffe);
2275                 card->broadcast_channel_auto_allocated = true;
2276         }
2277
2278         /* Get implemented bits of the priority arbitration request counter. */
2279         reg_write(ohci, OHCI1394_FairnessControl, 0x3f);
2280         ohci->pri_req_max = reg_read(ohci, OHCI1394_FairnessControl) & 0x3f;
2281         reg_write(ohci, OHCI1394_FairnessControl, 0);
2282         card->priority_budget_implemented = ohci->pri_req_max != 0;
2283
2284         reg_write(ohci, OHCI1394_PhyUpperBound, 0x00010000);
2285         reg_write(ohci, OHCI1394_IntEventClear, ~0);
2286         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
2287
2288         ret = configure_1394a_enhancements(ohci);
2289         if (ret < 0)
2290                 return ret;
2291
2292         /* Activate link_on bit and contender bit in our self ID packets.*/
2293         ret = ohci_update_phy_reg(card, 4, 0, PHY_LINK_ACTIVE | PHY_CONTENDER);
2294         if (ret < 0)
2295                 return ret;
2296
2297         /*
2298          * When the link is not yet enabled, the atomic config rom
2299          * update mechanism described below in ohci_set_config_rom()
2300          * is not active.  We have to update ConfigRomHeader and
2301          * BusOptions manually, and the write to ConfigROMmap takes
2302          * effect immediately.  We tie this to the enabling of the
2303          * link, so we have a valid config rom before enabling - the
2304          * OHCI requires that ConfigROMhdr and BusOptions have valid
2305          * values before enabling.
2306          *
2307          * However, when the ConfigROMmap is written, some controllers
2308          * always read back quadlets 0 and 2 from the config rom to
2309          * the ConfigRomHeader and BusOptions registers on bus reset.
2310          * They shouldn't do that in this initial case where the link
2311          * isn't enabled.  This means we have to use the same
2312          * workaround here, setting the bus header to 0 and then write
2313          * the right values in the bus reset tasklet.
2314          */
2315
2316         if (config_rom) {
2317                 ohci->next_config_rom =
2318                         dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2319                                            &ohci->next_config_rom_bus,
2320                                            GFP_KERNEL);
2321                 if (ohci->next_config_rom == NULL)
2322                         return -ENOMEM;
2323
2324                 copy_config_rom(ohci->next_config_rom, config_rom, length);
2325         } else {
2326                 /*
2327                  * In the suspend case, config_rom is NULL, which
2328                  * means that we just reuse the old config rom.
2329                  */
2330                 ohci->next_config_rom = ohci->config_rom;
2331                 ohci->next_config_rom_bus = ohci->config_rom_bus;
2332         }
2333
2334         ohci->next_header = ohci->next_config_rom[0];
2335         ohci->next_config_rom[0] = 0;
2336         reg_write(ohci, OHCI1394_ConfigROMhdr, 0);
2337         reg_write(ohci, OHCI1394_BusOptions,
2338                   be32_to_cpu(ohci->next_config_rom[2]));
2339         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2340
2341         reg_write(ohci, OHCI1394_AsReqFilterHiSet, 0x80000000);
2342
2343         if (!(ohci->quirks & QUIRK_NO_MSI))
2344                 pci_enable_msi(dev);
2345         if (request_irq(dev->irq, irq_handler,
2346                         pci_dev_msi_enabled(dev) ? 0 : IRQF_SHARED,
2347                         ohci_driver_name, ohci)) {
2348                 dev_err(card->device, "failed to allocate interrupt %d\n",
2349                         dev->irq);
2350                 pci_disable_msi(dev);
2351
2352                 if (config_rom) {
2353                         dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2354                                           ohci->next_config_rom,
2355                                           ohci->next_config_rom_bus);
2356                         ohci->next_config_rom = NULL;
2357                 }
2358                 return -EIO;
2359         }
2360
2361         irqs =  OHCI1394_reqTxComplete | OHCI1394_respTxComplete |
2362                 OHCI1394_RQPkt | OHCI1394_RSPkt |
2363                 OHCI1394_isochTx | OHCI1394_isochRx |
2364                 OHCI1394_postedWriteErr |
2365                 OHCI1394_selfIDComplete |
2366                 OHCI1394_regAccessFail |
2367                 OHCI1394_cycle64Seconds |
2368                 OHCI1394_cycleInconsistent |
2369                 OHCI1394_unrecoverableError |
2370                 OHCI1394_cycleTooLong |
2371                 OHCI1394_masterIntEnable;
2372         if (param_debug & OHCI_PARAM_DEBUG_BUSRESETS)
2373                 irqs |= OHCI1394_busReset;
2374         reg_write(ohci, OHCI1394_IntMaskSet, irqs);
2375
2376         reg_write(ohci, OHCI1394_HCControlSet,
2377                   OHCI1394_HCControl_linkEnable |
2378                   OHCI1394_HCControl_BIBimageValid);
2379
2380         reg_write(ohci, OHCI1394_LinkControlSet,
2381                   OHCI1394_LinkControl_rcvSelfID |
2382                   OHCI1394_LinkControl_rcvPhyPkt);
2383
2384         ar_context_run(&ohci->ar_request_ctx);
2385         ar_context_run(&ohci->ar_response_ctx);
2386
2387         flush_writes(ohci);
2388
2389         /* We are ready to go, reset bus to finish initialization. */
2390         fw_schedule_bus_reset(&ohci->card, false, true);
2391
2392         return 0;
2393 }
2394
2395 static int ohci_set_config_rom(struct fw_card *card,
2396                                const __be32 *config_rom, size_t length)
2397 {
2398         struct fw_ohci *ohci;
2399         unsigned long flags;
2400         __be32 *next_config_rom;
2401         dma_addr_t uninitialized_var(next_config_rom_bus);
2402
2403         ohci = fw_ohci(card);
2404
2405         /*
2406          * When the OHCI controller is enabled, the config rom update
2407          * mechanism is a bit tricky, but easy enough to use.  See
2408          * section 5.5.6 in the OHCI specification.
2409          *
2410          * The OHCI controller caches the new config rom address in a
2411          * shadow register (ConfigROMmapNext) and needs a bus reset
2412          * for the changes to take place.  When the bus reset is
2413          * detected, the controller loads the new values for the
2414          * ConfigRomHeader and BusOptions registers from the specified
2415          * config rom and loads ConfigROMmap from the ConfigROMmapNext
2416          * shadow register. All automatically and atomically.
2417          *
2418          * Now, there's a twist to this story.  The automatic load of
2419          * ConfigRomHeader and BusOptions doesn't honor the
2420          * noByteSwapData bit, so with a be32 config rom, the
2421          * controller will load be32 values in to these registers
2422          * during the atomic update, even on litte endian
2423          * architectures.  The workaround we use is to put a 0 in the
2424          * header quadlet; 0 is endian agnostic and means that the
2425          * config rom isn't ready yet.  In the bus reset tasklet we
2426          * then set up the real values for the two registers.
2427          *
2428          * We use ohci->lock to avoid racing with the code that sets
2429          * ohci->next_config_rom to NULL (see bus_reset_work).
2430          */
2431
2432         next_config_rom =
2433                 dma_alloc_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2434                                    &next_config_rom_bus, GFP_KERNEL);
2435         if (next_config_rom == NULL)
2436                 return -ENOMEM;
2437
2438         spin_lock_irqsave(&ohci->lock, flags);
2439
2440         /*
2441          * If there is not an already pending config_rom update,
2442          * push our new allocation into the ohci->next_config_rom
2443          * and then mark the local variable as null so that we
2444          * won't deallocate the new buffer.
2445          *
2446          * OTOH, if there is a pending config_rom update, just
2447          * use that buffer with the new config_rom data, and
2448          * let this routine free the unused DMA allocation.
2449          */
2450
2451         if (ohci->next_config_rom == NULL) {
2452                 ohci->next_config_rom = next_config_rom;
2453                 ohci->next_config_rom_bus = next_config_rom_bus;
2454                 next_config_rom = NULL;
2455         }
2456
2457         copy_config_rom(ohci->next_config_rom, config_rom, length);
2458
2459         ohci->next_header = config_rom[0];
2460         ohci->next_config_rom[0] = 0;
2461
2462         reg_write(ohci, OHCI1394_ConfigROMmap, ohci->next_config_rom_bus);
2463
2464         spin_unlock_irqrestore(&ohci->lock, flags);
2465
2466         /* If we didn't use the DMA allocation, delete it. */
2467         if (next_config_rom != NULL)
2468                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
2469                                   next_config_rom, next_config_rom_bus);
2470
2471         /*
2472          * Now initiate a bus reset to have the changes take
2473          * effect. We clean up the old config rom memory and DMA
2474          * mappings in the bus reset tasklet, since the OHCI
2475          * controller could need to access it before the bus reset
2476          * takes effect.
2477          */
2478
2479         fw_schedule_bus_reset(&ohci->card, true, true);
2480
2481         return 0;
2482 }
2483
2484 static void ohci_send_request(struct fw_card *card, struct fw_packet *packet)
2485 {
2486         struct fw_ohci *ohci = fw_ohci(card);
2487
2488         at_context_transmit(&ohci->at_request_ctx, packet);
2489 }
2490
2491 static void ohci_send_response(struct fw_card *card, struct fw_packet *packet)
2492 {
2493         struct fw_ohci *ohci = fw_ohci(card);
2494
2495         at_context_transmit(&ohci->at_response_ctx, packet);
2496 }
2497
2498 static int ohci_cancel_packet(struct fw_card *card, struct fw_packet *packet)
2499 {
2500         struct fw_ohci *ohci = fw_ohci(card);
2501         struct context *ctx = &ohci->at_request_ctx;
2502         struct driver_data *driver_data = packet->driver_data;
2503         int ret = -ENOENT;
2504
2505         tasklet_disable(&ctx->tasklet);
2506
2507         if (packet->ack != 0)
2508                 goto out;
2509
2510         if (packet->payload_mapped)
2511                 dma_unmap_single(ohci->card.device, packet->payload_bus,
2512                                  packet->payload_length, DMA_TO_DEVICE);
2513
2514         log_ar_at_event(ohci, 'T', packet->speed, packet->header, 0x20);
2515         driver_data->packet = NULL;
2516         packet->ack = RCODE_CANCELLED;
2517         packet->callback(packet, &ohci->card, packet->ack);
2518         ret = 0;
2519  out:
2520         tasklet_enable(&ctx->tasklet);
2521
2522         return ret;
2523 }
2524
2525 static int ohci_enable_phys_dma(struct fw_card *card,
2526                                 int node_id, int generation)
2527 {
2528 #ifdef CONFIG_FIREWIRE_OHCI_REMOTE_DMA
2529         return 0;
2530 #else
2531         struct fw_ohci *ohci = fw_ohci(card);
2532         unsigned long flags;
2533         int n, ret = 0;
2534
2535         /*
2536          * FIXME:  Make sure this bitmask is cleared when we clear the busReset
2537          * interrupt bit.  Clear physReqResourceAllBuses on bus reset.
2538          */
2539
2540         spin_lock_irqsave(&ohci->lock, flags);
2541
2542         if (ohci->generation != generation) {
2543                 ret = -ESTALE;
2544                 goto out;
2545         }
2546
2547         /*
2548          * Note, if the node ID contains a non-local bus ID, physical DMA is
2549          * enabled for _all_ nodes on remote buses.
2550          */
2551
2552         n = (node_id & 0xffc0) == LOCAL_BUS ? node_id & 0x3f : 63;
2553         if (n < 32)
2554                 reg_write(ohci, OHCI1394_PhyReqFilterLoSet, 1 << n);
2555         else
2556                 reg_write(ohci, OHCI1394_PhyReqFilterHiSet, 1 << (n - 32));
2557
2558         flush_writes(ohci);
2559  out:
2560         spin_unlock_irqrestore(&ohci->lock, flags);
2561
2562         return ret;
2563 #endif /* CONFIG_FIREWIRE_OHCI_REMOTE_DMA */
2564 }
2565
2566 static u32 ohci_read_csr(struct fw_card *card, int csr_offset)
2567 {
2568         struct fw_ohci *ohci = fw_ohci(card);
2569         unsigned long flags;
2570         u32 value;
2571
2572         switch (csr_offset) {
2573         case CSR_STATE_CLEAR:
2574         case CSR_STATE_SET:
2575                 if (ohci->is_root &&
2576                     (reg_read(ohci, OHCI1394_LinkControlSet) &
2577                      OHCI1394_LinkControl_cycleMaster))
2578                         value = CSR_STATE_BIT_CMSTR;
2579                 else
2580                         value = 0;
2581                 if (ohci->csr_state_setclear_abdicate)
2582                         value |= CSR_STATE_BIT_ABDICATE;
2583
2584                 return value;
2585
2586         case CSR_NODE_IDS:
2587                 return reg_read(ohci, OHCI1394_NodeID) << 16;
2588
2589         case CSR_CYCLE_TIME:
2590                 return get_cycle_time(ohci);
2591
2592         case CSR_BUS_TIME:
2593                 /*
2594                  * We might be called just after the cycle timer has wrapped
2595                  * around but just before the cycle64Seconds handler, so we
2596                  * better check here, too, if the bus time needs to be updated.
2597                  */
2598                 spin_lock_irqsave(&ohci->lock, flags);
2599                 value = update_bus_time(ohci);
2600                 spin_unlock_irqrestore(&ohci->lock, flags);
2601                 return value;
2602
2603         case CSR_BUSY_TIMEOUT:
2604                 value = reg_read(ohci, OHCI1394_ATRetries);
2605                 return (value >> 4) & 0x0ffff00f;
2606
2607         case CSR_PRIORITY_BUDGET:
2608                 return (reg_read(ohci, OHCI1394_FairnessControl) & 0x3f) |
2609                         (ohci->pri_req_max << 8);
2610
2611         default:
2612                 WARN_ON(1);
2613                 return 0;
2614         }
2615 }
2616
2617 static void ohci_write_csr(struct fw_card *card, int csr_offset, u32 value)
2618 {
2619         struct fw_ohci *ohci = fw_ohci(card);
2620         unsigned long flags;
2621
2622         switch (csr_offset) {
2623         case CSR_STATE_CLEAR:
2624                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2625                         reg_write(ohci, OHCI1394_LinkControlClear,
2626                                   OHCI1394_LinkControl_cycleMaster);
2627                         flush_writes(ohci);
2628                 }
2629                 if (value & CSR_STATE_BIT_ABDICATE)
2630                         ohci->csr_state_setclear_abdicate = false;
2631                 break;
2632
2633         case CSR_STATE_SET:
2634                 if ((value & CSR_STATE_BIT_CMSTR) && ohci->is_root) {
2635                         reg_write(ohci, OHCI1394_LinkControlSet,
2636                                   OHCI1394_LinkControl_cycleMaster);
2637                         flush_writes(ohci);
2638                 }
2639                 if (value & CSR_STATE_BIT_ABDICATE)
2640                         ohci->csr_state_setclear_abdicate = true;
2641                 break;
2642
2643         case CSR_NODE_IDS:
2644                 reg_write(ohci, OHCI1394_NodeID, value >> 16);
2645                 flush_writes(ohci);
2646                 break;
2647
2648         case CSR_CYCLE_TIME:
2649                 reg_write(ohci, OHCI1394_IsochronousCycleTimer, value);
2650                 reg_write(ohci, OHCI1394_IntEventSet,
2651                           OHCI1394_cycleInconsistent);
2652                 flush_writes(ohci);
2653                 break;
2654
2655         case CSR_BUS_TIME:
2656                 spin_lock_irqsave(&ohci->lock, flags);
2657                 ohci->bus_time = (ohci->bus_time & 0x7f) | (value & ~0x7f);
2658                 spin_unlock_irqrestore(&ohci->lock, flags);
2659                 break;
2660
2661         case CSR_BUSY_TIMEOUT:
2662                 value = (value & 0xf) | ((value & 0xf) << 4) |
2663                         ((value & 0xf) << 8) | ((value & 0x0ffff000) << 4);
2664                 reg_write(ohci, OHCI1394_ATRetries, value);
2665                 flush_writes(ohci);
2666                 break;
2667
2668         case CSR_PRIORITY_BUDGET:
2669                 reg_write(ohci, OHCI1394_FairnessControl, value & 0x3f);
2670                 flush_writes(ohci);
2671                 break;
2672
2673         default:
2674                 WARN_ON(1);
2675                 break;
2676         }
2677 }
2678
2679 static void flush_iso_completions(struct iso_context *ctx)
2680 {
2681         ctx->base.callback.sc(&ctx->base, ctx->last_timestamp,
2682                               ctx->header_length, ctx->header,
2683                               ctx->base.callback_data);
2684         ctx->header_length = 0;
2685 }
2686
2687 static void copy_iso_headers(struct iso_context *ctx, const u32 *dma_hdr)
2688 {
2689         u32 *ctx_hdr;
2690
2691         if (ctx->header_length + ctx->base.header_size > PAGE_SIZE)
2692                 return;
2693
2694         ctx_hdr = ctx->header + ctx->header_length;
2695         ctx->last_timestamp = (u16)le32_to_cpu((__force __le32)dma_hdr[0]);
2696
2697         /*
2698          * The two iso header quadlets are byteswapped to little
2699          * endian by the controller, but we want to present them
2700          * as big endian for consistency with the bus endianness.
2701          */
2702         if (ctx->base.header_size > 0)
2703                 ctx_hdr[0] = swab32(dma_hdr[1]); /* iso packet header */
2704         if (ctx->base.header_size > 4)
2705                 ctx_hdr[1] = swab32(dma_hdr[0]); /* timestamp */
2706         if (ctx->base.header_size > 8)
2707                 memcpy(&ctx_hdr[2], &dma_hdr[2], ctx->base.header_size - 8);
2708         ctx->header_length += ctx->base.header_size;
2709 }
2710
2711 static int handle_ir_packet_per_buffer(struct context *context,
2712                                        struct descriptor *d,
2713                                        struct descriptor *last)
2714 {
2715         struct iso_context *ctx =
2716                 container_of(context, struct iso_context, context);
2717         struct descriptor *pd;
2718         u32 buffer_dma;
2719
2720         for (pd = d; pd <= last; pd++)
2721                 if (pd->transfer_status)
2722                         break;
2723         if (pd > last)
2724                 /* Descriptor(s) not done yet, stop iteration */
2725                 return 0;
2726
2727         while (!(d->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))) {
2728                 d++;
2729                 buffer_dma = le32_to_cpu(d->data_address);
2730                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2731                                               buffer_dma & PAGE_MASK,
2732                                               buffer_dma & ~PAGE_MASK,
2733                                               le16_to_cpu(d->req_count),
2734                                               DMA_FROM_DEVICE);
2735         }
2736
2737         copy_iso_headers(ctx, (u32 *) (last + 1));
2738
2739         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2740                 flush_iso_completions(ctx);
2741
2742         return 1;
2743 }
2744
2745 /* d == last because each descriptor block is only a single descriptor. */
2746 static int handle_ir_buffer_fill(struct context *context,
2747                                  struct descriptor *d,
2748                                  struct descriptor *last)
2749 {
2750         struct iso_context *ctx =
2751                 container_of(context, struct iso_context, context);
2752         u32 buffer_dma;
2753
2754         if (last->res_count != 0)
2755                 /* Descriptor(s) not done yet, stop iteration */
2756                 return 0;
2757
2758         buffer_dma = le32_to_cpu(last->data_address);
2759         dma_sync_single_range_for_cpu(context->ohci->card.device,
2760                                       buffer_dma & PAGE_MASK,
2761                                       buffer_dma & ~PAGE_MASK,
2762                                       le16_to_cpu(last->req_count),
2763                                       DMA_FROM_DEVICE);
2764
2765         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2766                 ctx->base.callback.mc(&ctx->base,
2767                                       le32_to_cpu(last->data_address) +
2768                                       le16_to_cpu(last->req_count),
2769                                       ctx->base.callback_data);
2770
2771         return 1;
2772 }
2773
2774 static inline void sync_it_packet_for_cpu(struct context *context,
2775                                           struct descriptor *pd)
2776 {
2777         __le16 control;
2778         u32 buffer_dma;
2779
2780         /* only packets beginning with OUTPUT_MORE* have data buffers */
2781         if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2782                 return;
2783
2784         /* skip over the OUTPUT_MORE_IMMEDIATE descriptor */
2785         pd += 2;
2786
2787         /*
2788          * If the packet has a header, the first OUTPUT_MORE/LAST descriptor's
2789          * data buffer is in the context program's coherent page and must not
2790          * be synced.
2791          */
2792         if ((le32_to_cpu(pd->data_address) & PAGE_MASK) ==
2793             (context->current_bus          & PAGE_MASK)) {
2794                 if (pd->control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS))
2795                         return;
2796                 pd++;
2797         }
2798
2799         do {
2800                 buffer_dma = le32_to_cpu(pd->data_address);
2801                 dma_sync_single_range_for_cpu(context->ohci->card.device,
2802                                               buffer_dma & PAGE_MASK,
2803                                               buffer_dma & ~PAGE_MASK,
2804                                               le16_to_cpu(pd->req_count),
2805                                               DMA_TO_DEVICE);
2806                 control = pd->control;
2807                 pd++;
2808         } while (!(control & cpu_to_le16(DESCRIPTOR_BRANCH_ALWAYS)));
2809 }
2810
2811 static int handle_it_packet(struct context *context,
2812                             struct descriptor *d,
2813                             struct descriptor *last)
2814 {
2815         struct iso_context *ctx =
2816                 container_of(context, struct iso_context, context);
2817         struct descriptor *pd;
2818         __be32 *ctx_hdr;
2819
2820         for (pd = d; pd <= last; pd++)
2821                 if (pd->transfer_status)
2822                         break;
2823         if (pd > last)
2824                 /* Descriptor(s) not done yet, stop iteration */
2825                 return 0;
2826
2827         sync_it_packet_for_cpu(context, d);
2828
2829         if (ctx->header_length + 4 < PAGE_SIZE) {
2830                 ctx_hdr = ctx->header + ctx->header_length;
2831                 /* Present this value as big-endian to match the receive code */
2832                 *ctx_hdr = cpu_to_be32(
2833                                 ((u32)le16_to_cpu(pd->transfer_status) << 16) |
2834                                 le16_to_cpu(pd->res_count));
2835                 ctx->header_length += 4;
2836         }
2837
2838         ctx->last_timestamp = le16_to_cpu(last->res_count);
2839         if (last->control & cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS))
2840                 flush_iso_completions(ctx);
2841
2842         return 1;
2843 }
2844
2845 static void set_multichannel_mask(struct fw_ohci *ohci, u64 channels)
2846 {
2847         u32 hi = channels >> 32, lo = channels;
2848
2849         reg_write(ohci, OHCI1394_IRMultiChanMaskHiClear, ~hi);
2850         reg_write(ohci, OHCI1394_IRMultiChanMaskLoClear, ~lo);
2851         reg_write(ohci, OHCI1394_IRMultiChanMaskHiSet, hi);
2852         reg_write(ohci, OHCI1394_IRMultiChanMaskLoSet, lo);
2853         mmiowb();
2854         ohci->mc_channels = channels;
2855 }
2856
2857 static struct fw_iso_context *ohci_allocate_iso_context(struct fw_card *card,
2858                                 int type, int channel, size_t header_size)
2859 {
2860         struct fw_ohci *ohci = fw_ohci(card);
2861         struct iso_context *uninitialized_var(ctx);
2862         descriptor_callback_t uninitialized_var(callback);
2863         u64 *uninitialized_var(channels);
2864         u32 *uninitialized_var(mask), uninitialized_var(regs);
2865         unsigned long flags;
2866         int index, ret = -EBUSY;
2867
2868         spin_lock_irqsave(&ohci->lock, flags);
2869
2870         switch (type) {
2871         case FW_ISO_CONTEXT_TRANSMIT:
2872                 mask     = &ohci->it_context_mask;
2873                 callback = handle_it_packet;
2874                 index    = ffs(*mask) - 1;
2875                 if (index >= 0) {
2876                         *mask &= ~(1 << index);
2877                         regs = OHCI1394_IsoXmitContextBase(index);
2878                         ctx  = &ohci->it_context_list[index];
2879                 }
2880                 break;
2881
2882         case FW_ISO_CONTEXT_RECEIVE:
2883                 channels = &ohci->ir_context_channels;
2884                 mask     = &ohci->ir_context_mask;
2885                 callback = handle_ir_packet_per_buffer;
2886                 index    = *channels & 1ULL << channel ? ffs(*mask) - 1 : -1;
2887                 if (index >= 0) {
2888                         *channels &= ~(1ULL << channel);
2889                         *mask     &= ~(1 << index);
2890                         regs = OHCI1394_IsoRcvContextBase(index);
2891                         ctx  = &ohci->ir_context_list[index];
2892                 }
2893                 break;
2894
2895         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2896                 mask     = &ohci->ir_context_mask;
2897                 callback = handle_ir_buffer_fill;
2898                 index    = !ohci->mc_allocated ? ffs(*mask) - 1 : -1;
2899                 if (index >= 0) {
2900                         ohci->mc_allocated = true;
2901                         *mask &= ~(1 << index);
2902                         regs = OHCI1394_IsoRcvContextBase(index);
2903                         ctx  = &ohci->ir_context_list[index];
2904                 }
2905                 break;
2906
2907         default:
2908                 index = -1;
2909                 ret = -ENOSYS;
2910         }
2911
2912         spin_unlock_irqrestore(&ohci->lock, flags);
2913
2914         if (index < 0)
2915                 return ERR_PTR(ret);
2916
2917         memset(ctx, 0, sizeof(*ctx));
2918         ctx->header_length = 0;
2919         ctx->header = (void *) __get_free_page(GFP_KERNEL);
2920         if (ctx->header == NULL) {
2921                 ret = -ENOMEM;
2922                 goto out;
2923         }
2924         ret = context_init(&ctx->context, ohci, regs, callback);
2925         if (ret < 0)
2926                 goto out_with_header;
2927
2928         if (type == FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL)
2929                 set_multichannel_mask(ohci, 0);
2930
2931         return &ctx->base;
2932
2933  out_with_header:
2934         free_page((unsigned long)ctx->header);
2935  out:
2936         spin_lock_irqsave(&ohci->lock, flags);
2937
2938         switch (type) {
2939         case FW_ISO_CONTEXT_RECEIVE:
2940                 *channels |= 1ULL << channel;
2941                 break;
2942
2943         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2944                 ohci->mc_allocated = false;
2945                 break;
2946         }
2947         *mask |= 1 << index;
2948
2949         spin_unlock_irqrestore(&ohci->lock, flags);
2950
2951         return ERR_PTR(ret);
2952 }
2953
2954 static int ohci_start_iso(struct fw_iso_context *base,
2955                           s32 cycle, u32 sync, u32 tags)
2956 {
2957         struct iso_context *ctx = container_of(base, struct iso_context, base);
2958         struct fw_ohci *ohci = ctx->context.ohci;
2959         u32 control = IR_CONTEXT_ISOCH_HEADER, match;
2960         int index;
2961
2962         /* the controller cannot start without any queued packets */
2963         if (ctx->context.last->branch_address == 0)
2964                 return -ENODATA;
2965
2966         switch (ctx->base.type) {
2967         case FW_ISO_CONTEXT_TRANSMIT:
2968                 index = ctx - ohci->it_context_list;
2969                 match = 0;
2970                 if (cycle >= 0)
2971                         match = IT_CONTEXT_CYCLE_MATCH_ENABLE |
2972                                 (cycle & 0x7fff) << 16;
2973
2974                 reg_write(ohci, OHCI1394_IsoXmitIntEventClear, 1 << index);
2975                 reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, 1 << index);
2976                 context_run(&ctx->context, match);
2977                 break;
2978
2979         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
2980                 control |= IR_CONTEXT_BUFFER_FILL|IR_CONTEXT_MULTI_CHANNEL_MODE;
2981                 /* fall through */
2982         case FW_ISO_CONTEXT_RECEIVE:
2983                 index = ctx - ohci->ir_context_list;
2984                 match = (tags << 28) | (sync << 8) | ctx->base.channel;
2985                 if (cycle >= 0) {
2986                         match |= (cycle & 0x07fff) << 12;
2987                         control |= IR_CONTEXT_CYCLE_MATCH_ENABLE;
2988                 }
2989
2990                 reg_write(ohci, OHCI1394_IsoRecvIntEventClear, 1 << index);
2991                 reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, 1 << index);
2992                 reg_write(ohci, CONTEXT_MATCH(ctx->context.regs), match);
2993                 context_run(&ctx->context, control);
2994
2995                 ctx->sync = sync;
2996                 ctx->tags = tags;
2997
2998                 break;
2999         }
3000
3001         return 0;
3002 }
3003
3004 static int ohci_stop_iso(struct fw_iso_context *base)
3005 {
3006         struct fw_ohci *ohci = fw_ohci(base->card);
3007         struct iso_context *ctx = container_of(base, struct iso_context, base);
3008         int index;
3009
3010         switch (ctx->base.type) {
3011         case FW_ISO_CONTEXT_TRANSMIT:
3012                 index = ctx - ohci->it_context_list;
3013                 reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, 1 << index);
3014                 break;
3015
3016         case FW_ISO_CONTEXT_RECEIVE:
3017         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3018                 index = ctx - ohci->ir_context_list;
3019                 reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, 1 << index);
3020                 break;
3021         }
3022         flush_writes(ohci);
3023         context_stop(&ctx->context);
3024         tasklet_kill(&ctx->context.tasklet);
3025
3026         return 0;
3027 }
3028
3029 static void ohci_free_iso_context(struct fw_iso_context *base)
3030 {
3031         struct fw_ohci *ohci = fw_ohci(base->card);
3032         struct iso_context *ctx = container_of(base, struct iso_context, base);
3033         unsigned long flags;
3034         int index;
3035
3036         ohci_stop_iso(base);
3037         context_release(&ctx->context);
3038         free_page((unsigned long)ctx->header);
3039
3040         spin_lock_irqsave(&ohci->lock, flags);
3041
3042         switch (base->type) {
3043         case FW_ISO_CONTEXT_TRANSMIT:
3044                 index = ctx - ohci->it_context_list;
3045                 ohci->it_context_mask |= 1 << index;
3046                 break;
3047
3048         case FW_ISO_CONTEXT_RECEIVE:
3049                 index = ctx - ohci->ir_context_list;
3050                 ohci->ir_context_mask |= 1 << index;
3051                 ohci->ir_context_channels |= 1ULL << base->channel;
3052                 break;
3053
3054         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3055                 index = ctx - ohci->ir_context_list;
3056                 ohci->ir_context_mask |= 1 << index;
3057                 ohci->ir_context_channels |= ohci->mc_channels;
3058                 ohci->mc_channels = 0;
3059                 ohci->mc_allocated = false;
3060                 break;
3061         }
3062
3063         spin_unlock_irqrestore(&ohci->lock, flags);
3064 }
3065
3066 static int ohci_set_iso_channels(struct fw_iso_context *base, u64 *channels)
3067 {
3068         struct fw_ohci *ohci = fw_ohci(base->card);
3069         unsigned long flags;
3070         int ret;
3071
3072         switch (base->type) {
3073         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3074
3075                 spin_lock_irqsave(&ohci->lock, flags);
3076
3077                 /* Don't allow multichannel to grab other contexts' channels. */
3078                 if (~ohci->ir_context_channels & ~ohci->mc_channels & *channels) {
3079                         *channels = ohci->ir_context_channels;
3080                         ret = -EBUSY;
3081                 } else {
3082                         set_multichannel_mask(ohci, *channels);
3083                         ret = 0;
3084                 }
3085
3086                 spin_unlock_irqrestore(&ohci->lock, flags);
3087
3088                 break;
3089         default:
3090                 ret = -EINVAL;
3091         }
3092
3093         return ret;
3094 }
3095
3096 #ifdef CONFIG_PM
3097 static void ohci_resume_iso_dma(struct fw_ohci *ohci)
3098 {
3099         int i;
3100         struct iso_context *ctx;
3101
3102         for (i = 0 ; i < ohci->n_ir ; i++) {
3103                 ctx = &ohci->ir_context_list[i];
3104                 if (ctx->context.running)
3105                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3106         }
3107
3108         for (i = 0 ; i < ohci->n_it ; i++) {
3109                 ctx = &ohci->it_context_list[i];
3110                 if (ctx->context.running)
3111                         ohci_start_iso(&ctx->base, 0, ctx->sync, ctx->tags);
3112         }
3113 }
3114 #endif
3115
3116 static int queue_iso_transmit(struct iso_context *ctx,
3117                               struct fw_iso_packet *packet,
3118                               struct fw_iso_buffer *buffer,
3119                               unsigned long payload)
3120 {
3121         struct descriptor *d, *last, *pd;
3122         struct fw_iso_packet *p;
3123         __le32 *header;
3124         dma_addr_t d_bus, page_bus;
3125         u32 z, header_z, payload_z, irq;
3126         u32 payload_index, payload_end_index, next_page_index;
3127         int page, end_page, i, length, offset;
3128
3129         p = packet;
3130         payload_index = payload;
3131
3132         if (p->skip)
3133                 z = 1;
3134         else
3135                 z = 2;
3136         if (p->header_length > 0)
3137                 z++;
3138
3139         /* Determine the first page the payload isn't contained in. */
3140         end_page = PAGE_ALIGN(payload_index + p->payload_length) >> PAGE_SHIFT;
3141         if (p->payload_length > 0)
3142                 payload_z = end_page - (payload_index >> PAGE_SHIFT);
3143         else
3144                 payload_z = 0;
3145
3146         z += payload_z;
3147
3148         /* Get header size in number of descriptors. */
3149         header_z = DIV_ROUND_UP(p->header_length, sizeof(*d));
3150
3151         d = context_get_descriptors(&ctx->context, z + header_z, &d_bus);
3152         if (d == NULL)
3153                 return -ENOMEM;
3154
3155         if (!p->skip) {
3156                 d[0].control   = cpu_to_le16(DESCRIPTOR_KEY_IMMEDIATE);
3157                 d[0].req_count = cpu_to_le16(8);
3158                 /*
3159                  * Link the skip address to this descriptor itself.  This causes
3160                  * a context to skip a cycle whenever lost cycles or FIFO
3161                  * overruns occur, without dropping the data.  The application
3162                  * should then decide whether this is an error condition or not.
3163                  * FIXME:  Make the context's cycle-lost behaviour configurable?
3164                  */
3165                 d[0].branch_address = cpu_to_le32(d_bus | z);
3166
3167                 header = (__le32 *) &d[1];
3168                 header[0] = cpu_to_le32(IT_HEADER_SY(p->sy) |
3169                                         IT_HEADER_TAG(p->tag) |
3170                                         IT_HEADER_TCODE(TCODE_STREAM_DATA) |
3171                                         IT_HEADER_CHANNEL(ctx->base.channel) |
3172                                         IT_HEADER_SPEED(ctx->base.speed));
3173                 header[1] =
3174                         cpu_to_le32(IT_HEADER_DATA_LENGTH(p->header_length +
3175                                                           p->payload_length));
3176         }
3177
3178         if (p->header_length > 0) {
3179                 d[2].req_count    = cpu_to_le16(p->header_length);
3180                 d[2].data_address = cpu_to_le32(d_bus + z * sizeof(*d));
3181                 memcpy(&d[z], p->header, p->header_length);
3182         }
3183
3184         pd = d + z - payload_z;
3185         payload_end_index = payload_index + p->payload_length;
3186         for (i = 0; i < payload_z; i++) {
3187                 page               = payload_index >> PAGE_SHIFT;
3188                 offset             = payload_index & ~PAGE_MASK;
3189                 next_page_index    = (page + 1) << PAGE_SHIFT;
3190                 length             =
3191                         min(next_page_index, payload_end_index) - payload_index;
3192                 pd[i].req_count    = cpu_to_le16(length);
3193
3194                 page_bus = page_private(buffer->pages[page]);
3195                 pd[i].data_address = cpu_to_le32(page_bus + offset);
3196
3197                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3198                                                  page_bus, offset, length,
3199                                                  DMA_TO_DEVICE);
3200
3201                 payload_index += length;
3202         }
3203
3204         if (p->interrupt)
3205                 irq = DESCRIPTOR_IRQ_ALWAYS;
3206         else
3207                 irq = DESCRIPTOR_NO_IRQ;
3208
3209         last = z == 2 ? d : d + z - 1;
3210         last->control |= cpu_to_le16(DESCRIPTOR_OUTPUT_LAST |
3211                                      DESCRIPTOR_STATUS |
3212                                      DESCRIPTOR_BRANCH_ALWAYS |
3213                                      irq);
3214
3215         context_append(&ctx->context, d, z, header_z);
3216
3217         return 0;
3218 }
3219
3220 static int queue_iso_packet_per_buffer(struct iso_context *ctx,
3221                                        struct fw_iso_packet *packet,
3222                                        struct fw_iso_buffer *buffer,
3223                                        unsigned long payload)
3224 {
3225         struct device *device = ctx->context.ohci->card.device;
3226         struct descriptor *d, *pd;
3227         dma_addr_t d_bus, page_bus;
3228         u32 z, header_z, rest;
3229         int i, j, length;
3230         int page, offset, packet_count, header_size, payload_per_buffer;
3231
3232         /*
3233          * The OHCI controller puts the isochronous header and trailer in the
3234          * buffer, so we need at least 8 bytes.
3235          */
3236         packet_count = packet->header_length / ctx->base.header_size;
3237         header_size  = max(ctx->base.header_size, (size_t)8);
3238
3239         /* Get header size in number of descriptors. */
3240         header_z = DIV_ROUND_UP(header_size, sizeof(*d));
3241         page     = payload >> PAGE_SHIFT;
3242         offset   = payload & ~PAGE_MASK;
3243         payload_per_buffer = packet->payload_length / packet_count;
3244
3245         for (i = 0; i < packet_count; i++) {
3246                 /* d points to the header descriptor */
3247                 z = DIV_ROUND_UP(payload_per_buffer + offset, PAGE_SIZE) + 1;
3248                 d = context_get_descriptors(&ctx->context,
3249                                 z + header_z, &d_bus);
3250                 if (d == NULL)
3251                         return -ENOMEM;
3252
3253                 d->control      = cpu_to_le16(DESCRIPTOR_STATUS |
3254                                               DESCRIPTOR_INPUT_MORE);
3255                 if (packet->skip && i == 0)
3256                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3257                 d->req_count    = cpu_to_le16(header_size);
3258                 d->res_count    = d->req_count;
3259                 d->transfer_status = 0;
3260                 d->data_address = cpu_to_le32(d_bus + (z * sizeof(*d)));
3261
3262                 rest = payload_per_buffer;
3263                 pd = d;
3264                 for (j = 1; j < z; j++) {
3265                         pd++;
3266                         pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3267                                                   DESCRIPTOR_INPUT_MORE);
3268
3269                         if (offset + rest < PAGE_SIZE)
3270                                 length = rest;
3271                         else
3272                                 length = PAGE_SIZE - offset;
3273                         pd->req_count = cpu_to_le16(length);
3274                         pd->res_count = pd->req_count;
3275                         pd->transfer_status = 0;
3276
3277                         page_bus = page_private(buffer->pages[page]);
3278                         pd->data_address = cpu_to_le32(page_bus + offset);
3279
3280                         dma_sync_single_range_for_device(device, page_bus,
3281                                                          offset, length,
3282                                                          DMA_FROM_DEVICE);
3283
3284                         offset = (offset + length) & ~PAGE_MASK;
3285                         rest -= length;
3286                         if (offset == 0)
3287                                 page++;
3288                 }
3289                 pd->control = cpu_to_le16(DESCRIPTOR_STATUS |
3290                                           DESCRIPTOR_INPUT_LAST |
3291                                           DESCRIPTOR_BRANCH_ALWAYS);
3292                 if (packet->interrupt && i == packet_count - 1)
3293                         pd->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3294
3295                 context_append(&ctx->context, d, z, header_z);
3296         }
3297
3298         return 0;
3299 }
3300
3301 static int queue_iso_buffer_fill(struct iso_context *ctx,
3302                                  struct fw_iso_packet *packet,
3303                                  struct fw_iso_buffer *buffer,
3304                                  unsigned long payload)
3305 {
3306         struct descriptor *d;
3307         dma_addr_t d_bus, page_bus;
3308         int page, offset, rest, z, i, length;
3309
3310         page   = payload >> PAGE_SHIFT;
3311         offset = payload & ~PAGE_MASK;
3312         rest   = packet->payload_length;
3313
3314         /* We need one descriptor for each page in the buffer. */
3315         z = DIV_ROUND_UP(offset + rest, PAGE_SIZE);
3316
3317         if (WARN_ON(offset & 3 || rest & 3 || page + z > buffer->page_count))
3318                 return -EFAULT;
3319
3320         for (i = 0; i < z; i++) {
3321                 d = context_get_descriptors(&ctx->context, 1, &d_bus);
3322                 if (d == NULL)
3323                         return -ENOMEM;
3324
3325                 d->control = cpu_to_le16(DESCRIPTOR_INPUT_MORE |
3326                                          DESCRIPTOR_BRANCH_ALWAYS);
3327                 if (packet->skip && i == 0)
3328                         d->control |= cpu_to_le16(DESCRIPTOR_WAIT);
3329                 if (packet->interrupt && i == z - 1)
3330                         d->control |= cpu_to_le16(DESCRIPTOR_IRQ_ALWAYS);
3331
3332                 if (offset + rest < PAGE_SIZE)
3333                         length = rest;
3334                 else
3335                         length = PAGE_SIZE - offset;
3336                 d->req_count = cpu_to_le16(length);
3337                 d->res_count = d->req_count;
3338                 d->transfer_status = 0;
3339
3340                 page_bus = page_private(buffer->pages[page]);
3341                 d->data_address = cpu_to_le32(page_bus + offset);
3342
3343                 dma_sync_single_range_for_device(ctx->context.ohci->card.device,
3344                                                  page_bus, offset, length,
3345                                                  DMA_FROM_DEVICE);
3346
3347                 rest -= length;
3348                 offset = 0;
3349                 page++;
3350
3351                 context_append(&ctx->context, d, 1, 0);
3352         }
3353
3354         return 0;
3355 }
3356
3357 static int ohci_queue_iso(struct fw_iso_context *base,
3358                           struct fw_iso_packet *packet,
3359                           struct fw_iso_buffer *buffer,
3360                           unsigned long payload)
3361 {
3362         struct iso_context *ctx = container_of(base, struct iso_context, base);
3363         unsigned long flags;
3364         int ret = -ENOSYS;
3365
3366         spin_lock_irqsave(&ctx->context.ohci->lock, flags);
3367         switch (base->type) {
3368         case FW_ISO_CONTEXT_TRANSMIT:
3369                 ret = queue_iso_transmit(ctx, packet, buffer, payload);
3370                 break;
3371         case FW_ISO_CONTEXT_RECEIVE:
3372                 ret = queue_iso_packet_per_buffer(ctx, packet, buffer, payload);
3373                 break;
3374         case FW_ISO_CONTEXT_RECEIVE_MULTICHANNEL:
3375                 ret = queue_iso_buffer_fill(ctx, packet, buffer, payload);
3376                 break;
3377         }
3378         spin_unlock_irqrestore(&ctx->context.ohci->lock, flags);
3379
3380         return ret;
3381 }
3382
3383 static void ohci_flush_queue_iso(struct fw_iso_context *base)
3384 {
3385         struct context *ctx =
3386                         &container_of(base, struct iso_context, base)->context;
3387
3388         reg_write(ctx->ohci, CONTROL_SET(ctx->regs), CONTEXT_WAKE);
3389 }
3390
3391 static const struct fw_card_driver ohci_driver = {
3392         .enable                 = ohci_enable,
3393         .read_phy_reg           = ohci_read_phy_reg,
3394         .update_phy_reg         = ohci_update_phy_reg,
3395         .set_config_rom         = ohci_set_config_rom,
3396         .send_request           = ohci_send_request,
3397         .send_response          = ohci_send_response,
3398         .cancel_packet          = ohci_cancel_packet,
3399         .enable_phys_dma        = ohci_enable_phys_dma,
3400         .read_csr               = ohci_read_csr,
3401         .write_csr              = ohci_write_csr,
3402
3403         .allocate_iso_context   = ohci_allocate_iso_context,
3404         .free_iso_context       = ohci_free_iso_context,
3405         .set_iso_channels       = ohci_set_iso_channels,
3406         .queue_iso              = ohci_queue_iso,
3407         .flush_queue_iso        = ohci_flush_queue_iso,
3408         .start_iso              = ohci_start_iso,
3409         .stop_iso               = ohci_stop_iso,
3410 };
3411
3412 #ifdef CONFIG_PPC_PMAC
3413 static void pmac_ohci_on(struct pci_dev *dev)
3414 {
3415         if (machine_is(powermac)) {
3416                 struct device_node *ofn = pci_device_to_OF_node(dev);
3417
3418                 if (ofn) {
3419                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 1);
3420                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 1);
3421                 }
3422         }
3423 }
3424
3425 static void pmac_ohci_off(struct pci_dev *dev)
3426 {
3427         if (machine_is(powermac)) {
3428                 struct device_node *ofn = pci_device_to_OF_node(dev);
3429
3430                 if (ofn) {
3431                         pmac_call_feature(PMAC_FTR_1394_ENABLE, ofn, 0, 0);
3432                         pmac_call_feature(PMAC_FTR_1394_CABLE_POWER, ofn, 0, 0);
3433                 }
3434         }
3435 }
3436 #else
3437 static inline void pmac_ohci_on(struct pci_dev *dev) {}
3438 static inline void pmac_ohci_off(struct pci_dev *dev) {}
3439 #endif /* CONFIG_PPC_PMAC */
3440
3441 static int __devinit pci_probe(struct pci_dev *dev,
3442                                const struct pci_device_id *ent)
3443 {
3444         struct fw_ohci *ohci;
3445         u32 bus_options, max_receive, link_speed, version;
3446         u64 guid;
3447         int i, err;
3448         size_t size;
3449
3450         if (dev->vendor == PCI_VENDOR_ID_PINNACLE_SYSTEMS) {
3451                 dev_err(&dev->dev, "Pinnacle MovieBoard is not yet supported\n");
3452                 return -ENOSYS;
3453         }
3454
3455         ohci = kzalloc(sizeof(*ohci), GFP_KERNEL);
3456         if (ohci == NULL) {
3457                 err = -ENOMEM;
3458                 goto fail;
3459         }
3460
3461         fw_card_initialize(&ohci->card, &ohci_driver, &dev->dev);
3462
3463         pmac_ohci_on(dev);
3464
3465         err = pci_enable_device(dev);
3466         if (err) {
3467                 dev_err(&dev->dev, "failed to enable OHCI hardware\n");
3468                 goto fail_free;
3469         }
3470
3471         pci_set_master(dev);
3472         pci_write_config_dword(dev, OHCI1394_PCI_HCI_Control, 0);
3473         pci_set_drvdata(dev, ohci);
3474
3475         spin_lock_init(&ohci->lock);
3476         mutex_init(&ohci->phy_reg_mutex);
3477
3478         INIT_WORK(&ohci->bus_reset_work, bus_reset_work);
3479
3480         err = pci_request_region(dev, 0, ohci_driver_name);
3481         if (err) {
3482                 dev_err(&dev->dev, "MMIO resource unavailable\n");
3483                 goto fail_disable;
3484         }
3485
3486         ohci->registers = pci_iomap(dev, 0, OHCI1394_REGISTER_SIZE);
3487         if (ohci->registers == NULL) {
3488                 dev_err(&dev->dev, "failed to remap registers\n");
3489                 err = -ENXIO;
3490                 goto fail_iomem;
3491         }
3492
3493         for (i = 0; i < ARRAY_SIZE(ohci_quirks); i++)
3494                 if ((ohci_quirks[i].vendor == dev->vendor) &&
3495                     (ohci_quirks[i].device == (unsigned short)PCI_ANY_ID ||
3496                      ohci_quirks[i].device == dev->device) &&
3497                     (ohci_quirks[i].revision == (unsigned short)PCI_ANY_ID ||
3498                      ohci_quirks[i].revision >= dev->revision)) {
3499                         ohci->quirks = ohci_quirks[i].flags;
3500                         break;
3501                 }
3502         if (param_quirks)
3503                 ohci->quirks = param_quirks;
3504
3505         /*
3506          * Because dma_alloc_coherent() allocates at least one page,
3507          * we save space by using a common buffer for the AR request/
3508          * response descriptors and the self IDs buffer.
3509          */
3510         BUILD_BUG_ON(AR_BUFFERS * sizeof(struct descriptor) > PAGE_SIZE/4);
3511         BUILD_BUG_ON(SELF_ID_BUF_SIZE > PAGE_SIZE/2);
3512         ohci->misc_buffer = dma_alloc_coherent(ohci->card.device,
3513                                                PAGE_SIZE,
3514                                                &ohci->misc_buffer_bus,
3515                                                GFP_KERNEL);
3516         if (!ohci->misc_buffer) {
3517                 err = -ENOMEM;
3518                 goto fail_iounmap;
3519         }
3520
3521         err = ar_context_init(&ohci->ar_request_ctx, ohci, 0,
3522                               OHCI1394_AsReqRcvContextControlSet);
3523         if (err < 0)
3524                 goto fail_misc_buf;
3525
3526         err = ar_context_init(&ohci->ar_response_ctx, ohci, PAGE_SIZE/4,
3527                               OHCI1394_AsRspRcvContextControlSet);
3528         if (err < 0)
3529                 goto fail_arreq_ctx;
3530
3531         err = context_init(&ohci->at_request_ctx, ohci,
3532                            OHCI1394_AsReqTrContextControlSet, handle_at_packet);
3533         if (err < 0)
3534                 goto fail_arrsp_ctx;
3535
3536         err = context_init(&ohci->at_response_ctx, ohci,
3537                            OHCI1394_AsRspTrContextControlSet, handle_at_packet);
3538         if (err < 0)
3539                 goto fail_atreq_ctx;
3540
3541         reg_write(ohci, OHCI1394_IsoRecvIntMaskSet, ~0);
3542         ohci->ir_context_channels = ~0ULL;
3543         ohci->ir_context_support = reg_read(ohci, OHCI1394_IsoRecvIntMaskSet);
3544         reg_write(ohci, OHCI1394_IsoRecvIntMaskClear, ~0);
3545         ohci->ir_context_mask = ohci->ir_context_support;
3546         ohci->n_ir = hweight32(ohci->ir_context_mask);
3547         size = sizeof(struct iso_context) * ohci->n_ir;
3548         ohci->ir_context_list = kzalloc(size, GFP_KERNEL);
3549
3550         reg_write(ohci, OHCI1394_IsoXmitIntMaskSet, ~0);
3551         ohci->it_context_support = reg_read(ohci, OHCI1394_IsoXmitIntMaskSet);
3552         reg_write(ohci, OHCI1394_IsoXmitIntMaskClear, ~0);
3553         ohci->it_context_mask = ohci->it_context_support;
3554         ohci->n_it = hweight32(ohci->it_context_mask);
3555         size = sizeof(struct iso_context) * ohci->n_it;
3556         ohci->it_context_list = kzalloc(size, GFP_KERNEL);
3557
3558         if (ohci->it_context_list == NULL || ohci->ir_context_list == NULL) {
3559                 err = -ENOMEM;
3560                 goto fail_contexts;
3561         }
3562
3563         ohci->self_id_cpu = ohci->misc_buffer     + PAGE_SIZE/2;
3564         ohci->self_id_bus = ohci->misc_buffer_bus + PAGE_SIZE/2;
3565
3566         bus_options = reg_read(ohci, OHCI1394_BusOptions);
3567         max_receive = (bus_options >> 12) & 0xf;
3568         link_speed = bus_options & 0x7;
3569         guid = ((u64) reg_read(ohci, OHCI1394_GUIDHi) << 32) |
3570                 reg_read(ohci, OHCI1394_GUIDLo);
3571
3572         err = fw_card_add(&ohci->card, max_receive, link_speed, guid);
3573         if (err)
3574                 goto fail_contexts;
3575
3576         version = reg_read(ohci, OHCI1394_Version) & 0x00ff00ff;
3577         dev_notice(&dev->dev,
3578                   "added OHCI v%x.%x device as card %d, "
3579                   "%d IR + %d IT contexts, quirks 0x%x\n",
3580                   version >> 16, version & 0xff, ohci->card.index,
3581                   ohci->n_ir, ohci->n_it, ohci->quirks);
3582
3583         return 0;
3584
3585  fail_contexts:
3586         kfree(ohci->ir_context_list);
3587         kfree(ohci->it_context_list);
3588         context_release(&ohci->at_response_ctx);
3589  fail_atreq_ctx:
3590         context_release(&ohci->at_request_ctx);
3591  fail_arrsp_ctx:
3592         ar_context_release(&ohci->ar_response_ctx);
3593  fail_arreq_ctx:
3594         ar_context_release(&ohci->ar_request_ctx);
3595  fail_misc_buf:
3596         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3597                           ohci->misc_buffer, ohci->misc_buffer_bus);
3598  fail_iounmap:
3599         pci_iounmap(dev, ohci->registers);
3600  fail_iomem:
3601         pci_release_region(dev, 0);
3602  fail_disable:
3603         pci_disable_device(dev);
3604  fail_free:
3605         kfree(ohci);
3606         pmac_ohci_off(dev);
3607  fail:
3608         if (err == -ENOMEM)
3609                 dev_err(&dev->dev, "out of memory\n");
3610
3611         return err;
3612 }
3613
3614 static void pci_remove(struct pci_dev *dev)
3615 {
3616         struct fw_ohci *ohci;
3617
3618         ohci = pci_get_drvdata(dev);
3619         reg_write(ohci, OHCI1394_IntMaskClear, ~0);
3620         flush_writes(ohci);
3621         cancel_work_sync(&ohci->bus_reset_work);
3622         fw_core_remove_card(&ohci->card);
3623
3624         /*
3625          * FIXME: Fail all pending packets here, now that the upper
3626          * layers can't queue any more.
3627          */
3628
3629         software_reset(ohci);
3630         free_irq(dev->irq, ohci);
3631
3632         if (ohci->next_config_rom && ohci->next_config_rom != ohci->config_rom)
3633                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3634                                   ohci->next_config_rom, ohci->next_config_rom_bus);
3635         if (ohci->config_rom)
3636                 dma_free_coherent(ohci->card.device, CONFIG_ROM_SIZE,
3637                                   ohci->config_rom, ohci->config_rom_bus);
3638         ar_context_release(&ohci->ar_request_ctx);
3639         ar_context_release(&ohci->ar_response_ctx);
3640         dma_free_coherent(ohci->card.device, PAGE_SIZE,
3641                           ohci->misc_buffer, ohci->misc_buffer_bus);
3642         context_release(&ohci->at_request_ctx);
3643         context_release(&ohci->at_response_ctx);
3644         kfree(ohci->it_context_list);
3645         kfree(ohci->ir_context_list);
3646         pci_disable_msi(dev);
3647         pci_iounmap(dev, ohci->registers);
3648         pci_release_region(dev, 0);
3649         pci_disable_device(dev);
3650         kfree(ohci);
3651         pmac_ohci_off(dev);
3652
3653         dev_notice(&dev->dev, "removed fw-ohci device\n");
3654 }
3655
3656 #ifdef CONFIG_PM
3657 static int pci_suspend(struct pci_dev *dev, pm_message_t state)
3658 {
3659         struct fw_ohci *ohci = pci_get_drvdata(dev);
3660         int err;
3661
3662         software_reset(ohci);
3663         free_irq(dev->irq, ohci);
3664         pci_disable_msi(dev);
3665         err = pci_save_state(dev);
3666         if (err) {
3667                 dev_err(&dev->dev, "pci_save_state failed\n");
3668                 return err;
3669         }
3670         err = pci_set_power_state(dev, pci_choose_state(dev, state));
3671         if (err)
3672                 dev_err(&dev->dev, "pci_set_power_state failed with %d\n", err);
3673         pmac_ohci_off(dev);
3674
3675         return 0;
3676 }
3677
3678 static int pci_resume(struct pci_dev *dev)
3679 {
3680         struct fw_ohci *ohci = pci_get_drvdata(dev);
3681         int err;
3682
3683         pmac_ohci_on(dev);
3684         pci_set_power_state(dev, PCI_D0);
3685         pci_restore_state(dev);
3686         err = pci_enable_device(dev);
3687         if (err) {
3688                 dev_err(&dev->dev, "pci_enable_device failed\n");
3689                 return err;
3690         }
3691
3692         /* Some systems don't setup GUID register on resume from ram  */
3693         if (!reg_read(ohci, OHCI1394_GUIDLo) &&
3694                                         !reg_read(ohci, OHCI1394_GUIDHi)) {
3695                 reg_write(ohci, OHCI1394_GUIDLo, (u32)ohci->card.guid);
3696                 reg_write(ohci, OHCI1394_GUIDHi, (u32)(ohci->card.guid >> 32));
3697         }
3698
3699         err = ohci_enable(&ohci->card, NULL, 0);
3700         if (err)
3701                 return err;
3702
3703         ohci_resume_iso_dma(ohci);
3704
3705         return 0;
3706 }
3707 #endif
3708
3709 static const struct pci_device_id pci_table[] = {
3710         { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_FIREWIRE_OHCI, ~0) },
3711         { }
3712 };
3713
3714 MODULE_DEVICE_TABLE(pci, pci_table);
3715
3716 static struct pci_driver fw_ohci_pci_driver = {
3717         .name           = ohci_driver_name,
3718         .id_table       = pci_table,
3719         .probe          = pci_probe,
3720         .remove         = pci_remove,
3721 #ifdef CONFIG_PM
3722         .resume         = pci_resume,
3723         .suspend        = pci_suspend,
3724 #endif
3725 };
3726
3727 MODULE_AUTHOR("Kristian Hoegsberg <krh@bitplanet.net>");
3728 MODULE_DESCRIPTION("Driver for PCI OHCI IEEE1394 controllers");
3729 MODULE_LICENSE("GPL");
3730
3731 /* Provide a module alias so root-on-sbp2 initrds don't break. */
3732 #ifndef CONFIG_IEEE1394_OHCI1394_MODULE
3733 MODULE_ALIAS("ohci1394");
3734 #endif
3735
3736 static int __init fw_ohci_init(void)
3737 {
3738         return pci_register_driver(&fw_ohci_pci_driver);
3739 }
3740
3741 static void __exit fw_ohci_cleanup(void)
3742 {
3743         pci_unregister_driver(&fw_ohci_pci_driver);
3744 }
3745
3746 module_init(fw_ohci_init);
3747 module_exit(fw_ohci_cleanup);