From 56a09572268504317eb2885b827f9c4378071a7c Mon Sep 17 00:00:00 2001 From: l4check Date: Mon, 8 Apr 2013 17:39:36 +0000 Subject: [PATCH] update git-svn-id: http://svn.tudos.org/repos/oc/tudos/trunk@51 d050ee49-bd90-4346-b210-929a50b99cfc --- kernel/fiasco/Makefile | 6 +- kernel/fiasco/src/Kconfig | 91 +- kernel/fiasco/src/Makeconf.amd64 | 2 + kernel/fiasco/src/Makeconf.arm | 5 +- kernel/fiasco/src/Makeconf.ia32 | 2 + kernel/fiasco/src/Makefile | 9 +- kernel/fiasco/src/Makerules.UNITTEST | 5 +- kernel/fiasco/src/Makerules.global | 4 +- kernel/fiasco/src/Modules.amd64 | 13 +- kernel/fiasco/src/Modules.arm | 47 +- kernel/fiasco/src/Modules.generic | 8 + kernel/fiasco/src/Modules.ia32 | 13 +- kernel/fiasco/src/Modules.ux | 7 +- kernel/fiasco/src/abi/kip.cpp | 2 +- kernel/fiasco/src/abi/l4_buf_desc.cpp | 2 +- kernel/fiasco/src/abi/l4_fpage.cpp | 145 +- kernel/fiasco/src/abi/l4_msg_item.cpp | 23 +- kernel/fiasco/src/abi/l4_types.cpp | 29 +- .../src/boot/amd64/Makerules.BOOT.amd64 | 3 +- kernel/fiasco/src/boot/amd64/boot_cpu.cc | 2 +- kernel/fiasco/src/boot/amd64/boot_paging.h | 3 - .../fiasco/src/boot/ia32/Makerules.BOOT.ia32 | 3 +- kernel/fiasco/src/boot/ia32/boot_paging.h | 6 - kernel/fiasco/src/drivers/arm/mmu-arm.cpp | 239 +- .../fiasco/src/drivers/arm/processor-arm.cpp | 95 +- kernel/fiasco/src/drivers/arm/sa1100.cpp | 54 +- kernel/fiasco/src/drivers/io.cpp | 54 +- .../fiasco/src/drivers/mmio_register_block.h | 35 + .../src/drivers/ppc32/processor-ppc32.cpp | 6 +- .../src/drivers/sparc/processor-sparc.cpp | 6 +- kernel/fiasco/src/drivers/uart-16550.cpp | 6 +- kernel/fiasco/src/jdb/arm/jdb-arm.cpp | 55 +- kernel/fiasco/src/jdb/arm/jdb_extensions.cpp | 16 +- .../fiasco/src/jdb/arm/jdb_kern_info-arm.cpp | 2 +- .../src/jdb/arm/jdb_kern_info-bench-arm.cpp | 2 +- kernel/fiasco/src/jdb/arm/jdb_ptab-arm.cpp | 191 +- kernel/fiasco/src/jdb/arm/jdb_vm.cpp | 29 +- .../ia32/32/jdb_kern_info-bench-ia32-32.cpp | 4 +- .../fiasco/src/jdb/ia32/64/jdb_ptab-amd64.cpp | 91 +- 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| 2 +- .../fiasco/src/jdb/jdb_ptab-ia32-ux-arm.cpp | 117 +- kernel/fiasco/src/jdb/jdb_ptab.cpp | 133 +- kernel/fiasco/src/jdb/jdb_rcupdate.cpp | 8 +- kernel/fiasco/src/jdb/jdb_table.cpp | 2 +- kernel/fiasco/src/jdb/jdb_tbuf.cpp | 46 +- kernel/fiasco/src/jdb/jdb_tbuf_show.cpp | 19 +- kernel/fiasco/src/jdb/jdb_tcb.cpp | 21 +- kernel/fiasco/src/jdb/jdb_tetris.cpp | 2 +- kernel/fiasco/src/jdb/jdb_thread_list.cpp | 12 +- kernel/fiasco/src/jdb/jdb_timeout.cpp | 7 +- kernel/fiasco/src/jdb/jdb_trap_state.cpp | 9 +- kernel/fiasco/src/jdb/jdb_util.cpp | 5 +- kernel/fiasco/src/jdb/ppc32/jdb-ppc32.cpp | 16 +- kernel/fiasco/src/jdb/sparc/jdb-sparc.cpp | 18 +- kernel/fiasco/src/jdb/ux/jdb-ux.cpp | 43 +- kernel/fiasco/src/jdb/ux/jdb_bp-ux.cpp | 4 +- kernel/fiasco/src/kern/app_cpu_thread.cpp | 4 +- kernel/fiasco/src/kern/arm/Makerules.KERNEL | 12 +- kernel/fiasco/src/kern/arm/asm_entry.h | 215 ++ kernel/fiasco/src/kern/arm/bootstrap.cpp | 273 +- .../fiasco/src/kern/arm/bsp/bcm2835/Kconfig | 4 + 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.../arm/bsp/exynos/pic-arm-gic-exynos.cpp | 904 +++++++ .../arm/bsp/exynos/platform-arm-exynos.cpp | 180 ++ .../exynos/platform_control-arm-exynos.cpp | 196 ++ .../kern/arm/bsp/exynos/reset-arm-exynos.cpp | 14 + .../kern/arm/bsp/exynos/scu-arm-exynos.cpp | 24 + kernel/fiasco/src/kern/arm/bsp/exynos/smc.cpp | 90 + .../kern/arm/bsp/exynos/thread-arm-exynos.cpp | 38 + .../kern/arm/bsp/exynos/timer-arm-exynos.cpp | 145 ++ .../src/kern/arm/bsp/exynos/timer_mct.cpp | 95 + .../arm/bsp/exynos/timer_tick-exynos-mct.cpp | 119 + .../kern/arm/bsp/exynos/uart-arm-exynos.cpp | 25 + .../arm/bsp/exynos/watchdog-arm-exynos.cpp | 84 + kernel/fiasco/src/kern/arm/bsp/imx/Modules | 6 +- .../kern/arm/bsp/imx/bootstrap-arm-imx.cpp | 16 +- .../kern/arm/bsp/imx/mem_layout-arm-imx.cpp | 97 +- .../src/kern/arm/bsp/imx/pic-arm-imx.cpp | 101 +- .../src/kern/arm/bsp/imx/pic-arm-imx51.cpp | 5 +- .../arm/bsp/imx/platform_control-arm-imx6.cpp | 24 +- .../src/kern/arm/bsp/imx/reset-arm-imx.cpp | 14 +- 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kernel/fiasco/src/kern/arm/bsp/exynos/timer_mct.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/exynos/timer_tick-exynos-mct.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/exynos/uart-arm-exynos.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/exynos/watchdog-arm-exynos.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/imx/timer_imx_epit.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/Kconfig create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/Modules create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/bootstrap-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/config-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/kernel_uart-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/mem_layout-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/outer_cache-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/pic-arm-gic-omap4.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/pic-arm-omap3.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/platform_control-arm-omap4.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/reset-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/timer-arm-mptimer-omap4.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/timer-arm-omap3.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/timer_omap_1mstimer.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/timer_omap_gentimer.cpp create mode 100644 kernel/fiasco/src/kern/arm/bsp/omap/uart-arm-omap.cpp create mode 100644 kernel/fiasco/src/kern/arm/scu.cpp create mode 100644 kernel/fiasco/src/kern/arm/timer_sp804.cpp create mode 100644 kernel/fiasco/src/kern/arm/vm_factory-arm.cpp create mode 100644 kernel/fiasco/src/kern/ia32/vm_vmx_ept.cpp create mode 100644 kernel/fiasco/src/kern/mapdb_types.h create mode 100644 kernel/fiasco/src/kern/obj_space_phys_util.cpp create mode 100644 kernel/fiasco/src/kern/obj_space_types.cpp create mode 100644 kernel/fiasco/src/kern/obj_space_virt_util.cpp create mode 100644 kernel/fiasco/src/kern/timer_tick-broadcast.cpp create mode 100644 kernel/fiasco/src/lib/libk/cxx/bitfield create mode 100644 kernel/fiasco/src/lib/libk/cxx/bits/list_basics.h create mode 100644 kernel/fiasco/src/lib/libk/cxx/cxx_int create mode 100644 kernel/fiasco/src/lib/libk/cxx/dlist create mode 100644 kernel/fiasco/src/lib/libk/cxx/hlist create mode 100644 kernel/fiasco/src/lib/libk/cxx/slist create mode 100644 kernel/fiasco/src/lib/libk/cxx/type_list create mode 100644 kernel/fiasco/src/lib/libk/cxx/type_traits create mode 100644 kernel/fiasco/src/lib/libk/cxx/union create mode 100644 kernel/fiasco/src/templates/globalconfig.out.arm-a9-mp-vexpress-1 create mode 100644 kernel/fiasco/src/templates/globalconfig.out.arm-a9-mp-vexpress-2 create mode 100644 kernel/fiasco/src/templates/globalconfig.out.ppc32-1 create mode 100644 kernel/fiasco/src/templates/globalconfig.out.sparc-1 create mode 100755 kernel/fiasco/src/test/unit/map_util_t.out.verify.vf create mode 100644 kernel/fiasco/src/test/unit/mapdb_t.out.verify.vf create mode 100644 l4/mk/platforms/rpi_a.conf create mode 100644 l4/mk/platforms/rpi_b.conf create mode 100644 l4/mk/platforms/rv_vexpress_a15.conf create mode 100644 l4/pkg/bootstrap/server/src/Makefile.platform create mode 100644 l4/pkg/bootstrap/server/src/platform/exynos.cc create mode 100644 l4/pkg/bootstrap/server/src/platform/rpi.cc create mode 100644 l4/pkg/cxx/lib/tl/include/bitfield create mode 100644 l4/pkg/cxx/lib/tl/include/type_list create mode 100644 l4/pkg/cxx/lib/tl/include/utils create mode 100644 l4/pkg/libpng/lib/dist/scripts/dfn.awk create mode 100644 l4/pkg/libpng/lib/dist/test-driver diff --git a/kernel/fiasco/Makefile b/kernel/fiasco/Makefile index 05566909b..234711484 100644 --- a/kernel/fiasco/Makefile +++ b/kernel/fiasco/Makefile @@ -90,7 +90,7 @@ fiasco: fiasco.builddir.create $(MAKE) -C $(DFLBUILDDIR) -j$(PL) checkallseq: - error=0; \ + @error=0; \ $(RM) -r $(ALLBUILDDIR); \ for X in $(TEST_TEMPLATES); do \ echo -e "\n= Building configuration: $$X\n\n"; \ @@ -116,7 +116,7 @@ checkall l4check: .PHONY: dobuildparallel checkallp dobuildparallel: $(addprefix $(ALLBUILDDIR)/,$(TEST_TEMPLATES)) - error=0; \ + @error=0; \ echo "======================================================"; \ for d in $(TEST_TEMPLATES); do \ if [ -e $(ALLBUILDDIR)/$$d/build.failed ]; then \ @@ -137,7 +137,7 @@ $(addprefix $(ALLBUILDDIR)/,$(TEST_TEMPLATES)): $(MAKE) -C $@ 2>&1 | tee $@/build.log; \ if [ $${PIPESTATUS[0]} = 0 ]; \ then [ -z "$(KEEP_BUILD_DIRS)" ] && $(RM) -r $@; \ - else echo $${PIPESTATUS[0]} > $@/build.failed; fi + else echo $${PIPESTATUS[0]} > $@/build.failed; fi; true list: @echo "Templates:" diff --git a/kernel/fiasco/src/Kconfig b/kernel/fiasco/src/Kconfig index f6e98c5d8..b79185acc 100644 --- a/kernel/fiasco/src/Kconfig +++ b/kernel/fiasco/src/Kconfig @@ -85,7 +85,7 @@ config ABI_VF config PF_ARM_MP_CAPABLE bool - default y if ARM_MPCORE || ARM_CORTEX_A9 + default y if ARM_MPCORE || ARM_CORTEX_A7 || ARM_CORTEX_A9 || ARM_CORTEX_A15 config CAN_ARM_CPU_SA1100 bool @@ -108,12 +108,21 @@ config CAN_ARM_CPU_1176 config CAN_ARM_CPU_MPCORE bool +config CAN_ARM_CPU_CORTEX_A5 + bool + +config CAN_ARM_CPU_CORTEX_A7 + bool + config CAN_ARM_CPU_CORTEX_A8 bool config CAN_ARM_CPU_CORTEX_A9 bool +config CAN_ARM_CPU_CORTEX_A15 + bool + config CAN_ARM_CACHE_L2CXX0 bool @@ -153,6 +162,14 @@ config ARM_MPCORE bool "ARM MPCore CPU" depends on CAN_ARM_CPU_MPCORE +config ARM_CORTEX_A5 + bool "ARM Cortex-A5 CPU" + depends on CAN_ARM_CPU_CORTEX_A5 + +config ARM_CORTEX_A7 + bool "ARM Cortex-A7 CPU" + depends on CAN_ARM_CPU_CORTEX_A7 + config ARM_CORTEX_A8 bool "ARM Cortex-A8 CPU" depends on CAN_ARM_CPU_CORTEX_A8 @@ -161,6 +178,10 @@ config ARM_CORTEX_A9 bool "ARM Cortex-A9 CPU" depends on CAN_ARM_CPU_CORTEX_A9 +config ARM_CORTEX_A15 + bool "ARM Cortex-A15 CPU" + depends on CAN_ARM_CPU_CORTEX_A15 + config IA32_486 bool "Intel 80486" depends on IA32 @@ -278,8 +299,6 @@ config LEON3 Choose this if you have a LEON3 CPU. endchoice - - config CPU_VIRT bool "Enable CPU virtualization (SVM and VT)" depends on PF_PC @@ -294,19 +313,50 @@ config ARM_ALIGNMENT_CHECK help Enable if you want to have alignment check enabled. -config ARM_TZ - bool "Enable ARM TrustZone support" - depends on (ARM_1176 || ARM_CORTEX_A8 || ARM_CORTEX_A9) && EXPERIMENTAL +choice + prompt "Execution Model" + default ARM_EM_STD + depends on ARM + +config ARM_EM_STD + bool "Standard mode" help - Support ARM TrustZone security extension. + Systems without ARM TrustZone support, or no specific TrustZone + support. -config ARM_CA9_ENABLE_SWP +config ARM_EM_NS + bool "TrustZone normal side" + depends on ARM_1176 || ARM_CORTEX_A7 || ARM_CORTEX_A8 || ARM_CORTEX_A9 || ARM_CORTEX_A15 + help + In a system with ARM TrustZone extension, run on the normal side. + +config ARM_EM_TZ + bool "TrustZone secure side" + depends on ARM_1176 || ARM_CORTEX_A7 || ARM_CORTEX_A8 || ARM_CORTEX_A9 || ARM_CORTEX_A15 + help + In a system with ARM TrustZone extension, run on the secure side, + and allow monitor services. + +endchoice + +config ARM_SECMONIF_MC + bool + depends on ARM_EM_NS + default y + +config ARM_ENABLE_SWP bool "Enable the deprecated 'swp' instruction" - depends on ARM_CORTEX_A9 + depends on ARM_CORTEX_A9 || ARM_CORTEX_A15 || ARM_CORTEX_A7 || ARM_CORTEX_A5 help Enabling this option enables the deprecated 'swp' instruction. Avoid to enable it. +config ARM_LPAE + bool "Use LPAE page table format" + depends on ARM_CORTEX_A15 || ARM_CORTEX_A7 + help + Use the extended page table format (LPAE). + config ARM_CACHE_L2CXX0 bool "Enable L2 Cache" default y @@ -402,7 +452,7 @@ config ARM_1176_CACHE_ALIAS_FIX config ARM_CPU_ERRATA bool "Enable CPU errata workarounds" - depends on ARM && !ARM_TZ + depends on ARM endmenu # target @@ -410,7 +460,7 @@ menu "Kernel options" config MP bool "Enable multi processor support" - depends on (PF_PC || PF_ARM_MP_CAPABLE || (PF_UX && EXPERIMENTAL)) + depends on (PF_PC || PF_ARM_MP_CAPABLE) && !PF_UX help Enable support for machines with multiple processors. @@ -510,8 +560,14 @@ endchoice config DISABLE_VIRT_OBJ_SPACE bool "No virtually mapped array for cap tables" - depends on (PF_PC || ARM) && EXPERIMENTAL - default n + depends on (PF_PC || (ARM && !CPU_VIRT)) && EXPERIMENTAL + +config VIRT_OBJ_SPACE + def_bool y + depends on !DISABLE_VIRT_OBJ_SPACE + depends on !(CPU_VIRT && ARM) + depends on !ARM || (ARM_V6PLUS && (!ARM_1176 || ARM_1176_CACHE_ALIAS_FIX)) + endmenu # kernel options @@ -624,16 +680,14 @@ config JDB_LOGGING config JDB_DISASM bool "JDB disassembler" - default n if ARM - default y + default y if !ARM help Add support for disassembly. Increases memory foot-print, only enable when needed. config JDB_GZIP bool "GZIP compressed dumps" - default n if ARM - default y + default y if !ARM help Add supprt for gzip compressed dumps of the trace buffer. Increases memory foot-print, only enabled when needed. @@ -755,7 +809,8 @@ config ARM_V6 def_bool y if ARM_1136 || ARM_1176 || ARM_MPCORE config ARM_V7 - def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9 + def_bool y if ARM_CORTEX_A8 || ARM_CORTEX_A9 \ + || ARM_CORTEX_A5 || ARM_CORTEX_A7 || ARM_CORTEX_A15 config ARM_V6PLUS def_bool y if ARM_V6 || ARM_V7 diff --git a/kernel/fiasco/src/Makeconf.amd64 b/kernel/fiasco/src/Makeconf.amd64 index 1853672eb..3f32d0dcf 100644 --- a/kernel/fiasco/src/Makeconf.amd64 +++ b/kernel/fiasco/src/Makeconf.amd64 @@ -20,6 +20,8 @@ SHARED_FLAGS += $(call CHECKCC,-mno-mmx,) SHARED_FLAGS += $(call CHECKCC,-mno-sse,) SHARED_FLAGS += $(call CHECKCC,-mno-sse2,) SHARED_FLAGS += $(call CHECKCC,-mno-sse3,) +SHARED_FLAGS += $(call CHECKCC,-mno-sse4,) +SHARED_FLAGS += $(call CHECKCC,-mno-sse4a,) SHARED_FLAGS += $(call CHECKCC,-mno-3dnow,) ASFLAGS += -m64 -mcmodel=kernel diff --git a/kernel/fiasco/src/Makeconf.arm b/kernel/fiasco/src/Makeconf.arm index 43bfbfe5d..3d5c9e2c9 100644 --- a/kernel/fiasco/src/Makeconf.arm +++ b/kernel/fiasco/src/Makeconf.arm @@ -8,10 +8,13 @@ SHARED_FLAGS-$(CONFIG_ARM_926) += -mcpu=arm926ej-s SHARED_FLAGS-$(CONFIG_ARM_1136) += -mcpu=arm1136jf-s SHARED_FLAGS-$(CONFIG_ARM_1176) += -mcpu=arm1176jzf-s SHARED_FLAGS-$(CONFIG_ARM_MPCORE) += -mcpu=mpcore +SHARED_FLAGS-$(CONFIG_ARM_CORTEX_A5) += $(call CHECKCC,-mcpu=cortex-a5) +SHARED_FLAGS-$(CONFIG_ARM_CORTEX_A7) += $(call CHECKCC,-mcpu=cortex-a7,-mcpu=cortex-a9) SHARED_FLAGS-$(CONFIG_ARM_CORTEX_A8) += $(call CHECKCC,-mcpu=cortex-a8) SHARED_FLAGS-$(CONFIG_ARM_CORTEX_A9) += $(call CHECKCC,-mcpu=cortex-a9) +SHARED_FLAGS-$(CONFIG_ARM_CORTEX_A15) += $(call CHECKCC,-mcpu=cortex-a15,-mcpu=cortex-a9) SHARED_FLAGS += -msoft-float SHARED_FLAGS += $(call CHECKCC,-mno-thumb-interwork) -SHARED_FLAGS += -marm -mabi=apcs-gnu +SHARED_FLAGS += -marm -mabi=aapcs LDFLAGS += --no-warn-mismatch LD_EMULATION_CHOICE := armelf armelf_linux_eabi armelf_fbsd diff --git a/kernel/fiasco/src/Makeconf.ia32 b/kernel/fiasco/src/Makeconf.ia32 index 7635ee320..7a7057ecc 100644 --- a/kernel/fiasco/src/Makeconf.ia32 +++ b/kernel/fiasco/src/Makeconf.ia32 @@ -33,6 +33,8 @@ SHARED_FLAGS += $(call CHECKCC,-mno-mmx,) SHARED_FLAGS += $(call CHECKCC,-mno-sse,) SHARED_FLAGS += $(call CHECKCC,-mno-sse2,) SHARED_FLAGS += $(call CHECKCC,-mno-sse3,) +SHARED_FLAGS += $(call CHECKCC,-mno-sse4,) +SHARED_FLAGS += $(call CHECKCC,-mno-sse4a,) SHARED_FLAGS += $(call CHECKCC,-mno-3dnow,) ASFLAGS += -m32 diff --git a/kernel/fiasco/src/Makefile b/kernel/fiasco/src/Makefile index 4d157d3be..428b9a056 100644 --- a/kernel/fiasco/src/Makefile +++ b/kernel/fiasco/src/Makefile @@ -4,7 +4,8 @@ tooldir := $(srcdir)/../tool CONFIG_BANNER_STRING ?= "Fiasco - prepare for world domination" .PHONY: all do-all test-all config textconfig menuconfig xconfig \ - oldconfig regenconfig mrproper doc help update nconfig + oldconfig regenconfig mrproper doc help update nconfig \ + savedefconfig listnewconfig oldnoconfig oldaskconfig all: @@ -213,6 +214,12 @@ textconfig: $(KCONFIG_FILE) menuconfig oldconfig xconfig gconfig nconfig randconfig allyesconfig allnoconfig: $(KCONFIG_FILE) +$(kconfig_call) $@ silentoldconfig +listnewconfig oldnoconfig savedefconfig: $(KCONFIG_FILE) + +$(kconfig_call) $@ + +oldaskconfig: $(KCONFIG_FILE) + +$(kconfig_call) config + ifneq ($(filter clean cleanall mrproper,$(MAKECMDGOALS)),) # Try to suck in clean targets from subsystems' Makefile fragments diff --git a/kernel/fiasco/src/Makerules.UNITTEST b/kernel/fiasco/src/Makerules.UNITTEST index d6ce5b0a3..9cb4b185f 100644 --- a/kernel/fiasco/src/Makerules.UNITTEST +++ b/kernel/fiasco/src/Makerules.UNITTEST @@ -87,12 +87,13 @@ $(ALL_TESTS): %: %.o @echo "Linking test $@" $(VERBOSE)$(CXX) -m32 -Wl,-Tkernel.ux.lds,--gc-sections \ -static $(CXXFLAGS) $(LDFLAGS) $(PROF_FLAGS) $(OPT_CXXFLAGS) \ - $(filter-out kernel.ux.lds,$^) -o $@ $(TEST_LIB) + $(filter-out kernel.ux.lds,$^) -o $@ $(TEST_LIB) -lutil %.ok: % ifeq ($(SYSTEM_TARGET)$(CONFIG_XARCH),ux) # Test execution for non-cross UX builds @echo -n "Running test $* ... " - @./$< --test --quiet > $*.out + @./$< --test --quiet > $*.out.full + @grep "^\[UTEST\]" $*.out.full > $*.out ifeq ($(RECREATE_OUTPUT),1) @cp $*.out $(srcdir)/test/unit/$*.out.verify.$(CONFIG_ABI) endif # RECREATE_OUTPUT diff --git a/kernel/fiasco/src/Makerules.global b/kernel/fiasco/src/Makerules.global index 85a21d4a8..e0f1c3409 100644 --- a/kernel/fiasco/src/Makerules.global +++ b/kernel/fiasco/src/Makerules.global @@ -116,7 +116,7 @@ $(NONDEBUG_C:.c=.S) : %.S: %.c %.o: %.cc $(COMP_MESSAGE) $(VERBOSE)$(CXX) -c -MD -MP -MF .$*.cc.d.new -o $@ \ - $(CPPFLAGS) $(CXXFLAGS) $(PROF_FLAGS) $(OPT_CXXFLAGS) $< + $(CPPFLAGS) $(CXXFLAGS) $(PROF_FLAGS) $(OPT_CXXFLAGS) $(CXXFLAGS_$(basename $(notdir $@))) $< @mv .$*.cc.d.new .$*.cc.d %.S: %.cc @@ -157,7 +157,7 @@ $(NONDEBUG_C:.c=.S) : %.S: %.c %.lds: %.ld $(COMP_MESSAGE) - $(VERBOSE)$(CPP) -undef -P -DASSEMBLER -o $@ $(CPPFLAGS) $< + $(VERBOSE)$(CPP) -MD -MP -MF .$*.ld.d -undef -P -DASSEMBLER -o $@ $(CPPFLAGS) $< (%): % $(AR_MESSAGE) diff --git a/kernel/fiasco/src/Modules.amd64 b/kernel/fiasco/src/Modules.amd64 index ff3963d44..77656164c 100644 --- a/kernel/fiasco/src/Modules.amd64 +++ b/kernel/fiasco/src/Modules.amd64 @@ -14,11 +14,6 @@ PREPROCESS_PARTS += arch $(CONFIG_ABI) 64bit iofp \ i8259 pc i8254 fpu \ auto_map_kip io -OBJ_SPACE-y = phys -OBJ_SPACE- = virt -OBJ_SPACE = $(OBJ_SPACE-$(CONFIG_DISABLE_VIRT_OBJ_SPACE)) - -PREPROCESS_PARTS += obj_space_$(OBJ_SPACE) PREPROCESS_PARTS-$(CONFIG_MP) += mp PREPROCESS_PARTS-$(CONFIG_LIST_ALLOC_SANITY) += list_alloc_debug @@ -30,7 +25,7 @@ PREPROCESS_PARTS-$(CONFIG_SCHED_HPET) += hpet_timer PREPROCESS_PARTS-$(CONFIG_SERIAL) += serial 16550 PREPROCESS_PARTS-$(CONFIG_WATCHDOG) += watchdog PREPROCESS_PARTS-$(CONFIG_PERF_CNT) += perf_cnt -PREPROCESS_PARTS-$(CONFIG_CPU_VIRT) += svm vmx +PREPROCESS_PARTS-$(CONFIG_CPU_VIRT) += svm vmx virtual_space_iface PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO) += sched_fixed_prio PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ) += sched_wfq PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ) += sched_fp_wfq @@ -94,7 +89,7 @@ INTERFACES_KERNEL += __main acpi io_apic irq_chip_ia32 irq_chip_pic \ boot_console x86desc gdt idt tss timer_irq \ dirq -INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx +INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx vm_vmx_ept apic_IMPL := apic-ia32 apic-ia32-mp @@ -122,7 +117,6 @@ map_util_IMPL := map_util map_util-mem map_util-io map_util-objs mem_layout_IMPL := mem_layout mem_layout-ia32 mem_layout-ia32-64 mem_space_IMPL := mem_space mem_space-user mem_space-ia32 mem_unit_IMPL := mem_unit-amd64 -obj_space_IMPL := obj_space obj_space-$(OBJ_SPACE) paging_IMPL := paging-ia32-64 paging-ia32 paging perf_cnt_IMPL := perf_cnt perf_cnt-ia32 pic_IMPL := pic pic-i8259 @@ -167,6 +161,7 @@ ifeq ("$(CONFIG_SCHED_APIC)","y") endif ifeq ("$(CONFIG_SCHED_HPET)","y") timer_IMPL += timer-hpet + timer_tick_IMPL += timer_tick-single-vector timer_tick-ia32 INTERFACES_KERNEL += hpet endif @@ -266,7 +261,7 @@ ASSRC_CRT0 := crt0.S # # BOOT subsystem # -BOOT := main +BOOT := fiasco VPATH += boot/$(CONFIG_XARCH) boot PRIVATE_INCDIR += boot boot/amd64 CXXSRC_BOOT := boot_libc_glue.cc bootstrap.cc boot_cpu.cc \ diff --git a/kernel/fiasco/src/Modules.arm b/kernel/fiasco/src/Modules.arm index a8c05489f..2e75b027b 100644 --- a/kernel/fiasco/src/Modules.arm +++ b/kernel/fiasco/src/Modules.arm @@ -9,7 +9,7 @@ SUBSYSTEMS := ABI KERNEL LIBK DRIVERS MINILIBC \ PREPROCESS_PARTS += arch $(CONFIG_ABI) 32bit $(CONFIG_XARCH) \ - h3800 noncont_mem abs_syscalls + h3800 abs_syscalls PREPROCESS_PARTS-$(CONFIG_SERIAL) += serial PREPROCESS_PARTS-$(CONFIG_MP) += mp @@ -27,29 +27,26 @@ PREPROCESS_PARTS-$(CONFIG_ARM_V7) += armv7 PREPROCESS_PARTS-$(CONFIG_ARM_1136) += arm1136 PREPROCESS_PARTS-$(CONFIG_ARM_1176) += arm1176 PREPROCESS_PARTS-$(CONFIG_ARM_MPCORE) += mpcore +PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A7) += armca9 PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A8) += armca8 PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A9) += armca9 -PREPROCESS_PARTS-$(CONFIG_ARM_TZ) += tz +PREPROCESS_PARTS-$(CONFIG_ARM_CORTEX_A15) += armca9 +PREPROCESS_PARTS-$(CONFIG_ARM_EM_TZ) += arm_em_tz +PREPROCESS_PARTS-$(CONFIG_ARM_EM_STD) += arm_em_std +PREPROCESS_PARTS-$(CONFIG_ARM_EM_NS) += arm_em_ns +PREPROCESS_PARTS-$(CONFIG_ARM_SECMONIF_MC) += arm_smif_mc +PREPROCESS_PARTS-$(CONFIG_ARM_SECMONIF_LP) += arm_smif_lp +PREPROCESS_PARTS-$(CONFIG_ARM_SECMONIF_TL) += arm_smif_tl PREPROCESS_PARTS-$(CONFIG_ARM_1176_CACHE_ALIAS_FIX) += arm1176_cache_alias_fix PREPROCESS_PARTS-$(CONFIG_ARM_CPU_ERRATA) += arm_cpu_errata PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO) += sched_fixed_prio PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ) += sched_wfq PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ) += sched_fp_wfq +PREPROCESS_PARTS-$(CONFIG_ARM_LPAE) += arm_lpae +PREPROCESS_PARTS-$(CONFIG_CPU_VIRT) += hyp +PREPROCESS_PARTS-y$(CONFIG_CPU_VIRT) += noncont_mem -OBJ_SPACE-y = phys -OBJ_SPACE- = virt -OBJ_SPACE = $(OBJ_SPACE-$(CONFIG_DISABLE_VIRT_OBJ_SPACE)) - - -ifeq ("$(CONFIG_ARM_1176)@$(CONFIG_ARM_1176_CACHE_ALIAS_FIX)","y@") -OBJ_SPACE_TYPE = phys -else -OBJ_SPACE_TYPE = $(if $(CONFIG_ARM_V6PLUS),$(OBJ_SPACE),phys) -endif - -PREPROCESS_PARTS += obj_space_$(OBJ_SPACE_TYPE) - # # TYPES subsystem # @@ -137,24 +134,24 @@ kip_IMPL := kip kip-debug kip-arm # KERNEL subsystem # KERNEL := fiasco -KERNEL_EXTRA := Symbols +KERNEL_EXTRA := Symbols kernel.arm.lds VPATH += kern/$(CONFIG_XARCH) kern VPATH += jdb/arm jdb PRIVATE_INCDIR += kern/$(CONFIG_XARCH) kern -INTERFACES_KERNEL += __main mem_op pagetable kmem_space boot_uart_init \ +INTERFACES_KERNEL += __main mem_op kmem_space boot_uart_init \ irq_chip_generic bootstrap kern_lib_page \ jdb_extensions outer_cache utcb_support cascade_irq \ - irq_mgr_multi_chip + irq_mgr_multi_chip scu INTERFACES_KERNEL-$(CONFIG_SERIAL) += uart_console -INTERFACES_KERNEL-$(CONFIG_ARM_TZ) += vm +INTERFACES_KERNEL-$(CONFIG_ARM_EM_TZ) += vm -INTERFACES_KERNEL += $(INTERFACES_KERNEL-y) boot_info_IMPL := boot_info boot_info-arch bootstrap_IMPL := bootstrap +CXXFLAGS_bootstrap := -O3 clock_IMPL := clock config_IMPL := config config-arm context_IMPL := context context-arm context-vcpu @@ -174,14 +171,13 @@ mapping_IMPL := mapping-arm mapping mem_layout_IMPL := mem_layout mem_layout-arm mem_layout-noncont mem_space_IMPL := mem_space mem_space-arm mem_space-user kmem_alloc_IMPL := kmem_alloc kmem_alloc-arm -obj_space_IMPL := obj_space obj_space-$(OBJ_SPACE_TYPE) outer_cache_IMPL := outer_cache outer_cache-l2cxx0 -pagetable_IMPL := pagetable pagetable-arch paging_IMPL := paging-arm paging perf_cnt_IMPL := perf_cnt perf_cnt-arm pic_IMPL := pic sched_context_IMPL := sched_context-wfq sched_context-fixed_prio \ sched_context-fp_wfq sched_context +scu_IMPL := scu space_IMPL := space space-arm spin_lock_IMPL := spin_lock spin_lock-arm startup_IMPL := startup startup-arm @@ -196,6 +192,7 @@ timer_tick_IMPL := timer_tick timer_tick-arm utcb_init_IMPL := utcb_init utcb_init-arm utcb_support_IMPL := utcb_support utcb_support-arm vmem_alloc_IMPL := vmem_alloc vmem_alloc-arch +vm_factory_IMPL := vm_factory vm_factory-arm tb_entry_IMPL := tb_entry tb_entry-arm vcpu_IMPL := vcpu vcpu-arm @@ -245,12 +242,12 @@ ifneq ($(CONFIG_JDB_GZIP),) endif endif -INTERFACES_JDB += $(INTERFACES_JDB-y) endif CXXSRC_KERNEL := kernel_panic.cc libc_backend_lock.cc ASSRC_KERNEL := ivt.S $(if $(CONFIG_MP),tramp-mp.S) CPPFLAGS += $(if $(CONFIG_MP),-DMPCORE_PHYS_BASE=$(MPCORE_PHYS_BASE)) +CPPFLAGS += -DRAM_PHYS_BASE=$(RAM_PHYS_BASE) NOOPT += $(filter jdb%,\ $(foreach in,$(INTERFACES_KERNEL), \ @@ -323,11 +320,15 @@ endif include $(MODULES_FILE_BSP) VPATH += kern/arm/bsp/$(BSP_NAME) PREPROCESS_PARTS += $(PREPROCESS_PARTS-y) +INTERFACES_KERNEL += $(INTERFACES_KERNEL-y) +INTERFACES_JDB += $(INTERFACES_JDB-y) ifeq ("$(filter LIBUART, $(SUBSYSTEMS))","LIBUART") LIBUART := uart/libuart.a endif +CONFIG_KERNEL_LOAD_ADDR := $(RAM_PHYS_BASE) + ifneq ($(CONFIG_MP),) ifeq ($(MPCORE_PHYS_BASE),) $(error $(MODULES_FILE_BSP) needs to set MPCORE_PHYS_BASE variable) diff --git a/kernel/fiasco/src/Modules.generic b/kernel/fiasco/src/Modules.generic index 3ef2df7c5..c652594fd 100644 --- a/kernel/fiasco/src/Modules.generic +++ b/kernel/fiasco/src/Modules.generic @@ -4,6 +4,7 @@ INTERFACES_KERNEL := cpu_mask rcupdate kobject_mapdb context_base \ mapping spin_lock mapping_tree mappable \ dbg_page_info mapdb pic kobject_dbg koptions \ kobject_iface kobject ready_queue_wfq \ + obj_space_types obj_space_phys_util \ ready_queue_fp obj_space ptab_base ram_quota \ ref_ptr ref_obj mem_space space \ vlog kmem kmem_alloc slab_cache mem_layout \ @@ -25,6 +26,13 @@ INTERFACES_KERNEL := cpu_mask rcupdate kobject_mapdb context_base \ buddy_alloc vkey kdb_ke prio_list ipi scheduler \ clock vm_factory sys_call_page boot_alloc +OBJ_SPACE_TYPE = $(if $(CONFIG_VIRT_OBJ_SPACE),virt,phys) +PREPROCESS_PARTS-y$(CONFIG_VIRT_OBJ_SPACE) = obj_space_phys +PREPROCESS_PARTS += obj_space_$(OBJ_SPACE_TYPE) +INTERFACES_KERNEL-$(CONFIG_VIRT_OBJ_SPACE) += obj_space_virt_util +obj_space_IMPL = obj_space obj_space-$(OBJ_SPACE_TYPE) + + platform_control_IMPL := platform_control syscalls_IMPL := syscalls syscalls-log diff --git a/kernel/fiasco/src/Modules.ia32 b/kernel/fiasco/src/Modules.ia32 index a790224e7..d67205a49 100644 --- a/kernel/fiasco/src/Modules.ia32 +++ b/kernel/fiasco/src/Modules.ia32 @@ -14,12 +14,6 @@ PREPROCESS_PARTS += arch $(CONFIG_ABI) 32bit iofp \ i8259 pc i8254 fpu \ abs_syscalls auto_map_kip io -OBJ_SPACE-y = phys -OBJ_SPACE- = virt -OBJ_SPACE = $(OBJ_SPACE-$(CONFIG_DISABLE_VIRT_OBJ_SPACE)) - -PREPROCESS_PARTS += obj_space_$(OBJ_SPACE) - PREPROCESS_PARTS-$(CONFIG_MP) += mp PREPROCESS_PARTS-$(CONFIG_LIST_ALLOC_SANITY) += list_alloc_debug PREPROCESS_PARTS-$(CONFIG_JDB) += debug log @@ -30,7 +24,7 @@ PREPROCESS_PARTS-$(CONFIG_SCHED_HPET) += hpet_timer PREPROCESS_PARTS-$(CONFIG_SERIAL) += serial 16550 PREPROCESS_PARTS-$(CONFIG_WATCHDOG) += watchdog PREPROCESS_PARTS-$(CONFIG_PERF_CNT) += perf_cnt -PREPROCESS_PARTS-$(CONFIG_CPU_VIRT) += svm vmx +PREPROCESS_PARTS-$(CONFIG_CPU_VIRT) += svm vmx virtual_space_iface PREPROCESS_PARTS-$(CONFIG_SCHED_FIXED_PRIO) += sched_fixed_prio PREPROCESS_PARTS-$(CONFIG_SCHED_WFQ) += sched_wfq PREPROCESS_PARTS-$(CONFIG_SCHED_FP_WFQ) += sched_fp_wfq @@ -94,7 +88,7 @@ INTERFACES_KERNEL += __main acpi irq_chip_ia32 irq_chip_pic io_apic \ io_space apic pit checksum x86desc gdt idt tss \ timer_irq dirq -INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx +INTERFACES_KERNEL-$(CONFIG_CPU_VIRT) += svm vmx vm vm_svm vm_vmx vm_vmx_ept apic_IMPL := apic-ia32 apic-ia32-mp boot_console_IMPL := boot_console-ia32-amd64 @@ -121,7 +115,6 @@ map_util_IMPL := map_util map_util-mem map_util-io map_util-objs mem_layout_IMPL := mem_layout mem_layout-ia32 mem_layout-ia32-32 mem_space_IMPL := mem_space mem_space-user mem_space-ia32 mem_unit_IMPL := mem_unit-ia32 -obj_space_IMPL := obj_space obj_space-$(OBJ_SPACE) paging_IMPL := paging-ia32-32 paging-ia32 paging perf_cnt_IMPL := perf_cnt perf_cnt-ia32 pic_IMPL := pic pic-i8259 @@ -267,7 +260,7 @@ ASSRC_CRT0 := crt0.S # # BOOT subsystem # -BOOT := main +BOOT := fiasco VPATH += boot/$(CONFIG_XARCH) boot PRIVATE_INCDIR += boot boot/ia32 CXXSRC_BOOT := boot_libc_glue.cc bootstrap.cc boot_cpu.cc \ diff --git a/kernel/fiasco/src/Modules.ux b/kernel/fiasco/src/Modules.ux index 1c6294eca..cbf0155a7 100644 --- a/kernel/fiasco/src/Modules.ux +++ b/kernel/fiasco/src/Modules.ux @@ -96,9 +96,10 @@ INTERFACES_KERNEL := mem_region simpleio kernel_console panic warn \ sched_context switch_lock timer timeout \ obj_space kobject_dbg kobject kobject_iface \ l4_buf_iter lock \ + obj_space_types obj_space_phys_util \ mem_space space vcpu context \ helping_lock \ - mp_lock ipc_gate irq_controller \ + mp_lock \ mapping mapping_tree mappable \ mapdb kobject_mapdb map_util \ hostproc task sigma0_task kernel_task prio_list \ @@ -106,7 +107,7 @@ INTERFACES_KERNEL := mem_region simpleio kernel_console panic warn \ ipc_timeout thread_state \ sender receiver ipc_sender thread thread_object \ kobject_helper timer_tick platform_control \ - syscalls \ + syscalls ipc_gate irq_controller \ kernel_thread dirq irq_chip irq_mgr \ irq_chip_ia32 irq_chip_pic \ banner fpu_alloc irq icu_helper main \ @@ -335,7 +336,7 @@ endif # UNITTEST subsystem # # disabled until unittests fixed -ifeq (1,2) +ifeq (0,1) SUBSYSTEMS += UNITTEST VPATH += test/unit diff --git a/kernel/fiasco/src/abi/kip.cpp b/kernel/fiasco/src/abi/kip.cpp index 346574bc8..0a6e4e4c5 100644 --- a/kernel/fiasco/src/abi/kip.cpp +++ b/kernel/fiasco/src/abi/kip.cpp @@ -147,7 +147,7 @@ void Kip::init_global_kip(Kip *kip) global_kip = kip; // check that the KIP has actually been set up - assert(kip->sigma0_ip && kip->root_ip && kip->user_ptr); + //assert(kip->sigma0_ip && kip->root_ip && kip->user_ptr); } PUBLIC static inline Kip *Kip::k() { return global_kip; } diff --git a/kernel/fiasco/src/abi/l4_buf_desc.cpp b/kernel/fiasco/src/abi/l4_buf_desc.cpp index b157a4ff1..dd45bef1f 100644 --- a/kernel/fiasco/src/abi/l4_buf_desc.cpp +++ b/kernel/fiasco/src/abi/l4_buf_desc.cpp @@ -1,7 +1,7 @@ INTERFACE: #include "types.h" -#include +#include /** * Description of the mapping buffer registers contained in the UTCB diff --git a/kernel/fiasco/src/abi/l4_fpage.cpp b/kernel/fiasco/src/abi/l4_fpage.cpp index 4c774a9e9..4e06cd21f 100644 --- a/kernel/fiasco/src/abi/l4_fpage.cpp +++ b/kernel/fiasco/src/abi/l4_fpage.cpp @@ -1,8 +1,17 @@ INTERFACE: #include "types.h" +#include +#include -#include +/// Difference between two capability indexes +typedef cxx::int_type_order Cap_diff; + +/// A capability index +typedef cxx::int_type_full Cap_index; + +/// IA32 I/O port numbers +typedef cxx::int_type_order Port_number; /** * A L4 flex page. @@ -57,17 +66,95 @@ public: enum { Addr_shift = 12 }; + struct Rights + : cxx::int_type_base, + cxx::int_bit_ops, + cxx::int_null_chk + { + Rights() = default; + explicit Rights(unsigned char v) + : cxx::int_type_base(v) {} + + Rights apply(Rights r) const { return *this & r; } + + /// Memory flex page is user accessible + static Rights U() { return Rights(8); } + + /// Memory flex page is readable + static Rights R() { return Rights(4); } + + /// Memory flex page is writable + static Rights W() { return Rights(2); } + + /// Memory flex page is executable (often equal to #R) + static Rights X() { return Rights(1); } + + static Rights UR() { return U() | R(); } + static Rights URX() { return U() | R() | X(); } + static Rights URWX() { return U() | R() | W() | X(); } + static Rights URW() { return U() | R() | W(); } + + /// Memory flex page is readable and executable + static Rights RX() { return R() | X(); } + + /// Memory flex page is readable, writeable, and executable + static Rights RWX() { return R() | W() | X(); } + + /// Memory flex page is readable and writable + static Rights RW() { return R() | W(); } + + ///< Memory flex page is writable and executable + static Rights WX() { return W() | X(); } + + + /// Object flex page: delete rights + static Rights CD() { return Rights(0x8); } + + /// Object flex page: read rights (w/o this the mapping is not present) + static Rights CR() { return Rights(0x4); } + + /** Object flex page: strong semantics (object specific, i.e. not having + * this right on an IPC gate demotes all capabilities transferred via this + * IPC gate to also suffer this right. */ + static Rights CS() { return Rights(0x2); } + + /// Object flex page: write rights (purely object specific) + static Rights CW() { return Rights(0x1); } + + /// Object flex page: combine #CR and #CW + static Rights CRW() { return CR() | CW(); } + + /// Object flex page: combine #CR and #CS + static Rights CRS() { return CR() | CS(); } + + /// Object flex page: combine #CR, #CW, and #CS + static Rights CRWS() { return CRW() | CS(); } + + /// Object flex page: combine #CS and #CW + static Rights CWS() { return CW() | CS(); } + + /// Object flex page: combine #CS, #CW, and #CD + static Rights CWSD() { return CW() | CS() | CD(); } + + /// Object flex page: combine #CR, #CW, #CS, and #CD + static Rights CRWSD() { return CRWS() | CD(); } + + /// All rights shall be transferred, independent of the type + static Rights FULL() { return Rights(0xf); } + }; + private: /** * Create a flex page with the given parameters. */ L4_fpage(Type type, Mword address, unsigned char order, - unsigned char rights) - : _raw( address | rights_bfm_t::val_dirty(rights) + Rights rights) + : _raw( address | _rights_bfm_t::val_dirty(cxx::int_value(rights)) | order_bfm_t::val_dirty(order) | type_bfm_t::val_dirty(type)) {} public: + enum { Whole_space = 63 ///< Value to use as \a order for a whole address space. @@ -83,7 +170,7 @@ public: * \param order the order of the I/O flex page, size is 2^\a order ports. */ static L4_fpage io(Mword port, unsigned char order) - { return L4_fpage(Io, adr_bfm_t::val_dirty(port), order, 0); } + { return L4_fpage(Io, adr_bfm_t::val_dirty(port), order, Rights(0)); } /** * Create an object flex page. @@ -93,7 +180,7 @@ public: * \param order The size of the flex page is 2^\a order. The value in \a idx * must be aligned to 2^(\a order + #Addr_shift. */ - static L4_fpage obj(Mword idx, unsigned char order, unsigned char rights = 0) + static L4_fpage obj(Mword idx, unsigned char order, Rights rights = Rights(0)) { return L4_fpage(Obj, idx & adr_bfm_t::Mask, order, rights); } /** @@ -103,7 +190,7 @@ public: * considered, bits from 0 to \a order-1 are dropped. * \param order The size of the flex page is 2^\a order in bytes. */ - static L4_fpage mem(Mword addr, unsigned char order, unsigned char rights = 0) + static L4_fpage mem(Mword addr, unsigned char order, Rights rights = Rights(0)) { return L4_fpage(Memory, addr & adr_bfm_t::Mask, order, rights); } /** @@ -117,7 +204,7 @@ public: * all available address spaces at once. This is used * for page-fault and exception IPC. */ - static L4_fpage all_spaces(unsigned char rights = 0) + static L4_fpage all_spaces(Rights rights = Rights(0)) { return L4_fpage(Special, 0, Whole_space, rights); } /** @@ -154,7 +241,7 @@ public: * \pre type() must return #Io to return a valid value. * \return The I/O-port index of this flex page. */ - Mword io_address() const { return adr(); } + Port_number io_address() const { return (Port_number)(unsigned)adr(); } /** * Get the capability index of an object flex page. @@ -164,7 +251,7 @@ public: * This value is shifted #Addr_shift to be a real index * (opposed to obj_address()). */ - Mword obj_index() const { return adr(); } + Cap_index obj_index() const { return Cap_index((Mword)adr()); } /** * Test for memory flex page (if type() is #Memory). @@ -209,10 +296,10 @@ public: private: Raw _raw; -public: - /** \name Rights of the flex page */ - CXX_BITFIELD_MEMBER( 0, 3, rights, _raw); + CXX_BITFIELD_MEMBER( 0, 3, _rights, _raw); + +public: /** \name Type of the flex page */ CXX_BITFIELD_MEMBER( 4, 5, type, _raw); /** \name Size (as power of 2) of the flex page */ @@ -222,6 +309,9 @@ private: CXX_BITFIELD_MEMBER(12, MWORD_BITS-1, adr, _raw); public: + + Rights rights() const { return Rights(_rights()); } + /** * Rights bits for flex pages. * @@ -231,40 +321,13 @@ public: * there are #CD, #CR, #CS, and #CW rights on the object and additional * rights in the map control value of the map operation (see L4_fpage::Obj_map_ctl). */ - enum Rights - { - R = 4, ///< Memory flex page is readable - W = 2, ///< Memory flex page is writable - X = 1, ///< Memory flex page is executable (often equal to #R) - - RX = R | X, ///< Memory flex page is readable and executable - RWX = R | W | X, ///< Memory flex page is readable, writeable, and executable - RW = R | W, ///< Memory flex page is readable and writable - WX = W | X, ///< Memory flex page is writable and executable - - - CD = 0x8, ///< Object flex page: delete rights - CR = 0x4, ///< Object flex page: read rights (w/o this the mapping is not present) - CS = 0x2, ///< Object flex page: strong semantics (object specific, i.e. not having - /// this right on an IPC gate demotes all capabilities transferred via this - /// IPC gate to also suffer this right. - CW = 0x1, ///< Object flex page: write rights (purely object specific) - - CRW = CR | CW, ///< Object flex page: combine #CR and #CW - CRS = CR | CS, ///< Object flex page: combine #CR and #CS - CRWS = CRW | CS, ///< Object flex page: combine #CR, #CW, and #CS - CWS = CW | CS, ///< Object flex page: combine #CS and #CW - CWSD = CW | CS | CD, ///< Object flex page: combine #CS, #CW, and #CD - CRWSD = CRWS | CD, ///< Object flex page: combine #CR, #CW, #CS, and #CD - - FULL = 0xf, ///< All rights shall be transferred, independent of the type - }; + /** * Remove the given rights from this flex page. * \param r the rights to remove. The semantics depend on the * type (type()) of the flex page. */ - void mask_rights(Rights r) { _raw &= (Mword(r) | ~rights_bfm_t::Mask); } + void mask_rights(Rights r) { _raw &= (Mword(cxx::int_value(r)) | ~_rights_bfm_t::Mask); } }; diff --git a/kernel/fiasco/src/abi/l4_msg_item.cpp b/kernel/fiasco/src/abi/l4_msg_item.cpp index a5df29e44..6d537dc83 100644 --- a/kernel/fiasco/src/abi/l4_msg_item.cpp +++ b/kernel/fiasco/src/abi/l4_msg_item.cpp @@ -2,7 +2,7 @@ INTERFACE: #include "types.h" #include "l4_fpage.h" -#include +#include /** * The first word of a message item, either a send item or a receive buffer. @@ -93,14 +93,22 @@ public: * * These flags are to control the caching attributes of memory mappings. */ - enum Memory_attribs + struct Memory_type + : cxx::int_type_base, + cxx::int_bit_ops { - Caching_opt = 0x10, ///< This flag denotes the presence of a cachability option - Cached = 0x30, ///< Map the memory cachable - Buffered = 0x50, ///< Map the memory bufferable (write combining in Intel speech) - Uncached = 0x10, ///< Map the memory fully uncachable + Memory_type() = default; + explicit Memory_type(unsigned char v) + : cxx::int_type_base(v) {} + + static Memory_type Set() { return Memory_type(0x10); } + static Memory_type Normal() { return Memory_type(0x20); } + static Memory_type Buffered() { return Memory_type(0x40); } + static Memory_type Uncached() { return Memory_type(0x00); } }; + Memory_type mem_type() const { return Memory_type(attr() & 0x70); } + enum Type { Map = 8, @@ -167,7 +175,8 @@ public: * \return the flex page (L4_fpage) representing the single * object slot with index index(). */ - L4_fpage get_small_buf() { return L4_fpage::obj(_raw, 0, attr() >> 4); } + L4_fpage get_small_buf() + { return L4_fpage::obj(_raw, 0, L4_fpage::Rights(attr() >> 4)); } /** * Create a map item. diff --git a/kernel/fiasco/src/abi/l4_types.cpp b/kernel/fiasco/src/abi/l4_types.cpp index 6c629e194..7da85c282 100644 --- a/kernel/fiasco/src/abi/l4_types.cpp +++ b/kernel/fiasco/src/abi/l4_types.cpp @@ -223,7 +223,7 @@ public: * \return The index into the capability table stored in the capability * selector (i.e., the most significant bits of the selector). */ - unsigned long cap() const { return _raw >> 12; } + Cap_index cap() const { return Cap_index(_raw >> 12); } /** * Get the operation stored in this selector (see L4_obj_ref::Operation). @@ -245,6 +245,8 @@ public: * \param op the operation to be encoded in bits 0..3. */ explicit L4_obj_ref(Mword cap, Operation op = None) : _raw(cap | op) {} + explicit L4_obj_ref(Cap_index cap, Operation op = None) + : _raw((cxx::int_value(cap) << L4_obj_ref::Cap_shift) | op) {} /** * Create a capability selector (index 0) with the given operation. @@ -582,8 +584,11 @@ private: Mword _w; public: - Mword offset() const { return (_w & 0x00ffffff) & (~0 << granularity()); } - Mword granularity() const { return (_w >> 24) & (MWORD_BITS-1) ; } + Order granularity() const + { return Order((_w >> 24) & (MWORD_BITS-1)) ; } + + Cpu_number offset() const + { return cxx::mask_lsb(Cpu_number(_w & 0x00ffffff), granularity()); } }; class L4_cpu_set : public L4_cpu_set_descr @@ -592,33 +597,33 @@ private: Mword _map; public: - bool contains(unsigned cpu) const + bool contains(Cpu_number cpu) const { if (offset() > cpu) return false; cpu -= offset(); cpu >>= granularity(); - if (cpu >= MWORD_BITS) + if (cpu >= Cpu_number(MWORD_BITS)) return false; - return _map & (1UL << cpu); + return (_map >> cxx::int_value(cpu)) & 1; } template - Mword first(MAP const &bm, unsigned max) const + Cpu_number first(MAP const &bm, Cpu_number max) const { - unsigned cpu = offset(); + Cpu_number cpu = offset(); for (;;) { - unsigned b = (cpu - offset()) >> granularity(); - if (cpu >= max || b >= MWORD_BITS) + Cpu_number b = (cpu - offset()) >> granularity(); + if (cpu >= max || b >= Cpu_number(MWORD_BITS)) return max; - if (!(_map & (1UL << b))) + if (!((_map >> cxx::int_value(b)) & 1)) { - cpu += 1UL << granularity(); + cpu += Cpu_number(1) << granularity(); continue; } diff --git a/kernel/fiasco/src/boot/amd64/Makerules.BOOT.amd64 b/kernel/fiasco/src/boot/amd64/Makerules.BOOT.amd64 index cdafb985e..2039c3a33 100644 --- a/kernel/fiasco/src/boot/amd64/Makerules.BOOT.amd64 +++ b/kernel/fiasco/src/boot/amd64/Makerules.BOOT.amd64 @@ -30,8 +30,9 @@ $(KERNEL): kernel.amd64.lds boot_img.o $(CRT0) $(OBJ_KERNEL) $(JDB) $(LIBK) $(KE $(VERBOSE)$(LD) -m elf_x86_64 -N -T $< -gc-sections \ -o $@ $(filter-out $<,$+) $(LIBGCC) $(KERNEL_UNRES_SYMS) +# '$(RM) main' should be removed later - Late 2012 $(BOOT): $(KERNEL) $(LINK_MESSAGE) $(VERBOSE)$(STRIP) -o $@ $< $(VERBOSE)chmod 755 $@ - $(VERBOSE)ln -sf $@ fiasco + $(VERBOSE)$(RM) main diff --git a/kernel/fiasco/src/boot/amd64/boot_cpu.cc b/kernel/fiasco/src/boot/amd64/boot_cpu.cc index 1d4a6c05a..162131840 100644 --- a/kernel/fiasco/src/boot/amd64/boot_cpu.cc +++ b/kernel/fiasco/src/boot/amd64/boot_cpu.cc @@ -221,7 +221,7 @@ extern inline Unsigned16 get_ss() extern inline void enable_longmode() -{ Proc::efer(Proc::efer() | Proc::Efer_lme_flag); } +{ Proc::efer(Proc::efer() | Proc::Efer_lme_flag | Proc::Efer_nxe_flag); } static inline void fill_descriptor(struct x86_desc *desc, Unsigned32 base, Unsigned32 limit, diff --git a/kernel/fiasco/src/boot/amd64/boot_paging.h b/kernel/fiasco/src/boot/amd64/boot_paging.h index 0e4230671..a84891334 100644 --- a/kernel/fiasco/src/boot/amd64/boot_paging.h +++ b/kernel/fiasco/src/boot/amd64/boot_paging.h @@ -33,7 +33,4 @@ static inline Address trunc_page(Address x) static inline Address round_page(Address x) { return (x + PAGE_MASK) & ~PAGE_MASK; } -static inline Address round_superpage(Address x) -{ return (x + SUPERPAGE_MASK) & ~SUPERPAGE_MASK; } - #endif diff --git a/kernel/fiasco/src/boot/ia32/Makerules.BOOT.ia32 b/kernel/fiasco/src/boot/ia32/Makerules.BOOT.ia32 index 1eb498aec..3e0600cb1 100644 --- a/kernel/fiasco/src/boot/ia32/Makerules.BOOT.ia32 +++ b/kernel/fiasco/src/boot/ia32/Makerules.BOOT.ia32 @@ -36,8 +36,9 @@ $(KERNEL): kernel.ia32.lds boot_img.o $(CRT0) $(OBJ_KERNEL) $(JDB) $(LIBK) $(KER -T $< -gc-sections $(filter-out $<,$+) \ $(KERNEL_UNRES_SYMS) +# '$(RM) main' should be removed later - Late 2012 $(BOOT): $(KERNEL) $(LINK_MESSAGE) $(VERBOSE)$(STRIP) -o $@ $< $(VERBOSE)chmod 755 $@ - $(VERBOSE)ln -sf $@ fiasco + $(VERBOSE)$(RM) main diff --git a/kernel/fiasco/src/boot/ia32/boot_paging.h b/kernel/fiasco/src/boot/ia32/boot_paging.h index 9e899161a..0f5b50dbc 100644 --- a/kernel/fiasco/src/boot/ia32/boot_paging.h +++ b/kernel/fiasco/src/boot/ia32/boot_paging.h @@ -15,16 +15,10 @@ static inline int superpage_aligned(Address x) { return (x & SUPERPAGE_MASK) == 0; } -static inline Address trunc_superpage(Address x) -{ return x & ~SUPERPAGE_MASK; } - static inline Address trunc_page(Address x) { return x & ~PAGE_MASK; } static inline Address round_page(Address x) { return (x + PAGE_MASK) & ~PAGE_MASK; } -static inline Address round_superpage(Address x) -{ return (x + SUPERPAGE_MASK) & ~SUPERPAGE_MASK; } - #endif diff --git a/kernel/fiasco/src/drivers/arm/mmu-arm.cpp b/kernel/fiasco/src/drivers/arm/mmu-arm.cpp index cf445f3e6..3b2723885 100644 --- a/kernel/fiasco/src/drivers/arm/mmu-arm.cpp +++ b/kernel/fiasco/src/drivers/arm/mmu-arm.cpp @@ -2,20 +2,13 @@ INTERFACE: #include "mem.h" #include "std_macros.h" +#include "processor.h" EXTENSION class Mmu { public: static void btc_flush(); static void btc_inv(); - - enum - { - Cache_line_size = 32, - Cache_line_mask = Cache_line_size - 1, - Icache_line_size = 32, - Icache_line_mask = Icache_line_size - 1, - }; }; //--------------------------------------------------------------------------- @@ -44,6 +37,24 @@ template < unsigned long Flush_area, bool Ram > void Mmu::btc_inv() { asm volatile ("mcr p15, 0, %0, c7, c5, 0" : : "r" (0) : "memory"); } +//----------------------------------------------------------------------------- +IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || pxa || sa1100 || 926 || arm920t)]: + +PUBLIC static inline +template< unsigned long Flush_area, bool Ram > +Mword Mmu::dcache_line_size() +{ + return 32; +} + +PUBLIC static inline +template< unsigned long Flush_area, bool Ram > +Mword +Mmu::icache_line_size() +{ + return 32; +} + // --------------------------------------------------------------------------- IMPLEMENTATION [arm && arm920t]: @@ -84,6 +95,7 @@ IMPLEMENT template< unsigned long Flush_area, bool Ram > FIASCO_NOINLINE void Mmu::inv_dcache(void const *start, void const *end) { + (void)start; (void)end; // clean && invalidate dcache ||| XXX: all #if 1 for (unsigned long index = 0; index < (1 << (32 - 26)); ++index) @@ -95,7 +107,6 @@ FIASCO_NOINLINE void Mmu::inv_dcache(void const *start, void co #endif } - // --------------------------------------------------------------------------- IMPLEMENTATION [arm && (pxa || sa1100 || 926)]: @@ -122,7 +133,7 @@ FIASCO_NOINLINE void Mmu::clean_dcache(void const *start, void " cmp %0, %1 \n" " blo 1b \n" " mcr p15, 0, %0, c7, c10, 4 \n" // drain WB - : : "r" (start), "r" (end), "i" (Cache_line_size) + : : "r" (start), "r" (end), "i" (dcache_line_size()) ); } } @@ -150,7 +161,7 @@ FIASCO_NOINLINE void Mmu::flush_dcache(void const *start, void " cmp %0, %1 \n" " blo 1b \n" " mcr p15, 0, %0, c7, c10, 4 \n" // drain WB - : : "r" (start), "r" (end), "i" (Cache_line_size) + : : "r" (start), "r" (end), "i" (dcache_line_size()) ); } } @@ -166,10 +177,31 @@ FIASCO_NOINLINE void Mmu::inv_dcache(void const *start, void co " add %0, %0, %2 \n" " cmp %0, %1 \n" " blo 1b \n" - : : "r" (start), "r" (end), "i" (Cache_line_size) + : : "r" (start), "r" (end), "i" (dcache_line_size()) ); } +//----------------------------------------------------------------------------- +IMPLEMENTATION [arm && (armca8 || armca9)]: + +PUBLIC static inline +template< unsigned long Flush_area, bool Ram > +Mword Mmu::dcache_line_size() +{ + Mword v; + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 1" : "=r" (v)); + return 4 << ((v >> 16) & 0xf); +} + +PUBLIC static inline +template< unsigned long Flush_area, bool Ram > +Mword Mmu::icache_line_size() +{ + Mword v; + __asm__ __volatile__("mrc p15, 0, %0, c0, c0, 1" : "=r" (v)); + return 4 << (v & 0xf); +} + //----------------------------------------------------------------------------- IMPLEMENTATION [arm && (mpcore || arm1136 || arm1176 || armca8 || armca9)]: @@ -179,15 +211,15 @@ void Mmu::flush_cache(void const *start, void const *end) { __asm__ __volatile__ ( - "1: mcr p15, 0, %[i], c7, c14, 1 \n" - " mcr p15, 0, %[i], c7, c5, 1 \n" + "1: mcr p15, 0, %[i], c7, c14, 1 \n" // DCCIMVAC + " mcr p15, 0, %[i], c7, c5, 1 \n" // ICIMVAU " add %[i], %[i], %[clsz] \n" " cmp %[i], %[end] \n" " blo 1b \n" : [i] "=&r" (start) - : "0" ((unsigned long)start & ~(Cache_line_size - 1)), + : "0" ((unsigned long)start & ~(dcache_line_size() - 1)), [end] "r" (end), - [clsz] "i" (Cache_line_size) + [clsz] "ir" (dcache_line_size()) : "r0", "memory"); btc_inv(); Mem::dsb(); @@ -199,10 +231,10 @@ void Mmu::clean_dcache(void const *va) { Mem::dsb(); __asm__ __volatile__ ( - "mcr p15, 0, %1, c7, c10, 1 \n" // Clean Data Cache Line (using MVA) Register + "mcr p15, 0, %1, c7, c10, 1 \n" // DCCMVAC : : "r" (0), - "r"((unsigned long)va & ~(Cache_line_size - 1)) + "r" ((unsigned long)va & ~(dcache_line_size() - 1)) : "memory"); } @@ -213,14 +245,14 @@ void Mmu::clean_dcache(void const *start, void const *end) Mem::dsb(); __asm__ __volatile__ ( // arm1176 only: " mcrr p15, 0, %2, %1, c12 \n" - "1: mcr p15, 0, %[i], c7, c10, 1 \n" // Clean Data Cache Line (using MVA) Register + "1: mcr p15, 0, %[i], c7, c10, 1 \n" // DCCMVAC " add %[i], %[i], %[clsz] \n" " cmp %[i], %[end] \n" " blo 1b \n" : [i] "=&r" (start) - : "0" ((unsigned long)start & ~(Cache_line_size - 1)), + : "0" ((unsigned long)start & ~(dcache_line_size() - 1)), [end] "r" (end), - [clsz] "i" (Cache_line_size) + [clsz] "ir" (dcache_line_size()) : "memory"); btc_inv(); Mem::dsb(); @@ -237,9 +269,9 @@ void Mmu::flush_dcache(void const *start, void const *end) " cmp %[i], %[end] \n" " blo 1b \n" : [i] "=&r" (start) - : "0" ((unsigned long)start & ~(Cache_line_size - 1)), + : "0" ((unsigned long)start & ~(dcache_line_size() - 1)), [end] "r" (end), - [clsz] "i" (Cache_line_size) + [clsz] "ir" (dcache_line_size()) : "memory"); btc_inv(); Mem::dsb(); @@ -256,9 +288,9 @@ void Mmu::inv_dcache(void const *start, void const *end) " cmp %[i], %[end] \n" " blo 1b \n" : [i] "=&r" (start) - : "0" ((unsigned long)start & ~(Cache_line_size - 1)), + : "0" ((unsigned long)start & ~(dcache_line_size() - 1)), [end] "r" (end), - [clsz] "i" (Cache_line_size) + [clsz] "ir" (dcache_line_size()) : "memory"); btc_inv(); Mem::dsb(); @@ -311,104 +343,96 @@ private: struct set_way_dcache_flush_op { void operator()(Mword v) const - { // clean+inv data cache by set/way - __asm__ __volatile__ - ( "mcr p15, 0, %0, c7, c14, 2" : : "r"(v) : "memory"); + { // DCCISW + asm volatile("mcr p15, 0, %0, c7, c14, 2" : : "r" (v) : "memory"); } }; struct set_way_dcache_clean_op { void operator()(Mword v) const - { // clean data cache by set/way - __asm__ __volatile__ - ( "mcr p15, 0, %0, c7, c10, 2" : : "r"(v) : "memory"); + { // DCCSW + asm volatile("mcr p15, 0, %0, c7, c10, 2" : : "r" (v) : "memory"); } }; -}; -//----------------------------------------------------------------------------- -INTERFACE [arm && armca8]: - -EXTENSION class Mmu -{ - enum + template< typename T > + static void + __attribute__((optimize("no-unroll-loops"))) + set_way_full_loop(T const &f) { - SET_SIZE_16KB = 1 << 12, - SET_SIZE_32KB = 1 << 13, - SET_SIZE = SET_SIZE_32KB, - SET_INCR = 1 << 6, - WAY_INCR = 1 << 30, - WAY_SIZE = 4, - }; + Mem::dmb(); + Mword clidr; + asm volatile("mrc p15, 1, %0, c0, c0, 1" : "=r" (clidr)); + unsigned lvl = (clidr >> 23) & 14; + + for (unsigned cl = 0; cl < lvl; cl += 2) + { + // data cache only + if (((clidr >> (cl + (cl / 2))) & 6) == 0) + continue; + + Mword ccsidr; + { + Proc::Status s = Proc::cli_save(); + asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (cl)); + Mem::isb(); + asm volatile("mrc p15, 1, %0, c0, c0, 0" : "=r" (ccsidr)); + Proc::sti_restore(s); + } + + unsigned assoc = ((ccsidr >> 3) & 0x3ff); + unsigned w_shift = __builtin_clz(assoc); + unsigned set = ((ccsidr >> 13) & 0x7fff); + unsigned log2linelen = (ccsidr & 7) + 4; + do + { + unsigned w = assoc; + do + f((w << w_shift) | (set << log2linelen) | cl); + while (w--); + } + while (set--); + } + + asm volatile("mcr p15, 2, %0, c0, c0, 0" : : "r" (0)); + + btc_inv(); + Mem::dsb(); + Mem::isb(); + } }; //----------------------------------------------------------------------------- -INTERFACE [arm && armca9]: - -EXTENSION class Mmu -{ - enum - { - SET_SIZE_16KB = 1 << 12, - SET_SIZE_32KB = 1 << 13, - SET_SIZE_64KB = 1 << 14, - SET_SIZE = SET_SIZE_32KB, - SET_INCR = 1 << 5, - WAY_INCR = 1 << 30, - WAY_SIZE = 4, - }; - -}; - -//----------------------------------------- IMPLEMENTATION [arm && (armca8 || armca9)]: -PRIVATE -template< unsigned long Flush_area, bool Ram > -template< typename T > -static inline -void Mmu::set_way_full_op(T const &f) -{ - unsigned wv, w; - for (w = 0, wv = 0; w < WAY_SIZE; ++w, wv += WAY_INCR) - for (unsigned s = 0; s < SET_SIZE; s += SET_INCR) - f(wv | s); - btc_inv(); - __asm__ __volatile__ ("dsb; isb"); -} - IMPLEMENT template< unsigned long Flush_area, bool Ram > void Mmu::flush_dcache() { - __asm__ __volatile__("dsb"); - set_way_full_op(set_way_dcache_flush_op()); + Mem::dsb(); + set_way_full_loop(set_way_dcache_flush_op()); } - IMPLEMENT template< unsigned long Flush_area, bool Ram > void Mmu::flush_cache() { - __asm__ __volatile__ ( - " dsb \n" - // Invalidate Entire Instruction Cache Register + BTC - " mcr p15, 0, r0, c7, c5, 0 \n" - : : : "memory"); + Mem::dsb(); + asm volatile("mcr p15, 0, r0, c7, c5, 0 \n" // ICIALLU + "mcr p15, 0, r0, c7, c5, 6 \n" // BPIALL + "mcr p15, 0, r0, c8, c7, 0 \n" // TLBIALL + : : : "memory"); - set_way_full_op(set_way_dcache_flush_op()); + set_way_full_loop(set_way_dcache_flush_op()); } IMPLEMENT template< unsigned long Flush_area, bool Ram > void Mmu::clean_dcache() { - __asm__ __volatile__ ( - " dsb \n" // Drain Synchronization Barrier Register - : : : "memory"); - - set_way_full_op(set_way_dcache_clean_op()); + Mem::dsb(); + set_way_full_loop(set_way_dcache_clean_op()); } //----------------------------------------------------------------------------- @@ -428,7 +452,7 @@ FIASCO_NOINLINE void Mmu::flush_cache() " mcr p15, 0, r0, c7, c7, 0 \n" " mcr p15, 0, r0, c7, c10, 4 \n" // drain WB : "=r" (dummy) - : "r" (Flush_area), "i" (Cache_line_size) + : "r" (Flush_area), "i" (dcache_line_size()) : "r0" ); } @@ -440,12 +464,12 @@ FIASCO_NOINLINE void Mmu::clean_dcache() register Mword dummy; asm volatile ( " add %0, %1, #8192 \n" // 8k flush area - " 1: ldr r0, [%1], %2 \n" // 32 bytes cache line size + " 1: ldr r0, [%1], %2 \n" " teq %1, %0 \n" " bne 1b \n" " mcr p15, 0, r0, c7, c10, 4 \n" // drain WB : "=r" (dummy) - : "r" (Flush_area), "i" (Cache_line_size) + : "r" (Flush_area), "i" (dcache_line_size()) : "r0" ); } @@ -457,20 +481,18 @@ FIASCO_NOINLINE void Mmu::flush_dcache() register Mword dummy; asm volatile ( " add %0, %1, #8192 \n" // 8k flush area - " 1: ldr r0, [%1], %2 \n" // 32 bytes cache line size + " 1: ldr r0, [%1], %2 \n" " teq %1, %0 \n" " bne 1b \n" " mov r0, #0 \n" " mcr p15, 0, r0, c7, c6, 0 \n" // inv D cache " mcr p15, 0, r0, c7, c10, 4 \n" // drain WB : "=r" (dummy) - : "r" (Flush_area), "i" (Cache_line_size) + : "r" (Flush_area), "i" (dcache_line_size()) : "r0" ); - } - //----------------------------------------------------------------------------- IMPLEMENTATION [arm && pxa]: @@ -482,19 +504,19 @@ FIASCO_NOINLINE void Mmu::flush_cache() asm volatile ( // write back data cache - " 1: mcr p15,0,%0,c7,c2,5 \n\t" + " 1: mcr p15, 0, %0, c7, c2, 5 \n\t" " add %0, %0, #32 \n\t" " subs %1, %1, #1 \n\t" " bne 1b \n\t" // drain write buffer - " mcr p15, 0, %0, c7, c7, 0 \n" + " mcr p15, 0, %0, c7, c7, 0 \n\t" " mcr p15, 0, r0, c7, c10, 4 \n\t" : "=r" (dummy1), "=r" (dummy2) : "0" (Flush_area), - "1" (Ram?2048:1024) + "1" (Ram ? 2048 : 1024) ); } @@ -506,7 +528,7 @@ FIASCO_NOINLINE void Mmu::clean_dcache() asm volatile ( // write back data cache - " 1: mcr p15,0,%0,c7,c2,5 \n\t" + " 1: mcr p15, 0, %0, c7, c2, 5 \n\t" " add %0, %0, #32 \n\t" " subs %1, %1, #1 \n\t" " bne 1b \n\t" @@ -517,7 +539,7 @@ FIASCO_NOINLINE void Mmu::clean_dcache() "=r" (dummy2) : "0" (Flush_area), - "1" (Ram?2048:1024) + "1" (Ram ? 2048 : 1024) ); } @@ -529,11 +551,11 @@ FIASCO_NOINLINE void Mmu::flush_dcache() asm volatile ( // write back data cache - " 1: mcr p15,0,%0,c7,c2,5 \n\t" + " 1: mcr p15, 0, %0, c7, c2, 5 \n\t" " add %0, %0, #32 \n\t" " subs %1, %1, #1 \n\t" " bne 1b \n\t" - " mcr p15, 0, %0, c7, c6, 0 \n" // inv D cache + " mcr p15, 0, %0, c7, c6, 0 \n\t" // inv D cache // drain write buffer " mcr p15, 0, r0, c7, c10, 4 \n\t" : @@ -541,7 +563,7 @@ FIASCO_NOINLINE void Mmu::flush_dcache() "=r" (dummy2) : "0" (Flush_area), - "1" (Ram?2048:1024) + "1" (Ram ? 2048 : 1024) ); } @@ -563,7 +585,6 @@ FIASCO_NOINLINE void Mmu::flush_cache() asm volatile("mcr p15,0,%0,c7,c5,0" : : "r" (0) : "memory"); } - IMPLEMENT template< unsigned long Flush_area, bool Ram > FIASCO_NOINLINE void Mmu::clean_dcache() @@ -623,12 +644,10 @@ FIASCO_NOINLINE void Mmu::flush_dcache() // write back data cache "1: mrc p15, 0, r15, c7, c14, 3 \n\t" " bne 1b \n\t" - " mcr p15, 0, %0, c7, c6, 0 \n" // inv D cache + " mcr p15, 0, %0, c7, c6, 0 \n\t" // inv D cache // drain write buffer " mcr p15, 0, %0, c7, c10, 4 \n\t" : : "r" (0) ); } - - diff --git a/kernel/fiasco/src/drivers/arm/processor-arm.cpp b/kernel/fiasco/src/drivers/arm/processor-arm.cpp index d067e37f0..41598371a 100644 --- a/kernel/fiasco/src/drivers/arm/processor-arm.cpp +++ b/kernel/fiasco/src/drivers/arm/processor-arm.cpp @@ -2,44 +2,54 @@ INTERFACE[arm]: EXTENSION class Proc { +private: + enum : unsigned + { + Status_FIQ_disabled = 0x40, + Status_IRQ_disabled = 0x80, + }; + public: - enum + enum : unsigned { Status_mode_user = 0x10, Status_mode_supervisor = 0x13, Status_mode_mask = 0x1f, - Status_FIQ_disabled = 0x40, - Status_IRQ_disabled = 0x80, Status_interrupts_disabled = Status_FIQ_disabled | Status_IRQ_disabled, - Status_interrupts_mask = 0xc0, Status_thumb = 0x20, }; - static unsigned cpu_id(); + static Cpu_phys_id cpu_id(); }; -INTERFACE[arm && !tz]: +INTERFACE[arm && !arm_em_tz]: EXTENSION class Proc { public: - enum + enum : unsigned { - Cli_mask = Status_IRQ_disabled, - Sti_mask = Status_IRQ_disabled, + Cli_mask = Status_interrupts_disabled, + Sti_mask = Status_interrupts_disabled, + Status_preempt_disabled = Status_IRQ_disabled, + Status_interrupts_mask = Status_interrupts_disabled, + Status_always_mask = 0, }; }; -INTERFACE[arm && tz]: +INTERFACE[arm && arm_em_tz]: EXTENSION class Proc { public: - enum + enum : unsigned { - Cli_mask = Status_IRQ_disabled | Status_FIQ_disabled, - Sti_mask = Status_IRQ_disabled | Status_FIQ_disabled, + Cli_mask = Status_FIQ_disabled, + Sti_mask = Status_FIQ_disabled, + Status_preempt_disabled = Status_FIQ_disabled, + Status_interrupts_mask = Status_FIQ_disabled, + Status_always_mask = Status_IRQ_disabled, }; }; @@ -72,33 +82,38 @@ Mword Proc::program_counter() IMPLEMENT static inline void Proc::cli() { - asm volatile ( " mrs r6, cpsr \n" - " orr r6,r6,%0 \n" - " msr cpsr_c, r6 \n" - : : "i" (Cli_mask) : "r6", "memory" - ); + Mword v; + asm volatile("mrs %0, cpsr \n" + "orr %0, %0, %1 \n" + "msr cpsr_c, %0 \n" + : "=r" (v) + : "I" (Cli_mask) + : "memory"); } IMPLEMENT static inline void Proc::sti() { - asm volatile ( " mrs r6, cpsr \n" - " bic r6,r6,%0 \n" - " msr cpsr_c, r6 \n" - : : "i" (Sti_mask) : "r6", "memory" - ); + Mword v; + asm volatile("mrs %0, cpsr \n" + "bic %0, %0, %1 \n" + "msr cpsr_c, %0 \n" + : "=r" (v) + : "I" (Sti_mask) + : "memory"); } IMPLEMENT static inline Proc::Status Proc::cli_save() { Status ret; - asm volatile ( " mrs r6, cpsr \n" - " mov %0, r6 \n" - " orr r6,r6,%1 \n" - " msr cpsr_c, r6 \n" - : "=r"(ret) : "i" (Cli_mask) : "r6" - ); + Mword v; + asm volatile("mrs %0, cpsr \n" + "orr %1, %0, %2 \n" + "msr cpsr_c, %1 \n" + : "=r" (ret), "=r" (v) + : "I" (Cli_mask) + : "memory"); return ret; } @@ -106,23 +121,15 @@ IMPLEMENT static inline Proc::Status Proc::interrupts() { Status ret; - asm volatile (" mrs %0, cpsr \n" - : "=r"(ret) - ); + asm volatile("mrs %0, cpsr" : "=r" (ret)); return !(ret & Sti_mask); } IMPLEMENT static inline void Proc::sti_restore(Status st) { - asm volatile ( " tst %0, %1 \n" - " bne 1f \n" - " mrs r6, cpsr \n" - " bic r6,r6,%1 \n" - " msr cpsr_c, r6 \n" - "1: \n" - : : "r"(st), "i" (Sti_mask) : "r6" - ); + if (!(st & Sti_mask)) + sti(); } IMPLEMENT static inline @@ -136,18 +143,18 @@ void Proc::irq_chance() IMPLEMENTATION[arm && !mp]: IMPLEMENT static inline -unsigned Proc::cpu_id() -{ return 0; } +Cpu_phys_id Proc::cpu_id() +{ return Cpu_phys_id(0); } //---------------------------------------------------------------- IMPLEMENTATION[arm && mp]: IMPLEMENT static inline -unsigned Proc::cpu_id() +Cpu_phys_id Proc::cpu_id() { unsigned mpidr; __asm__("mrc p15, 0, %0, c0, c0, 5": "=r" (mpidr)); - return mpidr & 0x7; // mind gic softirq + return Cpu_phys_id(mpidr & 0x7); // mind gic softirq } //---------------------------------------------------------------- diff --git a/kernel/fiasco/src/drivers/arm/sa1100.cpp b/kernel/fiasco/src/drivers/arm/sa1100.cpp index da67fd755..1d03b6416 100644 --- a/kernel/fiasco/src/drivers/arm/sa1100.cpp +++ b/kernel/fiasco/src/drivers/arm/sa1100.cpp @@ -1,53 +1,35 @@ INTERFACE [sa1100]: #include "types.h" +#include "mmio_register_block.h" -template< unsigned long Hw_regs_base > -class Sa1100_generic +class Sa1100 : public Mmio_register_block { public: enum { - RSRR = Hw_regs_base + 0x030000, + RSRR = 0x030000, /* interrupt controller */ - ICIP = Hw_regs_base + 0x050000, - ICMR = Hw_regs_base + 0x050004, - ICLR = Hw_regs_base + 0x050008, - ICCR = Hw_regs_base + 0x05000c, - ICFP = Hw_regs_base + 0x050010, - ICPR = Hw_regs_base + 0x050020, + ICIP = 0x050000, + ICMR = 0x050004, + ICLR = 0x050008, + ICCR = 0x05000c, + ICFP = 0x050010, + ICPR = 0x050020, /* OS Timer */ - OSMR0 = Hw_regs_base + 0x000000, - OSMR1 = Hw_regs_base + 0x000004, - OSMR2 = Hw_regs_base + 0x000008, - OSMR3 = Hw_regs_base + 0x00000c, - OSCR = Hw_regs_base + 0x000010, - OSSR = Hw_regs_base + 0x000014, - OWER = Hw_regs_base + 0x000018, - OIER = Hw_regs_base + 0x00001c, + OSMR0 = 0x000000, + OSMR1 = 0x000004, + OSMR2 = 0x000008, + OSMR3 = 0x00000c, + OSCR = 0x000010, + OSSR = 0x000014, + OWER = 0x000018, + OIER = 0x00001c, RSRR_SWR = 1, }; - static inline void hw_reg( Mword value, Mword reg ); - static inline Mword hw_reg( Mword reg ); + Sa1100(Address base) : Mmio_register_block(base) {} }; -//--------------------------------------------------------------------------- -IMPLEMENTATION [sa1100]: - -IMPLEMENT inline -template< unsigned long Hw_regs_base > -void Sa1100_generic::hw_reg( Mword value, Mword reg ) -{ - *(Mword volatile*)reg = value; -} - -IMPLEMENT inline -template< unsigned long Hw_regs_base > -Mword Sa1100_generic::hw_reg( Mword reg ) -{ - return *(Mword volatile*)reg; -} - diff --git a/kernel/fiasco/src/drivers/io.cpp b/kernel/fiasco/src/drivers/io.cpp index 412bdb5ab..8530ed528 100644 --- a/kernel/fiasco/src/drivers/io.cpp +++ b/kernel/fiasco/src/drivers/io.cpp @@ -3,7 +3,7 @@ INTERFACE: #include "types.h" /** - * PC I/O port API. + * I/O API. */ class Io { @@ -42,73 +42,77 @@ public: template< typename T > static void set(T setbits, Address address); + /** + * Write ((read(address) & ~disable) | enable) of type T at address. + */ + template< typename T > + static void modify(T enable, T disable, Address address); + /** * Read byte port. */ - static Unsigned8 in8 ( unsigned long port ); + static Unsigned8 in8(unsigned long port); /** * Read 16-bit port. */ - static Unsigned16 in16( unsigned long port ); + static Unsigned16 in16(unsigned long port); /** * Read 32-bit port. */ - static Unsigned32 in32( unsigned long port ); + static Unsigned32 in32(unsigned long port); /** * Write byte port. */ - static void out8 ( Unsigned8 val, unsigned long port ); + static void out8(Unsigned8 val, unsigned long port); /** * Write 16-bit port. */ - static void out16( Unsigned16 val, unsigned long port ); + static void out16(Unsigned16 val, unsigned long port); /** * Write 32-bit port. */ - static void out32( Unsigned32 val, unsigned long port ); + static void out32(Unsigned32 val, unsigned long port); /// @name Delayed versions. - //@{ + //@{ /** * Read 8-bit port. */ - static Unsigned8 in8_p ( unsigned long port ); + static Unsigned8 in8_p(unsigned long port); /** * Read 16-bit port. */ - static Unsigned16 in16_p( unsigned long port ); + static Unsigned16 in16_p(unsigned long port); /** * Read 32-bit port. */ - static Unsigned32 in32_p( unsigned long port ); + static Unsigned32 in32_p(unsigned long port); /** * Write 8-bit port. */ - static void out8_p ( Unsigned8 val, unsigned long port ); + static void out8_p(Unsigned8 val, unsigned long port); /** * Write 16-bit port. */ - static void out16_p( Unsigned16 val, unsigned long port ); + static void out16_p(Unsigned16 val, unsigned long port); /** * Write 32-bit port. */ - static void out32_p( Unsigned32 val, unsigned long port ); + static void out32_p(Unsigned32 val, unsigned long port); //@} - }; - // ---------------------------------------------------------------------- IMPLEMENTATION [!ppc32]: @@ -122,6 +126,7 @@ template< typename T> void Io::write(T value, Address address) { *(volatile T *)address = value; } +// ---------------------------------------------------------------------- IMPLEMENTATION: IMPLEMENT inline @@ -139,7 +144,12 @@ template< typename T> void Io::set(T setbits, Address address) { write(read(address) | setbits, address); } - +IMPLEMENT inline +template< typename T> +void Io::modify(T enable, T disable, Address address) +{ + write((read(address) & ~disable) | enable, address); +} @@ -170,16 +180,20 @@ Unsigned32 Io::in32_p(unsigned long port) IMPLEMENT inline void Io::out8_p(Unsigned8 val, unsigned long port) { - out8(val,port); iodelay(); + out8(val, port); + iodelay(); } IMPLEMENT inline void Io::out16_p(Unsigned16 val, unsigned long port) { - out16(val,port); iodelay(); + out16(val, port); + iodelay(); } + IMPLEMENT inline void Io::out32_p(Unsigned32 val, unsigned long port) { - out32(val,port); iodelay(); + out32(val, port); + iodelay(); } diff --git a/kernel/fiasco/src/drivers/mmio_register_block.h b/kernel/fiasco/src/drivers/mmio_register_block.h new file mode 100644 index 000000000..9657fa594 --- /dev/null +++ b/kernel/fiasco/src/drivers/mmio_register_block.h @@ -0,0 +1,35 @@ +// vi:ft=cpp + +#pragma once + +#include "types.h" + +class Mmio_register_block +{ +public: + Mmio_register_block() {} + explicit Mmio_register_block(Address base) : _base(base) {} + + template< typename T > + void write(T t, Address reg) const + { *reinterpret_cast(_base + reg) = t; } + + template< typename T > + T read(Address reg) const + { return *reinterpret_cast(_base + reg); } + + template< typename T > + void modify(T enable, T disable, Address reg) const + { + Mword tmp = read(reg); + tmp &= ~disable; + tmp |= enable; + write(tmp, reg); + } + + Address get_mmio_base() const { return _base; } + void set_mmio_base(Address base) { _base = base; } + +private: + Address _base; +}; diff --git a/kernel/fiasco/src/drivers/ppc32/processor-ppc32.cpp b/kernel/fiasco/src/drivers/ppc32/processor-ppc32.cpp index 1b04dbf80..2ce99c1b1 100644 --- a/kernel/fiasco/src/drivers/ppc32/processor-ppc32.cpp +++ b/kernel/fiasco/src/drivers/ppc32/processor-ppc32.cpp @@ -8,7 +8,7 @@ EXTENSION class Proc public: //disable power savings mode static Mword wake(Mword); - static unsigned cpu_id(); + static Cpu_phys_id cpu_id(); }; /// Unblock external inetrrupts @@ -112,7 +112,7 @@ Mword Proc::program_counter() IMPLEMENTATION [ppc32 && !mpcore]: IMPLEMENT static inline -unsigned Proc::cpu_id() -{ return 0; } +Cpu_phys_id Proc::cpu_id() +{ return Cpu_phys_id(0); } diff --git a/kernel/fiasco/src/drivers/sparc/processor-sparc.cpp b/kernel/fiasco/src/drivers/sparc/processor-sparc.cpp index 001d0c8f7..b4989c504 100644 --- a/kernel/fiasco/src/drivers/sparc/processor-sparc.cpp +++ b/kernel/fiasco/src/drivers/sparc/processor-sparc.cpp @@ -9,7 +9,7 @@ EXTENSION class Proc public: //disable power savings mode static Mword wake(Mword); - static unsigned cpu_id(); + static Cpu_phys_id cpu_id(); }; /// Unblock external interrupts @@ -135,7 +135,7 @@ void Proc::write_alternative(Mword reg, Mword value) IMPLEMENTATION [sparc && !mpcore]: IMPLEMENT static inline -unsigned Proc::cpu_id() -{ return 0; } +Cpu_phys_id Proc::cpu_id() +{ return Cpu_phys_id(0); } diff --git a/kernel/fiasco/src/drivers/uart-16550.cpp b/kernel/fiasco/src/drivers/uart-16550.cpp index 86e85bca6..35cee60b5 100644 --- a/kernel/fiasco/src/drivers/uart-16550.cpp +++ b/kernel/fiasco/src/drivers/uart-16550.cpp @@ -188,7 +188,7 @@ bool Uart::valid() scratch3 = ier(); ier(scratch); - return (scratch2 == 0x00 && scratch3 == 0x0f); + return scratch2 == 0x00 && scratch3 == 0x0f; } IMPLEMENT @@ -208,9 +208,7 @@ bool Uart::startup(Address _port, int __irq) ier(Base_ier_bits);/* disable all rs-232 interrupts */ mcr(0x0b); /* out2, rts, and dtr enabled */ - fcr(1); /* enable fifo */ - fcr(0x07); /* clear rcv xmit fifo */ - fcr(1); /* enable fifo */ + fcr(7); /* enable and clear rcv+xmit fifo */ lcr(0); /* clear line control register */ /* clearall interrupts */ diff --git a/kernel/fiasco/src/jdb/arm/jdb-arm.cpp b/kernel/fiasco/src/jdb/arm/jdb-arm.cpp index a0ac4c139..0f989b72b 100644 --- a/kernel/fiasco/src/jdb/arm/jdb-arm.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb-arm.cpp @@ -9,6 +9,7 @@ IMPLEMENTATION [arm]: #include "mem_unit.h" #include "static_init.h" #include "watchdog.h" +#include "cxx/cxx_int" STATIC_INITIALIZE_P(Jdb, JDB_INIT_PRIO); @@ -17,41 +18,41 @@ DEFINE_PER_CPU static Per_cpu jdb_irq_state; // disable interrupts before entering the kernel debugger IMPLEMENT void -Jdb::save_disable_irqs(unsigned cpu) +Jdb::save_disable_irqs(Cpu_number cpu) { jdb_irq_state.cpu(cpu) = Proc::cli_save(); - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) Watchdog::disable(); } // restore interrupts after leaving the kernel debugger IMPLEMENT void -Jdb::restore_irqs(unsigned cpu) +Jdb::restore_irqs(Cpu_number cpu) { - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) Watchdog::enable(); Proc::sti_restore(jdb_irq_state.cpu(cpu)); } IMPLEMENT inline void -Jdb::enter_trap_handler(unsigned /*cpu*/) +Jdb::enter_trap_handler(Cpu_number) {} IMPLEMENT inline void -Jdb::leave_trap_handler(unsigned /*cpu*/) +Jdb::leave_trap_handler(Cpu_number) {} PROTECTED static inline void -Jdb::monitor_address(unsigned, void *) +Jdb::monitor_address(Cpu_number, void *) {} IMPLEMENT inline bool -Jdb::handle_conditional_breakpoint(unsigned /*cpu*/) +Jdb::handle_conditional_breakpoint(Cpu_number) { return false; } IMPLEMENT @@ -64,15 +65,15 @@ Jdb::handle_nested_trap(Jdb_entry_frame *e) IMPLEMENT bool -Jdb::handle_debug_traps(unsigned cpu) +Jdb::handle_debug_traps(Cpu_number cpu) { Jdb_entry_frame *ef = entry_frame.cpu(cpu); if (ef->error_code == 0x00e00000) - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), "%s", + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::first())), "%s", (char const *)ef->r[0]); else if (ef->debug_ipi()) - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::first())), "IPI ENTRY"); return true; @@ -80,7 +81,7 @@ Jdb::handle_debug_traps(unsigned cpu) IMPLEMENT inline bool -Jdb::handle_user_request(unsigned cpu) +Jdb::handle_user_request(Cpu_number cpu) { Jdb_entry_frame *ef = Jdb::entry_frame.cpu(cpu); const char *str = (char const *)ef->r[0]; @@ -88,7 +89,7 @@ Jdb::handle_user_request(unsigned cpu) char tmp; if (ef->debug_ipi()) - return cpu != 0; + return cpu != Cpu_number::boot_cpu(); if (ef->error_code == 0x00e00001) return execute_command_ni(task, str); @@ -140,11 +141,11 @@ Jdb::access_mem_task(Address virt, Space * task) { if (Mem_layout::in_kernel(virt)) { - Pte p = Kmem_space::kdir()->walk((void *)virt, 0, false, Ptab::Null_alloc(), 0); - if (!p.valid()) + auto p = Kmem_space::kdir()->walk(Virt_addr(virt)); + if (!p.is_valid()) return 0; - phys = p.phys((void*)virt); + phys = p.page_addr() | cxx::get_lsb(virt, p.page_order()); } else phys = virt; @@ -165,14 +166,17 @@ Jdb::access_mem_task(Address virt, Space * task) if (addr == (Address)-1) { Mem_unit::flush_vdcache(); - Pte pte = static_cast(Kernel_task::kernel_task()) - ->_dir->walk((void*)Mem_layout::Jdb_tmp_map_area, 0, false, Ptab::Null_alloc(), 0); + auto pte = static_cast(Kernel_task::kernel_task()) + ->_dir->walk(Virt_addr(Mem_layout::Jdb_tmp_map_area), Pdir::Super_level); - if (pte.phys() != (phys & ~(Config::SUPERPAGE_SIZE - 1))) - pte.set(phys & ~(Config::SUPERPAGE_SIZE - 1), Config::SUPERPAGE_SIZE, - Mem_page_attr(Page::KERN_RW | Page::CACHEABLE), true); + if (!pte.is_valid() || pte.page_addr() != cxx::mask_lsb(phys, pte.page_order())) + { + pte.create_page(Phys_mem_addr(cxx::mask_lsb(phys, pte.page_order())), + Page::Attr(Page::Rights::RW())); + pte.write_back_if(true); + } - Mem_unit::dtlb_flush(); + Mem_unit::tlb_flush(); addr = Mem_layout::Jdb_tmp_map_area + (phys & (Config::SUPERPAGE_SIZE - 1)); } @@ -295,9 +299,10 @@ IMPLEMENTATION [arm && mp]: static void -Jdb::send_nmi(unsigned cpu) +Jdb::send_nmi(Cpu_number cpu) { - printf("NMI to %d, what's that?\n", cpu); + printf("NMI to %d, what's that?\n", + cxx::int_value(cpu)); } PROTECTED static inline @@ -312,7 +317,7 @@ Jdb::set_monitored_address(T *dest, T val) PROTECTED static inline template< typename T > -T Jdb::monitor_address(unsigned, T volatile *addr) +T Jdb::monitor_address(Cpu_number, T volatile *addr) { asm volatile("wfe"); return *addr; diff --git a/kernel/fiasco/src/jdb/arm/jdb_extensions.cpp b/kernel/fiasco/src/jdb/arm/jdb_extensions.cpp index 0a2b745b7..7f1a48d71 100644 --- a/kernel/fiasco/src/jdb/arm/jdb_extensions.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb_extensions.cpp @@ -136,14 +136,14 @@ static void tbuf(Thread *t, Entry_frame *r) } static void do_cli(Thread *, Entry_frame *r) -{ r->psr |= Proc::Status_IRQ_disabled; } +{ r->psr |= Proc::Status_preempt_disabled; } static void do_sti(Thread *, Entry_frame *r) -{ r->psr &= ~Proc::Status_IRQ_disabled; } +{ r->psr &= ~Proc::Status_preempt_disabled; } static void getcpu(Thread *, Entry_frame *r) { - r->r[0] = current_cpu(); + r->r[0] = cxx::int_value(current_cpu()); } static void init_dbg_extensions() @@ -159,9 +159,13 @@ static void init_dbg_extensions() Thread::dbg_extension[0x09] = &outhex8; Thread::dbg_extension[0x0d] = &inchar; Thread::dbg_extension[0x1d] = &tbuf; - Thread::dbg_extension[0x32] = &do_cli; - Thread::dbg_extension[0x33] = &do_sti; - Thread::dbg_extension[0x34] = &getcpu; + + if (0) + { + Thread::dbg_extension[0x32] = &do_cli; + Thread::dbg_extension[0x33] = &do_sti; + Thread::dbg_extension[0x34] = &getcpu; + } } STATIC_INITIALIZER(init_dbg_extensions); diff --git a/kernel/fiasco/src/jdb/arm/jdb_kern_info-arm.cpp b/kernel/fiasco/src/jdb/arm/jdb_kern_info-arm.cpp index 1c61a1755..3e7260833 100644 --- a/kernel/fiasco/src/jdb/arm/jdb_kern_info-arm.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb_kern_info-arm.cpp @@ -29,7 +29,7 @@ Jdb_kern_info_misc::show() "pdir: %08x\n", (unsigned) (Kip::k()->clock >> 32), (unsigned) (Kip::k()->clock), - (unsigned) Mem_space::current_mem_space(0)->dir()); + (unsigned) Mem_space::current_mem_space(Cpu_number::boot_cpu())->dir()); } diff --git a/kernel/fiasco/src/jdb/arm/jdb_kern_info-bench-arm.cpp b/kernel/fiasco/src/jdb/arm/jdb_kern_info-bench-arm.cpp index 18453b956..f0e1a718e 100644 --- a/kernel/fiasco/src/jdb/arm/jdb_kern_info-bench-arm.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb_kern_info-bench-arm.cpp @@ -12,7 +12,7 @@ IMPLEMENTATION[arm && realview]: IMPLEMENT inline NEEDS["platform.h"] Unsigned64 Jdb_kern_info_bench::get_time_now() -{ return Platform::read(Platform::Sys::Cnt_24mhz); } +{ return Platform::sys->read(Platform::Sys::Cnt_24mhz); } IMPLEMENTATION[arm && !realview]: diff --git a/kernel/fiasco/src/jdb/arm/jdb_ptab-arm.cpp b/kernel/fiasco/src/jdb/arm/jdb_ptab-arm.cpp index cf96fd153..1b5dcbc01 100644 --- a/kernel/fiasco/src/jdb/arm/jdb_ptab-arm.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb_ptab-arm.cpp @@ -3,33 +3,9 @@ IMPLEMENTATION [arm]: #include "paging.h" #include "simpleio.h" -unsigned Jdb_ptab::max_pt_level = 1; - // ----------------------------------------------------------------------- IMPLEMENTATION [arm && armv5]: -IMPLEMENT inline -unsigned -Jdb_ptab::entry_valid(Mword entry, unsigned) -{ return entry & 0x03; } - -IMPLEMENT inline -unsigned -Jdb_ptab::entry_is_pt_ptr(Mword entry, unsigned level, - unsigned *entries, unsigned *next_level) -{ - if (level > 0 || (entry & 0x03) == 0x02) - return 0; - - if ((entry & 0x03) == 0x01) - *entries = 256; // coarse (1KB) - else - *entries = 1024; // fine (4KB) - - *next_level = 1; - return 1; -} - PRIVATE inline bool Jdb_ptab::is_cached(Mword entry, unsigned level) @@ -57,25 +33,7 @@ Jdb_ptab::ap_char(unsigned ap) // ----------------------------------------------------------------------- -IMPLEMENTATION [arm && (armv6 || armv7)]: - -IMPLEMENT inline NEEDS ["paging.h"] -unsigned -Jdb_ptab::entry_valid(Mword entry, unsigned) -{ return (entry & 3) == 1 || (entry & 3) == 2; } - -IMPLEMENT inline -unsigned -Jdb_ptab::entry_is_pt_ptr(Mword entry, unsigned level, - unsigned *entries, unsigned *next_level) -{ - if (level > 0 || (entry & 0x03) == 0x02) - return 0; - - *entries = 256; // coarse (1KB) - *next_level = 1; - return 1; -} +IMPLEMENTATION [arm && (armv6 || armv7) && !arm_lpae]: PRIVATE inline bool @@ -115,68 +73,31 @@ Jdb_ptab::ap_char(unsigned ap) } // ----------------------------------------------------------------------- -IMPLEMENTATION [arm]: - -IMPLEMENT inline NEEDS ["paging.h"] -Address -Jdb_ptab::entry_phys(Mword entry, unsigned level) -{ - unsigned t = entry & 0x03; - if (level == 0) - { - switch(t) - { - default: - case 0: - return 0; - case 1: - return entry & 0xfffffc00; - case 2: - return entry & 0xfff00000; - case 3: - return entry & 0xfffff000; - } - } - else - { - switch (t) - { - default: - case 0: - return 0; - case 1: - return entry & 0xffff0000; - case 2: - return entry & 0xfffff000; - case 3: - return entry & 0xfffffc00; - } - } -} +IMPLEMENTATION [arm && !arm_lpae]: IMPLEMENT void -Jdb_ptab::print_entry(Mword entry, unsigned level) +Jdb_ptab::print_entry(Pte_ptr const &entry) { if (dump_raw) - printf("%08lx", entry); + printf("%08lx", *entry.pte); else { - if (!entry_valid(entry,level)) + if (!entry.is_valid()) { putstr(" - "); return; } - Address phys = entry_phys(entry, level); + Address phys = entry_phys(entry); - unsigned t = entry & 0x03; - unsigned ap = entry >> 4; + unsigned t = *entry.pte & 0x03; + unsigned ap = *entry.pte >> 4; char ps; - if (level == 0) + if (entry.level == 0) switch (t) { case 1: ps = 'C'; break; - case 2: ps = 'S'; ap = entry >> 10; break; + case 2: ps = 'S'; ap = *entry.pte >> 10; break; case 3: ps = 'F'; break; default: ps = 'U'; break; } @@ -190,19 +111,97 @@ Jdb_ptab::print_entry(Mword entry, unsigned level) } printf("%05lx%s%c", phys >> Config::PAGE_SHIFT, - is_cached(entry, level) + is_cached(*entry.pte, entry.level) ? "-" : JDB_ANSI_COLOR(lightblue) "n" JDB_ANSI_END, ps); - if (level == 0 && t != 2) + if (entry.level == 0 && t != 2) putchar('-'); else printf("%s%c" JDB_ANSI_END, - is_executable(entry) ? "" : JDB_ANSI_COLOR(red), + is_executable(*entry.pte) ? "" : JDB_ANSI_COLOR(red), ap_char(ap)); } } -PUBLIC -unsigned long -Jdb_ptab::rows() const -{ return entries/8; } +// ----------------------------------------------------------------------- +IMPLEMENTATION [arm && arm_lpae]: + +PRIVATE inline +bool +Jdb_ptab::is_cached(Pte_ptr const &entry) +{ + if (!entry.is_leaf()) + return true; + return (*entry.pte & Page::Cache_mask) == Page::CACHEABLE; +} + +PRIVATE inline +bool +Jdb_ptab::is_executable(Mword entry) +{ + (void)entry; + return 1; +} + +PRIVATE inline +char +Jdb_ptab::ap_char(Mword entry) +{ + switch ((entry >> 6) & 3) + { + case 0: return 'W'; + case 1: return 'w'; + case 2: return 'R'; + case 3: default: return 'r'; + }; +} + +IMPLEMENT +void +Jdb_ptab::print_entry(Pte_ptr const &entry) +{ + if (dump_raw) + printf("%08lx", (unsigned long)*entry.pte); + else + { + if (!entry.is_valid()) + { + putstr(" - "); + return; + } + Address phys = entry_phys(entry); + + unsigned t = (*entry.pte & 2) >> 1; + + char ps; + if (entry.level == 0) + switch (t) + { + case 0: ps = 'G'; break; + case 1: ps = 'P'; break; + } + else if (entry.level == 1) + switch (t) + { + case 0: ps = 'M'; break; + case 1: ps = 'P'; break; + } + else + switch (t) + { + case 0: ps = '?'; break; + case 1: ps = 'p'; break; + } + + printf("%05lx%s%c", phys >> Config::PAGE_SHIFT, + is_cached(entry) + ? "-" : JDB_ANSI_COLOR(lightblue) "n" JDB_ANSI_END, + ps); + if (!entry.is_leaf()) + putchar('-'); + else + printf("%s%c" JDB_ANSI_END, + is_executable(*entry.pte) ? "" : JDB_ANSI_COLOR(red), + ap_char(*entry.pte)); + } +} diff --git a/kernel/fiasco/src/jdb/arm/jdb_vm.cpp b/kernel/fiasco/src/jdb/arm/jdb_vm.cpp index 1ccf454df..f184e02fa 100644 --- a/kernel/fiasco/src/jdb/arm/jdb_vm.cpp +++ b/kernel/fiasco/src/jdb/arm/jdb_vm.cpp @@ -1,17 +1,10 @@ -IMPLEMENTATION [tz]: +IMPLEMENTATION [arm_em_tz]: -#include #include #include -#include "jdb.h" -#include "jdb_core.h" #include "jdb_module.h" -#include "jdb_screen.h" #include "jdb_kobject.h" -#include "kernel_console.h" -#include "keycodes.h" -#include "simpleio.h" #include "static_init.h" #include "vm.h" @@ -32,7 +25,7 @@ PUBLIC bool Jdb_vm::show_kobject(Kobject_common *o, int lvl) { - Kobject::dcast(o)->dump_machine_state(); + Kobject::dcast(o)->dump_vm_state(); if (lvl) { Jdb::getchar(); @@ -53,15 +46,15 @@ PUBLIC int Jdb_vm::show_kobject_short(char *buf, int max, Kobject_common *o) { - return Kobject::dcast(o)->show_short(buf, max); + return Kobject::dcast(o)->show_short(buf, max); } -static Jdb_vm jdb_vm INIT_PRIORITY(JDB_MODULE_INIT_PRIO); +//static Jdb_vm jdb_vm INIT_PRIORITY(JDB_MODULE_INIT_PRIO); -static -bool -filter_vm(Kobject_common const *o) -{ - return Kobject::dcast(o); -} -static Jdb_kobject_list::Mode INIT_PRIORITY(JDB_MODULE_INIT_PRIO) tnt("[Vms]", filter_vm); +//static +//bool +//filter_vm(Kobject_common const *o) +//{ +// return Kobject::dcast(o); +//} +//static Jdb_kobject_list::Mode INIT_PRIORITY(JDB_MODULE_INIT_PRIO) tnt("[Vms]", filter_vm); diff --git a/kernel/fiasco/src/jdb/ia32/32/jdb_kern_info-bench-ia32-32.cpp b/kernel/fiasco/src/jdb/ia32/32/jdb_kern_info-bench-ia32-32.cpp index 217eadf81..dc7eafba7 100644 --- a/kernel/fiasco/src/jdb/ia32/32/jdb_kern_info-bench-ia32-32.cpp +++ b/kernel/fiasco/src/jdb/ia32/32/jdb_kern_info-bench-ia32-32.cpp @@ -371,7 +371,7 @@ Jdb_kern_info_bench::show_arch() // and do "sysret ; syscall". Gdt doesn't care us since sysret loads a // flat segment. Sysret enables the interrupts again so make sure that // we don't receive a timer interrupt. - Timer_tick::disable(0); + Timer_tick::disable(Cpu_number::boot_cpu()); Proc::sti(); Proc::irq_chance(); asm volatile ("pushf \n\t" @@ -419,7 +419,7 @@ Jdb_kern_info_bench::show_arch() : "i"(Mem_layout::Tbuf_status_page + Config::PAGE_SIZE-2) : "ebx", "ecx", "esi", "edi", "memory"); Proc::cli(); - Timer_tick::enable(0); + Timer_tick::enable(Cpu_number::boot_cpu()); show_time(time, 200000, "syscall + sysret"); } BENCH("push EAX + pop EAX", inst_push_pop, 200000); diff --git a/kernel/fiasco/src/jdb/ia32/64/jdb_ptab-amd64.cpp b/kernel/fiasco/src/jdb/ia32/64/jdb_ptab-amd64.cpp index a3aaa2e20..ac2c8a4bc 100644 --- a/kernel/fiasco/src/jdb/ia32/64/jdb_ptab-amd64.cpp +++ b/kernel/fiasco/src/jdb/ia32/64/jdb_ptab-amd64.cpp @@ -2,104 +2,41 @@ IMPLEMENTATION [amd64]: #include "paging.h" -unsigned Jdb_ptab::max_pt_level = Pdir::Depth; - -IMPLEMENT inline NEEDS ["paging.h"] -unsigned -Jdb_ptab::entry_is_pt_ptr(Mword entry, unsigned level, - unsigned *entries, unsigned *next_level) -{ - if (level > Pdir::Super_level || entry & Pt_entry::Pse_bit) - return 0; - *entries = Ptab::Level::length(level); - *next_level = level+1; - return 1; -} - -IMPLEMENT inline NEEDS ["paging.h"] -Address -Jdb_ptab::entry_phys(Mword entry, unsigned level) -{ - return Ptab::Level::addr(level, entry); -} - -IMPLEMENT inline NEEDS ["paging.h"] -unsigned -Jdb_ptab::entry_valid(Mword entry, unsigned) -{ return entry & Pt_entry::Valid; } - IMPLEMENT void -Jdb_ptab::print_entry(Mword entry, unsigned level) +Jdb_ptab::print_entry(Pdir::Pte_ptr const &entry) { if (dump_raw) { - printf(L4_PTR_FMT, entry); + printf(L4_PTR_FMT, *entry.pte); return; } - if (!entry_valid(entry,level)) + if (!entry.is_valid()) { putstr(" - "); return; } - Address phys = entry_phys(entry, level); + Address phys = entry_phys(entry); - if (level == Pdir::Super_level && entry & Pt_entry::Pse_bit) + if (entry.level != Pdir::Depth && entry.is_leaf()) printf((phys >> 20) > 0xFF ? " %03lx/2" : " %02lx/2", phys >> 20); else printf((phys >> Config::PAGE_SHIFT) > 0xFFFF ? "%13lx" : " %04lx", phys >> Config::PAGE_SHIFT); - putchar(((cur_pt_level>=max_pt_level || (entry & Pt_entry::Pse_bit)) && - (entry & Pt_entry::Cpu_global)) ? '+' : '-'); - printf("%s%c%s", entry & Pt_entry::Noncacheable ? JDB_ANSI_COLOR(lightblue) : "", - entry & Pt_entry::Noncacheable - ? 'n' : (entry & Pt_entry::Write_through) ? 't' : '-', - entry & Pt_entry::Noncacheable ? JDB_ANSI_END : ""); - putchar(entry & Pt_entry::User - ? (entry & Pt_entry::Writable) ? 'w' : 'r' - : (entry & Pt_entry::Writable) ? 'W' : 'R'); + putchar(((cur_pt_level >= Pdir::Depth || entry.is_leaf()) && + (*entry.pte & Pt_entry::Cpu_global)) ? '+' : '-'); + printf("%s%c%s", *entry.pte & Pt_entry::Noncacheable ? JDB_ANSI_COLOR(lightblue) : "", + *entry.pte & Pt_entry::Noncacheable + ? 'n' : (*entry.pte & Pt_entry::Write_through) ? 't' : '-', + *entry.pte & Pt_entry::Noncacheable ? JDB_ANSI_END : ""); + putchar(*entry.pte & Pt_entry::User + ? (*entry.pte & Pt_entry::Writable) ? 'w' : 'r' + : (*entry.pte & Pt_entry::Writable) ? 'W' : 'R'); } -PUBLIC -unsigned long -Jdb_ptab::rows() const -{ return entries/4; } -PRIVATE -Address -Jdb_ptab::disp_virt(unsigned long row, unsigned col) -{ - Pdir::Va e(Mword(col-1) + (Mword(row) * Mword(cols()-1))); - e <<= Ptab::Level::shift(cur_pt_level); - return Virt_addr(e).value() + virt_base; -} -PUBLIC -void -Jdb_ptab::print_statline(unsigned long row, unsigned long col) -{ - if (cur_pt_level == 0) - { - Jdb::printf_statline("pml4", "=mode =goto pdp", - "<" L4_PTR_FMT "> task %p", disp_virt(row,col), _task); - } - else if (cur_pt_level == 1) - { - Jdb::printf_statline("pdp", "=mode =goto pdir", - "<" L4_PTR_FMT "> task %p", disp_virt(row,col), _task); - } - else if (cur_pt_level == 2) - { - Jdb::printf_statline("pdir", "=mode =goto ptab/superpage", - "<" L4_PTR_FMT "> task %p", disp_virt(row,col), _task); - } - else // PT_MODE - { - Jdb::printf_statline("ptab", "=mode =goto page", - "<" L4_PTR_FMT "> task %p", disp_virt(row,col), _task); - } -} diff --git a/kernel/fiasco/src/jdb/ia32/jdb-ia32-amd64.cpp b/kernel/fiasco/src/jdb/ia32/jdb-ia32-amd64.cpp index a81299827..a9145d58e 100644 --- a/kernel/fiasco/src/jdb/ia32/jdb-ia32-amd64.cpp +++ b/kernel/fiasco/src/jdb/ia32/jdb-ia32-amd64.cpp @@ -214,7 +214,7 @@ Jdb::set_monitored_address(T *dest, T val) PROTECTED static inline template< typename T > T -Jdb::monitor_address(unsigned current_cpu, T *addr) +Jdb::monitor_address(Cpu_number current_cpu, T *addr) { if (!*addr && Cpu::cpus.cpu(current_cpu).has_monitor_mwait()) { @@ -227,23 +227,6 @@ Jdb::monitor_address(unsigned current_cpu, T *addr) } -#if 0 -PUBLIC static -template T -Jdb::peek(T const *addr) -{ - return *addr; -} - -PUBLIC static -template T -Jdb::peek(T const *addr, Address_type) -{ - // on IA32 we can touch directly into the user-space - return *(T*)addr; -} -#endif - static inline void Jdb::backspace() @@ -257,19 +240,19 @@ DEFINE_PER_CPU static Per_cpu jdb_saved_flags; // disable interrupts before entering the kernel debugger IMPLEMENT void -Jdb::save_disable_irqs(unsigned cpu) +Jdb::save_disable_irqs(Cpu_number cpu) { if (!jdb_irqs_disabled.cpu(cpu)++) { // save interrupt flags jdb_saved_flags.cpu(cpu) = Proc::cli_save(); - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) { Watchdog::disable(); pic_status = Pic::disable_all_save(); if (Config::getchar_does_hlt_works_ok) - Timer_tick::disable(0); + Timer_tick::disable(Cpu_number::boot_cpu()); } if (Io_apic::active() && Apic::is_present()) { @@ -277,16 +260,16 @@ Jdb::save_disable_irqs(unsigned cpu) Apic::tpr(APIC_IRQ_BASE - 0x10); } - if (cpu == 0 && Config::getchar_does_hlt_works_ok) + if (cpu == Cpu_number::boot_cpu() && Config::getchar_does_hlt_works_ok) { // set timer interrupt does nothing than wakeup from hlt Timer_tick::set_vectors_stop(); - Timer_tick::enable(0); + Timer_tick::enable(Cpu_number::boot_cpu()); } } - if (cpu == 0 && Config::getchar_does_hlt_works_ok) + if (cpu == Cpu_number::boot_cpu() && Config::getchar_does_hlt_works_ok) // explicit enable interrupts because the timer interrupt is // needed to wakeup from "hlt" state in getchar(). All other // interrupts are disabled at the pic. @@ -296,7 +279,7 @@ Jdb::save_disable_irqs(unsigned cpu) // restore interrupts after leaving the kernel debugger IMPLEMENT void -Jdb::restore_irqs(unsigned cpu) +Jdb::restore_irqs(Cpu_number cpu) { if (!--jdb_irqs_disabled.cpu(cpu)) { @@ -305,14 +288,14 @@ Jdb::restore_irqs(unsigned cpu) if (Io_apic::active() && Apic::is_present()) Apic::tpr(apic_tpr.cpu(cpu)); - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) { Pic::restore_all(Jdb::pic_status); Watchdog::enable(); } // reset timer interrupt vector - if (cpu == 0 && Config::getchar_does_hlt_works_ok) + if (cpu == Cpu_number::boot_cpu() && Config::getchar_does_hlt_works_ok) Idt::set_vectors_run(); // reset interrupt flags @@ -325,7 +308,7 @@ struct On_dbg_stack { Mword sp; On_dbg_stack(Mword sp) : sp(sp) {} - bool operator () (unsigned cpu) const + bool operator () (Cpu_number cpu) const { Thread::Dbg_stack const &st = Thread::dbg_stack.cpu(cpu); return sp <= Mword(st.stack_top) @@ -338,7 +321,7 @@ struct On_dbg_stack // context. We _never_ return 0! IMPLEMENT Thread* -Jdb::get_thread(unsigned cpu) +Jdb::get_thread(Cpu_number cpu) { Jdb_entry_frame *entry_frame = Jdb::entry_frame.cpu(cpu); Address sp = (Address) entry_frame; @@ -398,8 +381,8 @@ Jdb::peek_task(Address addr, Space *task, void *value, int width) Address pdbr; asm volatile ("mov %%cr3, %0" : "=r" (pdbr)); Pdir *kdir = (Pdir*)Mem_layout::phys_to_pmem(pdbr); - Pdir::Iter i = kdir->walk(Virt_addr(addr)); - if (i.e->valid()) + auto i = kdir->walk(Virt_addr(addr)); + if (i.is_valid()) { memcpy(value, (void*)addr, width); return 0; @@ -435,8 +418,8 @@ Jdb::poke_task(Address addr, Space *task, void const *value, int width) Address pdbr; asm volatile ("mov %%cr3, %0" : "=r" (pdbr)); Pdir *kdir = (Pdir*)Mem_layout::phys_to_pmem(pdbr); - Pdir::Iter i = kdir->walk(Virt_addr(addr)); - if (i.e->valid()) + auto i = kdir->walk(Virt_addr(addr)); + if (i.is_valid()) { memcpy((void*)addr, value, width); return 0; @@ -557,7 +540,7 @@ Jdb::guess_thread_state(Thread *t) PUBLIC static void -Jdb::set_single_step(unsigned cpu, int on) +Jdb::set_single_step(Cpu_number cpu, int on) { if (on) entry_frame.cpu(cpu)->flags(entry_frame.cpu(cpu)->flags() | EFLAGS_TF); @@ -618,7 +601,7 @@ IMPLEMENTATION[ia32]: // set global indicators code_call, code_ret, code_bra, code_int // This can fail if the current page is still not mapped static void -Jdb::analyze_code(unsigned cpu) +Jdb::analyze_code(Cpu_number cpu) { Jdb_entry_frame *entry_frame = Jdb::entry_frame.cpu(cpu); Space *task = get_task(cpu); @@ -665,14 +648,14 @@ Jdb::analyze_code(unsigned cpu) IMPLEMENTATION[amd64]: static void -Jdb::analyze_code(unsigned) +Jdb::analyze_code(Cpu_number) {} IMPLEMENTATION[ia32,amd64]: // entered debugger because of single step trap static inline NOEXPORT int -Jdb::handle_single_step(unsigned cpu) +Jdb::handle_single_step(Cpu_number cpu) { int really_break = 1; @@ -718,33 +701,33 @@ Jdb::handle_single_step(unsigned cpu) { // condition met ss_state.cpu(cpu) = SS_NONE; - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), "%s", "Branch/Call"); + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())), "%s", "Branch/Call"); } } else // (ss_state == SS_NONE) // regular single_step - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), "%s", "Singlestep"); + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())), "%s", "Singlestep"); return really_break; } // entered debugger due to debug exception static inline NOEXPORT int -Jdb::handle_trap1(unsigned cpu) +Jdb::handle_trap1(Cpu_number cpu) { // FIXME: currently only on bot cpu - if (cpu != 0) + if (cpu != Cpu_number::boot_cpu()) return 0; if (bp_test_sstep && bp_test_sstep()) return handle_single_step(cpu); if (bp_test_break - && bp_test_break(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)))) + && bp_test_break(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())))) return 1; if (bp_test_other - && bp_test_other(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)))) + && bp_test_other(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())))) return 1; return 0; @@ -752,14 +735,14 @@ Jdb::handle_trap1(unsigned cpu) // entered debugger due to software breakpoint static inline NOEXPORT int -Jdb::handle_trap3(unsigned cpu) +Jdb::handle_trap3(Cpu_number cpu) { Jdb_entry_frame *entry_frame = Jdb::entry_frame.cpu(cpu); Space *task = get_task(cpu); Unsigned8 op; Unsigned8 len; - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), "%s", "INT 3"); + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())), "%s", "INT 3"); if ( !peek((Unsigned8*)entry_frame->ip(), task, op) || !peek((Unsigned8*)(entry_frame->ip()+1), task, len) || op != 0xeb) @@ -798,7 +781,7 @@ Jdb::handle_trap3(unsigned cpu) ctrl[i] = tmp; } ctrl[i] = '\0'; - snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(0)), + snprintf(error_buffer.cpu(cpu), sizeof(error_buffer.cpu(Cpu_number::boot_cpu())), "invalid ctrl sequence \"%s\"", ctrl); } } @@ -807,9 +790,9 @@ Jdb::handle_trap3(unsigned cpu) { unsigned i; len = len < 47 ? len : 47; - len = len < sizeof(error_buffer.cpu(0))-1 + len = len < sizeof(error_buffer.cpu(Cpu_number::boot_cpu()))-1 ? len - : sizeof(error_buffer.cpu(0))-1; + : sizeof(error_buffer.cpu(Cpu_number::boot_cpu()))-1; for(i=0; i_trapno)) + 1; - if ( pos < sizeof(error_buffer.cpu(0)) + if ( pos < sizeof(error_buffer.cpu(Cpu_number::boot_cpu())) && entry_frame.cpu(cpu)->_trapno >= 10 && entry_frame.cpu(cpu)->_trapno <= 14) - snprintf(error_buffer.cpu(cpu)+pos, sizeof(error_buffer.cpu(0))-pos, + snprintf(error_buffer.cpu(cpu)+pos, sizeof(error_buffer.cpu(Cpu_number::boot_cpu()))-pos, "(ERR=" L4_PTR_FMT ")", entry_frame.cpu(cpu)->_err); return 1; @@ -840,7 +823,7 @@ Jdb::handle_trapX(unsigned cpu) */ IMPLEMENT bool -Jdb::handle_user_request(unsigned cpu) +Jdb::handle_user_request(Cpu_number cpu) { Jdb_entry_frame *entry_frame = Jdb::entry_frame.cpu(cpu); @@ -905,17 +888,17 @@ Jdb::handle_user_request(unsigned cpu) IMPLEMENT void -Jdb::enter_trap_handler(unsigned cpu) +Jdb::enter_trap_handler(Cpu_number cpu) { Cpu::cpus.cpu(cpu).debugctl_disable(); } IMPLEMENT void -Jdb::leave_trap_handler(unsigned cpu) +Jdb::leave_trap_handler(Cpu_number cpu) { Cpu::cpus.cpu(cpu).debugctl_enable(); } IMPLEMENT bool -Jdb::handle_conditional_breakpoint(unsigned cpu) +Jdb::handle_conditional_breakpoint(Cpu_number cpu) { return entry_frame.cpu(cpu)->_trapno == 1 && bp_test_log_only && bp_test_log_only(); } IMPLEMENT @@ -969,7 +952,7 @@ Jdb::handle_nested_trap(Jdb_entry_frame *e) IMPLEMENT bool -Jdb::handle_debug_traps(unsigned cpu) +Jdb::handle_debug_traps(Cpu_number cpu) { bool really_break = true; @@ -982,7 +965,7 @@ Jdb::handle_debug_traps(unsigned cpu) if (really_break) { - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) { if (!Cpu::online(i) || !running.cpu(i)) continue; @@ -1015,7 +998,7 @@ IMPLEMENTATION [(ia32 || amd64) && mp]: static void -Jdb::send_nmi(unsigned cpu) +Jdb::send_nmi(Cpu_number cpu) { Apic::mp_send_ipi(Apic::apic.cpu(cpu)->apic_id(), 0, Apic::APIC_IPI_NMI); } diff --git a/kernel/fiasco/src/jdb/ia32/jdb_bp-ia32-ux.cpp b/kernel/fiasco/src/jdb/ia32/jdb_bp-ia32-ux.cpp index 94ffab90b..a81801a59 100644 --- a/kernel/fiasco/src/jdb/ia32/jdb_bp-ia32-ux.cpp +++ b/kernel/fiasco/src/jdb/ia32/jdb_bp-ia32-ux.cpp @@ -493,8 +493,8 @@ PUBLIC static int Jdb_bp::test_break(Mword dr6, char *errbuf, size_t bufsize) { - Thread *t = Jdb::get_thread(0); - Jdb_entry_frame *e = Jdb::get_entry_frame(0); + Thread *t = Jdb::get_thread(Cpu_number::boot_cpu()); + Jdb_entry_frame *e = Jdb::get_entry_frame(Cpu_number::boot_cpu()); for (int i=0; i<4; i++) if (dr6 & (1<sp(); tcb = (Mword)is_current.c; - printf("\n current on cpu %u\n", is_current.cpu); + printf("\n current on cpu %u\n", + cxx::int_value(is_current.cpu)); } else { diff --git a/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-amd64.cpp b/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-amd64.cpp index 6135c2473..64bcb4441 100644 --- a/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-amd64.cpp +++ b/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-amd64.cpp @@ -289,14 +289,14 @@ Jdb_kern_info_gdt::Jdb_kern_info_gdt() PRIVATE static void -Jdb_kern_info_gdt::show_gdt(unsigned cpu) +Jdb_kern_info_gdt::show_gdt(Cpu_number cpu) { Gdt *gdt = Cpu::cpus.cpu(cpu).get_gdt(); unsigned entries = Gdt::gdt_max / 8; if (Config::Max_num_cpus > 1) printf("CPU%d: GDT base=" L4_PTR_FMT " limit=%04x (%04x bytes)\n", - cpu, (Mword)gdt, entries, Gdt::gdt_max); + cxx::int_value(cpu), (Mword)gdt, entries, Gdt::gdt_max); else printf("GDT base=" L4_PTR_FMT " limit=%04x (%04x bytes)\n", (Mword)gdt, entries, Gdt::gdt_max); diff --git a/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-ux.cpp b/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-ux.cpp index 28cb9c02f..662428078 100644 --- a/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-ux.cpp +++ b/kernel/fiasco/src/jdb/ia32/jdb_kern_info-ia32-ux.cpp @@ -136,7 +136,7 @@ PRIVATE inline NEEDS["jdb_screen.h"] void Jdb_kern_info_misc::show_pdir() { - Mem_space *s = Mem_space::current_mem_space(0); + Mem_space *s = Mem_space::current_mem_space(Cpu_number::boot_cpu()); printf("%s" L4_PTR_FMT "\n", Jdb_screen::Root_page_table, (Address)s->dir()); } diff --git a/kernel/fiasco/src/jdb/ia32/jdb_trace_set-ia32-ux.cpp b/kernel/fiasco/src/jdb/ia32/jdb_trace_set-ia32-ux.cpp index d6de9b71f..21881f42d 100644 --- a/kernel/fiasco/src/jdb/ia32/jdb_trace_set-ia32-ux.cpp +++ b/kernel/fiasco/src/jdb/ia32/jdb_trace_set-ia32-ux.cpp @@ -19,7 +19,7 @@ typedef void (Fast_entry_func)(void); PUBLIC static void -Jdb_set_trace::ia32_set_fast_entry(unsigned cpu, void *entry) +Jdb_set_trace::ia32_set_fast_entry(Cpu_number cpu, void *entry) { Cpu::cpus.cpu(cpu).set_fast_entry((Fast_entry_func*)entry); } @@ -28,7 +28,7 @@ struct Set_fast_entry { void *entry; Set_fast_entry(Fast_entry_func *entry) : entry((void*)entry) {} - void operator () (unsigned cpu) const + void operator () (Cpu_number cpu) const { Jdb::remote_work(cpu, Jdb_set_trace::ia32_set_fast_entry, entry, true); } }; diff --git a/kernel/fiasco/src/jdb/jdb-thread.cpp b/kernel/fiasco/src/jdb/jdb-thread.cpp index e02e84a79..d4fc08fda 100644 --- a/kernel/fiasco/src/jdb/jdb-thread.cpp +++ b/kernel/fiasco/src/jdb/jdb-thread.cpp @@ -9,7 +9,7 @@ public: * Deliver Thread object which was active at entry of kernel debugger. * If we came from the kernel itself, return Thread with id 0.0 */ - static Thread *get_thread(unsigned cpu); + static Thread *get_thread(Cpu_number cpu); }; //--------------------------------------------------------------------------- @@ -50,7 +50,7 @@ IMPLEMENTATION [arm || ux || ppc32 || sparc]: IMPLEMENT Thread * -Jdb::get_thread(unsigned cpu) +Jdb::get_thread(Cpu_number cpu) { Jdb_entry_frame *c = get_entry_frame(cpu); @@ -65,7 +65,7 @@ IMPLEMENTATION: PUBLIC static void -Jdb::get_current(unsigned cpu) +Jdb::get_current(Cpu_number cpu) { current_active = get_thread(cpu); } diff --git a/kernel/fiasco/src/jdb/jdb.cpp b/kernel/fiasco/src/jdb/jdb.cpp index e56339701..6a944eec3 100644 --- a/kernel/fiasco/src/jdb/jdb.cpp +++ b/kernel/fiasco/src/jdb/jdb.cpp @@ -15,19 +15,19 @@ class Jdb : public Jdb_core { public: static Per_cpu entry_frame; - static unsigned current_cpu; - static Per_cpu remote_func; + static Cpu_number current_cpu; + static Per_cpu remote_func; static Per_cpu remote_func_data; static Per_cpu remote_func_running; - static int FIASCO_FASTCALL enter_jdb(Jdb_entry_frame *e, unsigned cpu); + static int FIASCO_FASTCALL enter_jdb(Jdb_entry_frame *e, Cpu_number cpu); static void cursor_end_of_screen(); static void cursor_home(); static void printf_statline(const char *prompt, const char *help, const char *format, ...) __attribute__((format(printf, 3, 4))); - static void save_disable_irqs(unsigned cpu); - static void restore_irqs(unsigned cpu); + static void save_disable_irqs(Cpu_number cpu); + static void restore_irqs(Cpu_number cpu); private: Jdb(); // default constructors are undefined @@ -52,12 +52,12 @@ private: static bool never_break; static bool jdb_active; - static void enter_trap_handler(unsigned cpu); - static void leave_trap_handler(unsigned cpu); - static bool handle_conditional_breakpoint(unsigned cpu); + static void enter_trap_handler(Cpu_number cpu); + static void leave_trap_handler(Cpu_number cpu); + static bool handle_conditional_breakpoint(Cpu_number cpu); static void handle_nested_trap(Jdb_entry_frame *e); - static bool handle_user_request(unsigned cpu); - static bool handle_debug_traps(unsigned cpu); + static bool handle_user_request(Cpu_number cpu); + static bool handle_debug_traps(Cpu_number cpu); static bool test_checksums(); public: @@ -105,11 +105,11 @@ char Jdb::last_cmd; char Jdb::hide_statline; // show status line on enter_kdebugger DEFINE_PER_CPU Per_cpu Jdb::entry_frame; -unsigned Jdb::current_cpu; // current CPU JDB is running on +Cpu_number Jdb::current_cpu; // current CPU JDB is running on Thread *Jdb::current_active; // current running thread bool Jdb::was_input_error; // error in command sequence -DEFINE_PER_CPU Per_cpu Jdb::remote_func; +DEFINE_PER_CPU Per_cpu Jdb::remote_func; DEFINE_PER_CPU Per_cpu Jdb::remote_func_data; DEFINE_PER_CPU Per_cpu Jdb::remote_func_running; @@ -130,7 +130,7 @@ unsigned long Jdb::cpus_in_debugger; PUBLIC static bool -Jdb::cpu_in_jdb(unsigned cpu) +Jdb::cpu_in_jdb(Cpu_number cpu) { return Cpu::online(cpu) && running.cpu(cpu); } @@ -139,7 +139,7 @@ template< typename Func > void Jdb::foreach_cpu(Func const &f) { - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) { if (!Cpu::online(i) || !running.cpu(i)) continue; @@ -153,7 +153,7 @@ bool Jdb::foreach_cpu(Func const &f, bool positive) { bool r = positive; - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) { if (!Cpu::online(i) || !running.cpu(i)) continue; @@ -531,11 +531,11 @@ Jdb::execute_command() PRIVATE static bool -Jdb::open_debug_console(unsigned cpu) +Jdb::open_debug_console(Cpu_number cpu) { in_service = 1; save_disable_irqs(cpu); - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) jdb_enter.execute(); if (!stop_all_cpus(cpu)) @@ -551,11 +551,11 @@ Jdb::open_debug_console(unsigned cpu) PRIVATE static void -Jdb::close_debug_console(unsigned cpu) +Jdb::close_debug_console(Cpu_number cpu) { Proc::cli(); Mem::barrier(); - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) { running.cpu(cpu) = 0; // eat up input from console @@ -576,10 +576,10 @@ Jdb::close_debug_console(unsigned cpu) PUBLIC static void -Jdb::remote_work(unsigned cpu, void (*func)(unsigned, void *), void *data, +Jdb::remote_work(Cpu_number cpu, void (*func)(Cpu_number, void *), void *data, bool sync = true) { - if (cpu == 0) + if (cpu == Cpu_number::boot_cpu()) func(cpu, data); else { @@ -742,7 +742,7 @@ Jdb::get_current_active() PUBLIC static inline Jdb_entry_frame* -Jdb::get_entry_frame(unsigned cpu) +Jdb::get_entry_frame(Cpu_number cpu) { return entry_frame.cpu(cpu); } @@ -888,7 +888,7 @@ Jdb::std_cursor_key(int c, Mword cols, Mword lines, Mword max_absy, Mword *absy, PUBLIC static inline Space * -Jdb::get_task(unsigned cpu) +Jdb::get_task(Cpu_number cpu) { if (!get_thread(cpu)) return 0; @@ -1005,7 +1005,7 @@ char Jdb::esc_symbol[] = "\033[33;1m"; IMPLEMENT int -Jdb::enter_jdb(Jdb_entry_frame *e, unsigned cpu) +Jdb::enter_jdb(Jdb_entry_frame *e, Cpu_number cpu) { if (e->debug_ipi()) { @@ -1099,14 +1099,16 @@ Jdb::enter_jdb(Jdb_entry_frame *e, unsigned cpu) "read-only data has changed!\n", Jdb_screen::width()-11, Jdb_screen::Line); - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) if (Cpu::online(i)) { if (running.cpu(i)) - printf(" CPU%2u [" L4_PTR_FMT "]: %s\n", i, + printf(" CPU%2u [" L4_PTR_FMT "]: %s\n", + cxx::int_value(i), entry_frame.cpu(i)->ip(), error_buffer.cpu(i)); else - printf(" CPU%2u: is not in JDB (not responding)\n", i); + printf(" CPU%2u: is not in JDB (not responding)\n", + cxx::int_value(i)); } hide_statline = true; } @@ -1140,7 +1142,7 @@ IMPLEMENTATION [!mp]: PRIVATE static bool -Jdb::stop_all_cpus(unsigned /*current_cpu*/) +Jdb::stop_all_cpus(Cpu_number) { return true; } PRIVATE @@ -1156,7 +1158,7 @@ Jdb::check_for_cpus(bool) PRIVATE static inline int -Jdb::remote_work_ipi_process(unsigned) +Jdb::remote_work_ipi_process(Cpu_number) { return 1; } @@ -1169,7 +1171,7 @@ EXTENSION class Jdb { // remote call static Spin_lock<> _remote_call_lock; - static void (*_remote_work_ipi_func)(unsigned, void *); + static void (*_remote_work_ipi_func)(Cpu_number, void *); static void *_remote_work_ipi_func_data; static unsigned long _remote_work_ipi_done; }; @@ -1177,7 +1179,7 @@ EXTENSION class Jdb //-------------------------------------------------------------------------- IMPLEMENTATION [mp]: -void (*Jdb::_remote_work_ipi_func)(unsigned, void *); +void (*Jdb::_remote_work_ipi_func)(Cpu_number, void *); void *Jdb::_remote_work_ipi_func_data; unsigned long Jdb::_remote_work_ipi_done; Spin_lock<> Jdb::_remote_call_lock; @@ -1187,10 +1189,10 @@ bool Jdb::check_for_cpus(bool try_nmi) { enum { Max_wait_cnt = 1000 }; - for (unsigned c = 1; c < Config::Max_num_cpus; ++c) + for (Cpu_number c = Cpu_number::second(); c < Config::max_num_cpus(); ++c) { if (Cpu::online(c) && !running.cpu(c)) - Ipi::send(Ipi::Debug, 0, c); + Ipi::send(Ipi::Debug, Cpu_number::first(), c); } Mem::barrier(); retry: @@ -1200,7 +1202,7 @@ retry: bool all_there = true; cpus_in_debugger = 0; // skip boot cpu 0 - for (unsigned c = 1; c < Config::Max_num_cpus; ++c) + for (Cpu_number c = Cpu_number::second(); c < Config::max_num_cpus(); ++c) { if (Cpu::online(c)) { @@ -1225,13 +1227,14 @@ retry: } bool do_retry = false; - for (unsigned c = 1; c < Config::Max_num_cpus; ++c) + for (Cpu_number c = Cpu_number::second(); c < Config::max_num_cpus(); ++c) { if (Cpu::online(c)) { if (!running.cpu(c)) { - printf("JDB: CPU %d: is not responding ... %s\n",c, + printf("JDB: CPU %d: is not responding ... %s\n", + cxx::int_value(c), try_nmi ? "trying NMI" : ""); if (try_nmi) { @@ -1252,12 +1255,12 @@ retry: PRIVATE static bool -Jdb::stop_all_cpus(unsigned current_cpu) +Jdb::stop_all_cpus(Cpu_number current_cpu) { enum { Max_wait_cnt = 1000 }; - // JDB allways runs on CPU 0, if any other CPU enters the debugger - // CPU 0 is notified to do enter the debugger too - if (current_cpu == 0) + // JDB allways runs on the boot CPU, if any other CPU enters the debugger + // the boot CPU is notified to do enter the debugger too + if (current_cpu == Cpu_number::boot_cpu()) { // I'm CPU 0 stop all other CPUs and wait for them to enter the JDB jdb_active = 1; @@ -1271,10 +1274,10 @@ Jdb::stop_all_cpus(unsigned current_cpu) // Huh, not CPU 0, so notify CPU 0 to enter JDB too // The notification is ignored if CPU 0 is already within JDB jdb_active = true; - Ipi::send(Ipi::Debug, current_cpu, 0); + Ipi::send(Ipi::Debug, current_cpu, Cpu_number::boot_cpu()); unsigned long wait_count = Max_wait_cnt; - while (!running.cpu(0) && wait_count) + while (!running.cpu(Cpu_number::boot_cpu()) && wait_count) { Proc::pause(); Delay::delay(1); @@ -1283,14 +1286,14 @@ Jdb::stop_all_cpus(unsigned current_cpu) } if (wait_count == 0) - send_nmi(0); + send_nmi(Cpu_number::boot_cpu()); // Wait for messages from CPU 0 while ((volatile bool)jdb_active) { Mem::barrier(); - void (**func)(unsigned, void *) = &remote_func.cpu(current_cpu); - void (*f)(unsigned, void *); + void (**func)(Cpu_number, void *) = &remote_func.cpu(current_cpu); + void (*f)(Cpu_number, void *); if ((f = monitor_address(current_cpu, func))) { @@ -1334,13 +1337,13 @@ Jdb::leave_wait_for_others() for (;;) { bool all_there = true; - for (unsigned c = 0; c < Config::Max_num_cpus; ++c) + for (Cpu_number c = Cpu_number::first(); c < Config::max_num_cpus(); ++c) { if (Cpu::online(c) && running.cpu(c)) { // notify other CPU set_monitored_address(&Jdb::remote_func.cpu(c), - (void (*)(unsigned, void *))0); + (void (*)(Cpu_number, void *))0); // printf("JDB: wait for CPU[%2u] to leave\n", c); all_there = false; } @@ -1369,7 +1372,7 @@ Jdb::leave_wait_for_others() // The remote_work_ipi* functions are for the IPI round-trip benchmark (only) PRIVATE static int -Jdb::remote_work_ipi_process(unsigned cpu) +Jdb::remote_work_ipi_process(Cpu_number cpu) { if (_remote_work_ipi_func) { @@ -1383,8 +1386,8 @@ Jdb::remote_work_ipi_process(unsigned cpu) PUBLIC static bool -Jdb::remote_work_ipi(unsigned this_cpu, unsigned to_cpu, - void (*f)(unsigned, void *), void *data, bool wait = true) +Jdb::remote_work_ipi(Cpu_number this_cpu, Cpu_number to_cpu, + void (*f)(Cpu_number, void *), void *data, bool wait = true) { if (to_cpu == this_cpu) { diff --git a/kernel/fiasco/src/jdb/jdb_dbinfo.cpp b/kernel/fiasco/src/jdb/jdb_dbinfo.cpp index 2163af45d..4473376d3 100644 --- a/kernel/fiasco/src/jdb/jdb_dbinfo.cpp +++ b/kernel/fiasco/src/jdb/jdb_dbinfo.cpp @@ -71,7 +71,7 @@ Jdb_dbinfo::init() Address addr; for (addr = area_start; addr < area_end; addr += Config::SUPERPAGE_SIZE) - Kmem::kdir->walk(Virt_addr(addr), 100, pdir_alloc(Kmem_alloc::allocator())); + Kmem::kdir->walk(Virt_addr(addr), Pdir::Depth, false, pdir_alloc(Kmem_alloc::allocator())); init_symbols_lines(); } @@ -169,7 +169,7 @@ Jdb_dbinfo::map(Address phys, size_t &size, Address &virt) Kmem::kdir->map(phys, Virt_addr(virt), Virt_size(size), Pt_entry::Valid | Pt_entry::Writable | Pt_entry::Referenced - | Pt_entry::Dirty, 100, Ptab::Null_alloc()); + | Pt_entry::Dirty, Pdir::Depth, false, Ptab::Null_alloc()); virt += offs; return true; @@ -183,8 +183,8 @@ Jdb_dbinfo::unmap(Address virt, size_t size) { virt &= Config::PAGE_MASK; - Kmem::kdir->unmap(Virt_addr(virt), Virt_size(size), 100); - Mem_unit::tlb_flush (); + Kmem::kdir->unmap(Virt_addr(virt), Virt_size(size), Pdir::Depth, false); + Mem_unit::tlb_flush(); return_pages(virt, size/Config::PAGE_SIZE); } diff --git a/kernel/fiasco/src/jdb/jdb_exit_module.cpp b/kernel/fiasco/src/jdb/jdb_exit_module.cpp index 0e8a98586..0e734952a 100644 --- a/kernel/fiasco/src/jdb/jdb_exit_module.cpp +++ b/kernel/fiasco/src/jdb/jdb_exit_module.cpp @@ -79,14 +79,14 @@ IMPLEMENTATION [vmx]: PRIVATE static void -Jdb_exit_module::do_vmxoff(unsigned, void *) +Jdb_exit_module::do_vmxoff(Cpu_number, void *) { asm volatile("vmxoff"); } PRIVATE static void -Jdb_exit_module::remote_vmxoff(unsigned cpu) +Jdb_exit_module::remote_vmxoff(Cpu_number cpu) { Jdb::remote_work(cpu, do_vmxoff, 0); } diff --git a/kernel/fiasco/src/jdb/jdb_idle_stats.cpp b/kernel/fiasco/src/jdb/jdb_idle_stats.cpp index a05b99d49..9550e7ef1 100644 --- a/kernel/fiasco/src/jdb/jdb_idle_stats.cpp +++ b/kernel/fiasco/src/jdb/jdb_idle_stats.cpp @@ -24,12 +24,13 @@ Jdb_module::Action_code Jdb_idle_stats::action(int, void *&, char const *&, int &) { printf("\nIDLE STATISTICS --------------------------\n"); - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) { if (!Cpu::online(i)) continue; - printf("CPU[%2u]: %lu times idle, %lu times deep sleep\n", i, + printf("CPU[%2u]: %lu times idle, %lu times deep sleep\n", + cxx::int_value(i), Kernel_thread::_idle_counter.cpu(i), Kernel_thread::_deep_idle_counter.cpu(i)); } diff --git a/kernel/fiasco/src/jdb/jdb_io_apic.cpp b/kernel/fiasco/src/jdb/jdb_io_apic.cpp index fbc017646..24f16862e 100644 --- a/kernel/fiasco/src/jdb/jdb_io_apic.cpp +++ b/kernel/fiasco/src/jdb/jdb_io_apic.cpp @@ -28,10 +28,11 @@ static Jdb_io_apic_module jdb_io_apic_module INIT_PRIORITY(JDB_MODULE_INIT_PRIO) PRIVATE static void -Jdb_io_apic_module::print_lapic(unsigned cpu, void *) +Jdb_io_apic_module::print_lapic(Cpu_number cpu, void *) { - printf("\nLocal APIC [%u, %08x]: tpr=%2x ppr=%2x\n", cpu, Apic::get_id(), Apic::tpr(), - Apic::reg_read(0xa0)); + printf("\nLocal APIC [%u, %08x]: tpr=%2x ppr=%2x\n", + cxx::int_value(cpu), + Apic::get_id(), Apic::tpr(), Apic::reg_read(0xa0)); printf(" Running: tpr=%02x\n", Jdb::apic_tpr.cpu(cpu)); unsigned const regs[] = { 0x200, 0x100, 0x180 }; @@ -50,7 +51,7 @@ Jdb_io_apic_module::print_lapic(unsigned cpu, void *) PRIVATE static void -Jdb_io_apic_module::remote_print_lapic(unsigned cpu) +Jdb_io_apic_module::remote_print_lapic(Cpu_number cpu) { Jdb::remote_work(cpu, print_lapic, 0); } diff --git a/kernel/fiasco/src/jdb/jdb_ipi.cpp b/kernel/fiasco/src/jdb/jdb_ipi.cpp index 94f3d0362..eb47e9892 100644 --- a/kernel/fiasco/src/jdb/jdb_ipi.cpp +++ b/kernel/fiasco/src/jdb/jdb_ipi.cpp @@ -18,11 +18,11 @@ static Jdb_ipi_module jdb_ipi_module INIT_PRIORITY(JDB_MODULE_INIT_PRIO); PRIVATE static void -Jdb_ipi_module::print_info(unsigned cpu) +Jdb_ipi_module::print_info(Cpu_number cpu) { Ipi &ipi = Ipi::_ipi.cpu(cpu); printf("CPU%02u sent/rcvd: %ld/%ld\n", - cpu, ipi._stat_sent, ipi._stat_received); + cxx::int_value(cpu), ipi._stat_sent, ipi._stat_received); } PUBLIC diff --git a/kernel/fiasco/src/jdb/jdb_kern_info-bench.cpp b/kernel/fiasco/src/jdb/jdb_kern_info-bench.cpp index d6b0f4a54..e642bd551 100644 --- a/kernel/fiasco/src/jdb/jdb_kern_info-bench.cpp +++ b/kernel/fiasco/src/jdb/jdb_kern_info-bench.cpp @@ -67,7 +67,7 @@ static int ipi_cnt; PRIVATE static void -Jdb_kern_info_bench::wait_for_ipi(unsigned cpu, void *) +Jdb_kern_info_bench::wait_for_ipi(Cpu_number cpu, void *) { Jdb::restore_irqs(cpu); stop_timer(); @@ -82,17 +82,17 @@ Jdb_kern_info_bench::wait_for_ipi(unsigned cpu, void *) PRIVATE static void -Jdb_kern_info_bench::empty_func(unsigned, void *) +Jdb_kern_info_bench::empty_func(Cpu_number, void *) { ++ipi_cnt; } PRIVATE static void -Jdb_kern_info_bench::do_ipi_bench(unsigned my_cpu, void *_partner) +Jdb_kern_info_bench::do_ipi_bench(Cpu_number my_cpu, void *_partner) { Unsigned64 time; - unsigned partner = (unsigned long)_partner; + Cpu_number partner = Cpu_number((unsigned long)_partner); enum { Runs2 = 3, Warmup = 4, @@ -110,7 +110,8 @@ Jdb_kern_info_bench::do_ipi_bench(unsigned my_cpu, void *_partner) for (i = 0; i < (1 << Runs2); i++) Jdb::remote_work_ipi(my_cpu, partner, empty_func, 0, true); - printf(" %2u:%8lld", partner, (get_time_now() - time) >> Runs2); + printf(" %2u:%8lld", cxx::int_value(partner), + (get_time_now() - time) >> Runs2); if (ipi_cnt != Rounds) printf("\nCounter mismatch: cnt=%d v %d\n", ipi_cnt, Rounds); @@ -125,33 +126,35 @@ Jdb_kern_info_bench::do_mp_benchmark() { // IPI bench matrix printf("IPI round-trips:\n"); - for (unsigned u = 0; u < Config::Max_num_cpus; ++u) + for (Cpu_number u = Cpu_number::first(); u < Config::max_num_cpus(); ++u) if (Cpu::online(u)) { - printf("l%2u: ", u); + printf("l%2u: ", cxx::int_value(u)); - for (unsigned v = 0; v < Config::Max_num_cpus; ++v) + for (Cpu_number v = Cpu_number::first(); v < Config::max_num_cpus(); ++v) if (Cpu::online(v)) { if (u == v) - printf(" %2u:%8s", u, "X"); + printf(" %2u:%8s", cxx::int_value(u), "X"); else { ipi_bench_spin_done = 0; // v is waiting for IPIs - if (v != 0) + if (v != Cpu_number::boot_cpu()) Jdb::remote_work(v, wait_for_ipi, 0, false); // u is doing benchmark - if (u == 0) - do_ipi_bench(0, (void *)v); + if (u == Cpu_number::boot_cpu()) + do_ipi_bench(Cpu_number::boot_cpu(), + (void *)(long)cxx::int_value(v)); else - Jdb::remote_work(u, do_ipi_bench, (void *)v, false); + Jdb::remote_work(u, do_ipi_bench, + (void *)(long)cxx::int_value(v), false); // v is waiting for IPIs - if (v == 0) - wait_for_ipi(0, 0); + if (v == Cpu_number::boot_cpu()) + wait_for_ipi(Cpu_number::boot_cpu(), 0); Mem::barrier(); diff --git a/kernel/fiasco/src/jdb/jdb_kern_info.cpp b/kernel/fiasco/src/jdb/jdb_kern_info.cpp index a236586b0..07cdecf8e 100644 --- a/kernel/fiasco/src/jdb/jdb_kern_info.cpp +++ b/kernel/fiasco/src/jdb/jdb_kern_info.cpp @@ -1,7 +1,7 @@ INTERFACE: #include "jdb_module.h" -#include +#include class Jdb_kern_info_module; diff --git a/kernel/fiasco/src/jdb/jdb_kobject.cpp b/kernel/fiasco/src/jdb/jdb_kobject.cpp index db249840a..b432a8373 100644 --- a/kernel/fiasco/src/jdb/jdb_kobject.cpp +++ b/kernel/fiasco/src/jdb/jdb_kobject.cpp @@ -3,7 +3,7 @@ INTERFACE: #include "jdb_module.h" #include "jdb_list.h" #include "kobject.h" -#include +#include class Kobject; class Jdb_kobject_handler; diff --git a/kernel/fiasco/src/jdb/jdb_mapdb.cpp b/kernel/fiasco/src/jdb/jdb_mapdb.cpp index fe86479ef..64ff3edcd 100644 --- a/kernel/fiasco/src/jdb/jdb_mapdb.cpp +++ b/kernel/fiasco/src/jdb/jdb_mapdb.cpp @@ -45,12 +45,22 @@ size_str (Mword size) return scratchbuf; } +static +unsigned long long +Jdb_mapdb::val(Mdb_types::Pfn p, Mdb_types::Order base_size) +{ + return cxx::int_value(p << base_size); +} + + static bool -Jdb_mapdb::show_tree(Treemap* pages, Page_number address, +Jdb_mapdb::show_tree(Treemap* pages, Mapping::Pcnt offset, Mdb_types::Order base_size, unsigned &screenline, unsigned indent = 1) { - Page_number page = address >> pages->_page_shift; + typedef Treemap::Page Page; + + Page page = pages->trunc_to_page(offset); Physframe* f = pages->frame(page); Mapping_tree* t = f->tree.get(); unsigned i; @@ -58,16 +68,18 @@ Jdb_mapdb::show_tree(Treemap* pages, Page_number address, if (! t) { - printf(" no mapping tree registered for frame number 0x%x\033[K\n", - (unsigned) page.value()); + printf(" no mapping tree registered for frame number 0x%lx\033[K\n", + cxx::int_value(page)); screenline++; return true; } - printf(" mapping tree for %s-page " L4_PTR_FMT " of task %p - header at " - L4_PTR_FMT "\033[K\n", - size_str (1UL << pages->_page_shift), - pages->vaddr(t->mappings()).value(), t->mappings()[0].space(), (Address)t); + printf(" mapping tree for %s-page %012llx of task %lx - header at " + L4_PTR_FMT "\033[K\n", + size_str(1ULL << cxx::int_value(pages->_page_shift + base_size)), + val(pages->vaddr(t->mappings()), base_size), + Kobject_dbg::pointer_to_id(t->mappings()[0].space()), + (Address)t); #ifdef NDEBUG // If NDEBUG is active, t->_empty_count is undefined printf(" header info: " @@ -118,10 +130,10 @@ Jdb_mapdb::show_tree(Treemap* pages, Page_number address, i+1, (Address) m->data(), (Mword) m->submap()); else { - printf("%*u: %lx va=" L4_PTR_FMT " task=%lx depth=", + printf("%*u: %lx va=%012llx task=%lx depth=", indent + m->depth() > 10 ? 0 : indent + m->depth(), i+1, (Address) m->data(), - pages->vaddr(m).value(), + val(pages->vaddr(m), base_size), Kobject_dbg::pointer_to_id(m->space())); if (m->depth() == Mapping::Depth_root) @@ -154,7 +166,8 @@ Jdb_mapdb::show_tree(Treemap* pages, Page_number address, if (m->depth() == Mapping::Depth_submap) { if (! Jdb_mapdb::show_tree(m->submap(), - address.offset(Page_count::create(1UL << pages->_page_shift)), + cxx::get_lsb(offset, pages->_page_shift), + base_size, screenline, indent + m->parent()->depth())) return false; } @@ -167,58 +180,58 @@ static Address Jdb_mapdb::end_address (Mapdb* mapdb) { - return mapdb->_treemap->end_addr().value(); + return cxx::int_value(mapdb->_treemap->end_addr()); } static void -Jdb_mapdb::show (Page_number page, char which_mapdb) +Jdb_mapdb::show(Mapping::Pfn page, char which_mapdb) { unsigned j; int c; Jdb::clear_screen(); + typedef Mdb_types::Order Order; for (;;) { Mapdb* mapdb; const char* type; - Mword page_shift; - Page_count super_inc; + Mapping::Pcnt super_inc; + Mdb_types::Order super_shift; + Order base_size = Order(0); switch (which_mapdb) { case 'm': type = "Phys frame"; mapdb = mapdb_mem.get(); - page_shift = 0; //Config::PAGE_SHIFT; - super_inc = Page_count::create(Config::SUPERPAGE_SIZE / Config::PAGE_SIZE); + base_size = Order(Config::PAGE_SHIFT); + super_shift = Mdb_types::Order(Config::SUPERPAGE_SHIFT - Config::PAGE_SHIFT); break; #ifdef CONFIG_PF_PC case 'i': type = "I/O port"; mapdb = mapdb_io.get(); - page_shift = 0; - super_inc = Page_count::create(0x100); + base_size = Order(0); + super_shift = Mdb_types::Order(8); break; #endif default: return; } - if (! mapdb->valid_address (page << page_shift)) - page = Page_number::create(0); + super_inc = Mapping::Pcnt(1) << super_shift; + + if (! mapdb->valid_address(page)) + page = Mapping::Pfn(0); Jdb::cursor(); - printf ("%s " L4_PTR_FMT "\033[K\n\033[K\n", - type, page.value() << page_shift); + printf("%s %012llx\033[K\n\033[K\n", type, val(page, base_size)); j = 3; - if (! Jdb_mapdb::show_tree (mapdb->_treemap, - (page << page_shift) - - mapdb->_treemap->_page_offset, - j)) + if (! Jdb_mapdb::show_tree(mapdb->_treemap, page - Mapping::Pfn(0), base_size, j)) return; for (; jvalid_address(++page << page_shift)) - page = Page_number::create(0); + if (! mapdb->valid_address(++page)) + page = Mapping::Pfn(0); redraw = true; break; case 'p': case KEY_CURSOR_UP: - if (! mapdb->valid_address(--page << page_shift)) - page = Page_number::create(end_address (mapdb) - 1) >> page_shift; + if (! mapdb->valid_address(--page)) + page = Mapping::Pfn(end_address(mapdb) - 1); redraw = true; break; case 'N': case KEY_PAGE_DOWN: - page = (page + super_inc).trunc(super_inc); - if (! mapdb->valid_address(page << page_shift)) - page = Page_number::create(0); + page = cxx::mask_lsb(page + super_inc, super_shift); + if (! mapdb->valid_address(page)) + page = Mapping::Pfn(0); redraw = true; break; case 'P': case KEY_PAGE_UP: - page = (page - super_inc).trunc(super_inc); - if (! mapdb->valid_address(page << page_shift)) - page = Page_number::create(end_address (mapdb) - 1) >> page_shift; + page = cxx::mask_lsb(page - super_inc, super_shift); + if (! mapdb->valid_address(page)) + page = Mapping::Pfn(end_address(mapdb) - 1); redraw = true; break; case ' ': @@ -325,11 +338,7 @@ Jdb_mapdb::action(int cmd, void *&args, char const *&fmt, int &next_char) fmt = " port: " L4_FRAME_INPUT_FMT; break; #endif - - case 'o': - fmt = " object: %x"; - break; - } + } which_mapdb = subcmd; args = &pagenum; @@ -340,10 +349,7 @@ Jdb_mapdb::action(int cmd, void *&args, char const *&fmt, int &next_char) return NOTHING; doit: - if (which_mapdb == 'o') - Jdb_mapdb::show_simple_tree((Kobject_common*)pagenum); - else - show(Page_number::create(pagenum), which_mapdb); + show(Mapping::Pfn(pagenum), which_mapdb); return NOTHING; } @@ -354,7 +360,7 @@ Jdb_mapdb::cmds() const static Cmd cs[] = { { 0, "m", "mapdb", "%c", - "m[it]\tshow [I/O,task] mapping database starting at address", + "m[i]\tshow [I/O] mapping database starting at address", &subcmd }, { 1, "", "dumpmapdbobjs", "", "dumpmapdbobjs\tDump complete object mapping database", 0 }, @@ -502,12 +508,13 @@ Jdb_mapdb::show_simple_tree(Kobject_common *f, unsigned indent = 1) if (pi) { - space_id = static_cast(pi->info()->s)->dbg_info()->dbg_id(); - cap_idx += pi->info()->offset; + space_id = static_cast(pi->info()->s)->dbg_info()->dbg_id(); + cap_idx += pi->info()->offset; } printf(" " L4_PTR_FMT "[C:%lx]: space=D:%lx rights=%x flags=%lx obj=%p", - (Address)*m, cap_idx, space_id, (unsigned)e->rights(), e->_flags, + (Address)*m, cap_idx, space_id, + (unsigned)cxx::int_value(e->rights()), e->_flags, e->obj()); puts("\033[K"); diff --git a/kernel/fiasco/src/jdb/jdb_module.cpp b/kernel/fiasco/src/jdb/jdb_module.cpp index 8a649c246..30a7a6950 100644 --- a/kernel/fiasco/src/jdb/jdb_module.cpp +++ b/kernel/fiasco/src/jdb/jdb_module.cpp @@ -1,8 +1,8 @@ INTERFACE: #include -#include -#include +#include +#include #include "initcalls.h" diff --git a/kernel/fiasco/src/jdb/jdb_mp_request_sl.cpp b/kernel/fiasco/src/jdb/jdb_mp_request_sl.cpp index 2e4dcd6fb..e50e9fc6f 100644 --- a/kernel/fiasco/src/jdb/jdb_mp_request_sl.cpp +++ b/kernel/fiasco/src/jdb/jdb_mp_request_sl.cpp @@ -19,9 +19,9 @@ public: struct Find_cpu { Item const *r; - mutable unsigned cpu; + mutable Cpu_number cpu; Find_cpu(Item const *i) : r(i), cpu(~0U) {} - void operator()(unsigned _cpu) const + void operator()(Cpu_number _cpu) const { if (&Mp_request_queue::rq.cpu(_cpu) == r) { @@ -35,11 +35,11 @@ public: static Jdb_mp_request_module jdb_mp_request_module INIT_PRIORITY(JDB_MODULE_INIT_PRIO); PRIVATE static -unsigned +Cpu_number Jdb_mp_request_module::find_cpu(Item const *r) { if (!r) - return 0; + return Cpu_number::boot_cpu(); Find_cpu _find_cpu(r); Jdb::foreach_cpu(_find_cpu); @@ -54,12 +54,12 @@ Jdb_mp_request_module::print_request(Item const *item) " value = { func = %p, arg = %p, _lock=%lu }\n" " next = %p (cpu %u)\n", find_cpu(item), item, item->value.func, item->value.arg, item->value._lock, - item->next, find_cpu(item->next)); + item->next, Cpu_number::val(find_cpu(item->next))); } PRIVATE static void -Jdb_mp_request_module::print_queue(unsigned cpu) +Jdb_mp_request_module::print_queue(Cpu_number cpu) { if (!Jdb::cpu_in_jdb(cpu)) @@ -67,10 +67,10 @@ Jdb_mp_request_module::print_queue(unsigned cpu) bool online = Cpu::online(cpu); if (!online) { - printf("CPU %u is not online...\n", cpu); + printf("CPU %u is not online...\n", Cpu_number::val(cpu)); return; } - printf("CPU %u has not entered JDB (try to display queue...\n", cpu); + printf("CPU %u has not entered JDB (try to display queue...\n", Cpu_number::val(cpu)); } Item const *item = &Mp_request_queue::rq.cpu(cpu); @@ -79,7 +79,7 @@ Jdb_mp_request_module::print_queue(unsigned cpu) printf("CPU[%2u]: Mp request item @%p, Mp request FIFO @%p\n" " Local queue Item:\n", - cpu, item, fifo); + Cpuz_number::val(cpu), item, fifo); print_request(item); @@ -102,11 +102,11 @@ Jdb_module::Action_code Jdb_mp_request_module::action (int cmd, void *&argbuf, char const *&fmt, int &next) { char const *c = (char const *)argbuf; - unsigned cpu; + Cpu_number cpu; if (cmd!=0) return NOTHING; - if (argbuf != &cpu) + if (argbuf != &Cpu_number::val(cpu)) { if (*c == 'a') Jdb::foreach_cpu(&print_queue); diff --git a/kernel/fiasco/src/jdb/jdb_obj_space.cpp b/kernel/fiasco/src/jdb/jdb_obj_space.cpp index 26e2fb35e..ac728d0cb 100644 --- a/kernel/fiasco/src/jdb/jdb_obj_space.cpp +++ b/kernel/fiasco/src/jdb/jdb_obj_space.cpp @@ -96,18 +96,18 @@ Jdb_obj_space::print_statline(unsigned long row, unsigned long col) if (!o) { Jdb::printf_statline("objs", "=mode", "%lx: -- INVALID --", - index(row,col)); + cxx::int_value(index(row,col))); return; } unsigned len = Jdb_kobject::obj_description(buf, sizeof(buf), true, o->dbg_info()); Jdb::printf_statline("objs", "=mode", - "%lx: %-*s", index(row,col), len, buf); + "%lx: %-*s", cxx::int_value(index(row,col)), len, buf); } PUBLIC void -Jdb_obj_space::print_entry(Address entry) +Jdb_obj_space::print_entry(Cap_index entry) { unsigned rights; Kobject_iface *o = item(entry, &rights); @@ -122,9 +122,9 @@ Jdb_obj_space::print_entry(Address entry) case Name: switch (rights) { - case L4_fpage::WX: r = '*'; break; - case L4_fpage::W: r = 'w'; break; - case L4_fpage::X: r = 'x'; break; + case 0x3: r = '*'; break; + case 0x2: r = 'w'; break; + case 0x1: r = 'x'; break; } printf("%05lx%c %-*s", o->dbg_info()->dbg_id(), r, 9, Jdb_kobject::kobject_type(o)); break; @@ -141,17 +141,17 @@ void Jdb_obj_space::draw_entry(unsigned long row, unsigned long col) { if (col==0) - printf("%06lx ", index(row, 1)); + printf("%06lx ", cxx::int_value(index(row, 1))); else print_entry(index(row, col)); } PRIVATE -Address +Cap_index Jdb_obj_space::index(unsigned long row, unsigned long col) { Mword e = (col-1) + (row * (cols()-1)); - return _base + e; + return Cap_index(_base + e); } PRIVATE @@ -221,36 +221,11 @@ Jdb_obj_space::handle_key(Kobject_common *o, int code) static Jdb_obj_space jdb_obj_space INIT_PRIORITY(JDB_MODULE_INIT_PRIO); -// ------------------------------------------------------------------------ -IMPLEMENTATION [obj_space_virt]: - -PUBLIC -Kobject_iface * -Jdb_obj_space::item(Address entry, unsigned *rights) -{ - Mword dummy; - Obj_space::Capability *c = _task->cap_virt(entry); - if (!c) - return 0; - - Mword mapped = Jdb::peek((Mword*)c, _task, dummy); - - if (!mapped) - return 0; - - Kobject_iface *o = (Kobject_iface*)(dummy & ~3UL); - *rights = dummy & 3; - - return o; -} - -// ------------------------------------------------------------------------ -IMPLEMENTATION [obj_space_phys]: PUBLIC Kobject_iface * -Jdb_obj_space::item(Address entry, unsigned *rights) +Jdb_obj_space::item(Cap_index entry, unsigned *rights) { - Obj_space::Capability *c = _task->get_cap(entry); + Obj_space::Capability *c = _task->jdb_lookup_cap(entry); if (!c) return 0; diff --git a/kernel/fiasco/src/jdb/jdb_prompt_ext.cpp b/kernel/fiasco/src/jdb/jdb_prompt_ext.cpp index e62dfa54e..1e63b1a66 100644 --- a/kernel/fiasco/src/jdb/jdb_prompt_ext.cpp +++ b/kernel/fiasco/src/jdb/jdb_prompt_ext.cpp @@ -1,6 +1,6 @@ INTERFACE: -#include +#include class Jdb_prompt_ext : public cxx::H_list_item { diff --git a/kernel/fiasco/src/jdb/jdb_ptab-ia32-ux-arm.cpp b/kernel/fiasco/src/jdb/jdb_ptab-ia32-ux-arm.cpp index 01e1bca99..b8f6df3c7 100644 --- a/kernel/fiasco/src/jdb/jdb_ptab-ia32-ux-arm.cpp +++ b/kernel/fiasco/src/jdb/jdb_ptab-ia32-ux-arm.cpp @@ -1,127 +1,42 @@ -IMPLEMENTATION [ia32,ux]: +IMPLEMENTATION [ia32,ux,arm]: #include "paging.h" -unsigned Jdb_ptab::max_pt_level = Pdir::Depth; - -static unsigned long _leaf_check[] -= { Pt_entry::Pse_bit | Pt_entry::Valid, 0 }; -static unsigned long next_level_mask[] -= { 0xfffff000, 0 }; - - -static inline bool leaf_check(unsigned long entry, unsigned level) -{ return (_leaf_check[level] & entry) == _leaf_check[level]; } - -IMPLEMENT -unsigned -Jdb_ptab::entry_is_pt_ptr(Mword entry, unsigned level, - unsigned *entries, unsigned *next_level) -{ - if (leaf_check(entry, level)) - return 0; - *entries = Ptab::Level::length(level); - *next_level = level+1; - return 1; -} - -IMPLEMENT -Address -Jdb_ptab::entry_phys(Mword entry, unsigned level) -{ - if (!leaf_check(entry, level)) - return entry & next_level_mask[level]; - - return Ptab::Level::addr(level, entry); -} - -IMPLEMENT inline NEEDS ["paging.h"] -unsigned -Jdb_ptab::entry_valid(Mword entry, unsigned) -{ return entry & Pt_entry::Valid; } +IMPLEMENTATION [ia32,ux]: IMPLEMENT void -Jdb_ptab::print_entry(Mword entry, unsigned level) +Jdb_ptab::print_entry(Pdir::Pte_ptr const &entry) { if (dump_raw) { - printf(L4_PTR_FMT, entry); + printf(L4_PTR_FMT, *entry.pte); return; } - if (!entry_valid(entry,level)) + if (!entry.is_valid()) { putstr(" - "); return; } - Address phys = entry_phys(entry, level); + Address phys = entry_phys(entry); - if (level == Pdir::Super_level && entry & Pt_entry::Pse_bit) + if (entry.level != Pdir::Depth && entry.is_leaf()) printf((phys >> 20) > 0xFF ? "%03lX/4" : " %02lX/4", phys >> 20); else printf((phys >> Config::PAGE_SHIFT) > 0xFFFF ? "%05lx" : " %04lx", phys >> Config::PAGE_SHIFT); - putchar(((cur_pt_level>=max_pt_level || (entry & Pt_entry::Pse_bit)) && - (entry & Pt_entry::Cpu_global)) ? '+' : '-'); - printf("%s%c%s", entry & Pt_entry::Noncacheable ? JDB_ANSI_COLOR(lightblue) : "", - entry & Pt_entry::Noncacheable - ? 'n' : (entry & Pt_entry::Write_through) ? 't' : '-', - entry & Pt_entry::Noncacheable ? JDB_ANSI_END : ""); - putchar(entry & Pt_entry::User - ? (entry & Pt_entry::Writable) ? 'w' : 'r' - : (entry & Pt_entry::Writable) ? 'W' : 'R'); + putchar(((cur_pt_level >= Pdir::Depth || entry.is_leaf()) && + (*entry.pte & Pt_entry::Cpu_global)) ? '+' : '-'); + printf("%s%c%s", *entry.pte & Pt_entry::Noncacheable ? JDB_ANSI_COLOR(lightblue) : "", + *entry.pte & Pt_entry::Noncacheable + ? 'n' : (*entry.pte & Pt_entry::Write_through) ? 't' : '-', + *entry.pte & Pt_entry::Noncacheable ? JDB_ANSI_END : ""); + putchar(*entry.pte & Pt_entry::User + ? (*entry.pte & Pt_entry::Writable) ? 'w' : 'r' + : (*entry.pte & Pt_entry::Writable) ? 'W' : 'R'); } -PUBLIC -unsigned long -Jdb_ptab::rows() const -{ return entries/8; } - -IMPLEMENTATION [ia32,ux,arm]: - -#if 0 -// calculate row from virtual address -PRIVATE -unsigned -Jdb_ptab::disp_virt_to_r(Address v) -{ - v = Ptab::Level::index(cur_pt_level, v >> Pdir::Va::Shift); - return v / (cols()-1); -} - -// calculate column from virtual address -PRIVATE -unsigned -Jdb_ptab::disp_virt_to_c(Address v) -{ - v = Ptab::Level::index(cur_pt_level, v >> Pdir::Va::Shift); - return (v % (cols()-1)) + 1; -} -#endif - -PRIVATE -Address -Jdb_ptab::disp_virt(unsigned row, unsigned col) -{ - Pdir::Va e((col-1) + (row * (cols()-1))); - e <<= Ptab::Level::shift(cur_pt_level); - return Virt_addr(e).value() + virt_base; -} - -PUBLIC -void -Jdb_ptab::print_statline(unsigned long row, unsigned long col) -{ - unsigned long sid = Kobject_dbg::pointer_to_id(_task); - - if (cur_pt_level=mode =goto ptab/superpage", - "<" L4_PTR_FMT "> task D:%lx", disp_virt(row,col), sid); - else // PT_MODE - Jdb::printf_statline("ptab", "=mode =goto page", - "<" L4_PTR_FMT "> task D:%lx", disp_virt(row,col), sid); -} diff --git a/kernel/fiasco/src/jdb/jdb_ptab.cpp b/kernel/fiasco/src/jdb/jdb_ptab.cpp index 4b99fe186..174584786 100644 --- a/kernel/fiasco/src/jdb/jdb_ptab.cpp +++ b/kernel/fiasco/src/jdb/jdb_ptab.cpp @@ -38,15 +38,12 @@ private: unsigned char cur_pt_level; char dump_raw; - static unsigned max_pt_level; - - static unsigned entry_valid(Mword entry, unsigned level); - static unsigned entry_is_pt_ptr(Mword entry, unsigned level, + static unsigned entry_is_pt_ptr(Pdir::Pte_ptr const &entry, unsigned *entries, unsigned *next_level); - static Address entry_phys(Mword entry, unsigned level); + static Address entry_phys(Pdir::Pte_ptr const &entry); - void print_entry(Mword entry, unsigned level); - void print_head(Mword entry); + void print_entry(Pdir::Pte_ptr const &); + void print_head(void *entry); }; char Jdb_ptab_m::first_char; @@ -61,8 +58,8 @@ Jdb_ptab::Jdb_ptab(void *pt_base = 0, Space *task = 0, : base((Address)pt_base), virt_base(virt_base), _level(level), _task(task), entries(entries), cur_pt_level(pt_level), dump_raw(0) { - if (!pt_level && entries == 0) - this->entries = 1UL << Ptab::Level::Traits::Size; + if (entries == 0) + this->entries = Pdir::entries_at_level(pt_level); } PUBLIC @@ -92,25 +89,70 @@ PUBLIC void Jdb_ptab::draw_entry(unsigned long row, unsigned long col) { - if (col==0) - print_head(virt(row, 1)); + int idx; + if (col == 0) + { + idx = index(row, 1); + if (idx >= 0) + print_head(pte(idx)); + else + putstr(" "); + } + else if ((idx = index(row, col)) >= 0) + print_entry(Pdir::Pte_ptr(pte(idx), cur_pt_level)); else - print_entry(*(My_pte*)(virt(row,col)), cur_pt_level); + putstr(" ### "); } -PRIVATE +IMPLEMENT Address -Jdb_ptab::virt(unsigned long row, unsigned long col) +Jdb_ptab::entry_phys(Pdir::Pte_ptr const &entry) +{ + if (!entry.is_leaf()) + return entry.next_level(); + + return entry.page_addr(); +} + + +PRIVATE inline +int +Jdb_ptab::index(unsigned row, unsigned col) { Mword e = (col-1) + (row * (cols()-1)); - return base + e * sizeof(Mword); + if (e < Pdir::Levels::length(cur_pt_level)) + return e; + else + return -1; +} + + +PRIVATE inline +void * +Jdb_ptab::pte(int index) +{ + return (void*)(base + index * Pdir::Levels::entry_size(cur_pt_level)); +} + +IMPLEMENT +unsigned +Jdb_ptab::entry_is_pt_ptr(Pdir::Pte_ptr const &entry, + unsigned *entries, unsigned *next_level) +{ + if (!entry.is_valid() || entry.is_leaf()) + return 0; + + *entries = Pdir::entries_at_level(entry.level+1); + *next_level = entry.level+1; + return 1; } + IMPLEMENT void -Jdb_ptab::print_head(Mword entry) +Jdb_ptab::print_head(void *entry) { - printf(L4_PTR_FMT, entry); + printf(L4_PTR_FMT, (Address)entry); } PUBLIC @@ -125,7 +167,7 @@ Jdb_ptab_m::handle_key(Kobject_common *o, int code) { Thread *th = Kobject::dcast(o); if (!th || !th->space()) - return false; + return false; t = th->space(); } @@ -157,27 +199,30 @@ Jdb_ptab::key_pressed(int c, unsigned long &row, unsigned long &col) case KEY_RETURN: // goto ptab/address under cursor if (_level<=7) { - My_pte pt_entry = *(My_pte*)virt(row,col); - if (!entry_valid(pt_entry, cur_pt_level)) + int idx = index(row, col); + if (idx < 0) + break; + + Pdir::Pte_ptr pt_entry(pte(idx), cur_pt_level); + if (!pt_entry.is_valid()) break; - Address pd_virt = (Address) - Mem_layout::phys_to_pmem(entry_phys(pt_entry, cur_pt_level)); + void *pd_virt = (void*)Mem_layout::phys_to_pmem(entry_phys(pt_entry)); unsigned next_level, entries; - if (cur_pt_level < max_pt_level - && entry_is_pt_ptr(pt_entry, cur_pt_level, &entries, &next_level)) + if (cur_pt_level < Pdir::Depth + && entry_is_pt_ptr(pt_entry, &entries, &next_level)) { - Jdb_ptab pt_view((void *)pd_virt, _task, next_level, entries, - disp_virt(row,col), _level+1); + Jdb_ptab pt_view(pd_virt, _task, next_level, entries, + disp_virt(idx), _level+1); if (!pt_view.show(0,1)) return Exit; return Redraw; } else if (jdb_dump_addr_task != 0) { - if (!jdb_dump_addr_task(disp_virt(row,col), _task, _level+1)) + if (!jdb_dump_addr_task(disp_virt(idx), _task, _level+1)) return Exit; return Redraw; } @@ -188,6 +233,40 @@ Jdb_ptab::key_pressed(int c, unsigned long &row, unsigned long &col) return Handled; } +PRIVATE +Address +Jdb_ptab::disp_virt(int idx) +{ + Pdir::Va e((Mword)idx << Pdir::lsb_for_level(cur_pt_level)); + return Virt_addr::val(e) + virt_base; +} + +PUBLIC +unsigned long +Jdb_ptab::rows() const +{ + if (cols() > 1) + return (entries + cols() - 2) / (cols()-1); + return 0; +} + +PUBLIC +void +Jdb_ptab::print_statline(unsigned long row, unsigned long col) +{ + unsigned long sid = Kobject_dbg::pointer_to_id(_task); + + Address va; + int idx = index(row, col); + if (idx >= 0) + va = disp_virt(idx); + else + va = -1; + + Jdb::printf_statline("p:", "=mode =goto page/next level", + " <" L4_PTR_FMT "> task D:%lx", cur_pt_level, va, sid); +} + PUBLIC Jdb_module::Action_code Jdb_ptab_m::action(int cmd, void *&args, char const *&fmt, int &next_char) diff --git a/kernel/fiasco/src/jdb/jdb_rcupdate.cpp b/kernel/fiasco/src/jdb/jdb_rcupdate.cpp index a3f081852..81c0c1615 100644 --- a/kernel/fiasco/src/jdb/jdb_rcupdate.cpp +++ b/kernel/fiasco/src/jdb/jdb_rcupdate.cpp @@ -45,17 +45,17 @@ Jdb_rcupdate::action(int cmd, void *&, char const *&, int &) print_batch(Rcu::_rcu._completed); puts(""); printf(" next_pending=%s\n" " cpus=", Rcu::_rcu._next_pending?"yes":"no"); - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) - printf("%s%s", Rcu::_rcu._cpus.get(i)?"1":"0", i%4 == 3?" ":""); + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) + printf("%s%s", Rcu::_rcu._cpus.get(i)?"1":"0", cxx::int_value(i) % 4 == 3?" ":""); puts(""); - for (unsigned i = 0; i < Config::Max_num_cpus; ++i) + for (Cpu_number i = Cpu_number::first(); i < Config::max_num_cpus(); ++i) { if (!Cpu::online(i)) continue; - printf(" CPU[%2u]:", i); + printf(" CPU[%2u]:", cxx::int_value(i)); Rcu_data const *d = &Rcu::_rcu_data.cpu(i); printf(" quiescent batch="); print_batch(d->_q_batch); puts(""); diff --git a/kernel/fiasco/src/jdb/jdb_table.cpp b/kernel/fiasco/src/jdb/jdb_table.cpp index cf830b53c..4f1f1bc6e 100644 --- a/kernel/fiasco/src/jdb/jdb_table.cpp +++ b/kernel/fiasco/src/jdb/jdb_table.cpp @@ -342,7 +342,7 @@ screen: PUBLIC void -Jdb_table::draw_table(unsigned long row, unsigned long col, +Jdb_table::draw_table(unsigned long row, unsigned long col, unsigned lines, unsigned columns) { for (unsigned long y = 0; y < lines; ++y) diff --git a/kernel/fiasco/src/jdb/jdb_tbuf.cpp b/kernel/fiasco/src/jdb/jdb_tbuf.cpp index dc8ecd65c..dc7ccee00 100644 --- a/kernel/fiasco/src/jdb/jdb_tbuf.cpp +++ b/kernel/fiasco/src/jdb/jdb_tbuf.cpp @@ -138,7 +138,7 @@ protected: #else // ! CONFIG_JDB_LOGGING -#define BEGIN_LOG_EVENT(name, sc, fmt) \ +#define BEGIN_LOG_EVENT(name, sc, fmt) \ if (0) \ { char __do_log__ = 0; (void)__do_log__; @@ -177,14 +177,14 @@ PUBLIC static inline NEEDS["mem_layout.h"] Tracebuffer_status * Jdb_tbuf::status() { - return (Tracebuffer_status*) Mem_layout::Tbuf_status_page; + return (Tracebuffer_status *)Mem_layout::Tbuf_status_page; } PROTECTED static inline NEEDS["mem_layout.h"] Tb_entry_union * Jdb_tbuf::buffer() { - return (Tb_entry_union*)Mem_layout::Tbuf_buffer_area; + return (Tb_entry_union *)Mem_layout::Tbuf_buffer_area; } PUBLIC static inline @@ -201,7 +201,7 @@ Jdb_tbuf::clear_tbuf() { Mword i; - for (i=0; i<_max_entries; i++) + for (i = 0; i < _max_entries; i++) buffer()[i].clear(); _tbuf_act = buffer(); @@ -286,7 +286,7 @@ Jdb_tbuf::entries() Mword cnt = 0; - for (Mword idx=0; idx