From 4323e178f084712b74f7addcfd470f56e6d5eb7e Mon Sep 17 00:00:00 2001
From: l4check <l4check@d050ee49-bd90-4346-b210-929a50b99cfc>
Date: Sun, 19 Jan 2014 21:01:56 +0000
Subject: [PATCH] update

git-svn-id: http://svn.tudos.org/repos/oc/tudos/trunk@62 d050ee49-bd90-4346-b210-929a50b99cfc
---
 kernel/fiasco/src/kern/arm/bootstrap.cpp | 14 ++++++++++++--
 kernel/fiasco/src/kern/arm/fpu-arm.cpp   | 11 ++++++-----
 2 files changed, 18 insertions(+), 7 deletions(-)

diff --git a/kernel/fiasco/src/kern/arm/bootstrap.cpp b/kernel/fiasco/src/kern/arm/bootstrap.cpp
index 8b97c2d1c..e3c3df0cf 100644
--- a/kernel/fiasco/src/kern/arm/bootstrap.cpp
+++ b/kernel/fiasco/src/kern/arm/bootstrap.cpp
@@ -35,17 +35,28 @@ INTERFACE [arm && armv5]:
 namespace Bootstrap {
 inline void set_asid()
 {}
+
+inline void set_ttbcr()
+{}
 }
 
 //---------------------------------------------------------------------------
 INTERFACE [arm && (armv6 || armv7)]:
 
+#include "kmem_space.h"
+
 namespace Bootstrap {
 inline void
 set_asid()
 {
   asm volatile ("mcr p15, 0, %0, c13, c0, 1" : : "r" (0)); // ASID 0
 }
+
+inline void set_ttbcr()
+{
+  asm volatile("mcr p15, 0, %[ttbcr], c2, c0, 2" // TTBCR
+               : : [ttbcr] "r" (Page::Ttbcr_bits));
+}
 }
 
 //---------------------------------------------------------------------------
@@ -260,8 +271,7 @@ extern "C" void bootstrap_main()
   Bootstrap::do_arm_1176_cache_alias_workaround();
   Bootstrap::set_asid();
 
-  asm volatile("mcr p15, 0, %[ttbcr], c2, c0, 2" // TTBCR
-               : : [ttbcr] "r" (Page::Ttbcr_bits));
+  Bootstrap::set_ttbcr();
   Mem::dsb();
   asm volatile("mcr p15, 0, %[null], c8, c7, 0" // TLBIALL
                : : [null]  "r" (0));
diff --git a/kernel/fiasco/src/kern/arm/fpu-arm.cpp b/kernel/fiasco/src/kern/arm/fpu-arm.cpp
index dede7c0ee..23207e518 100644
--- a/kernel/fiasco/src/kern/arm/fpu-arm.cpp
+++ b/kernel/fiasco/src/kern/arm/fpu-arm.cpp
@@ -257,8 +257,9 @@ Fpu::init(Cpu_number cpu, bool resume)
 {
   copro_enable();
 
-  fpu.cpu(cpu)._fpsid = Fpsid(fpsid_read());
-  if (cpu == Cpu_number::boot_cpu())
+  Fpu &f = fpu.cpu(cpu);
+  f._fpsid = Fpsid(fpsid_read());
+  if (cpu == Cpu_number::boot_cpu() && f._fpsid.arch_version() > 1)
     save_32r = (mvfr0() & 0xf) == 2;
 
   if (!resume)
@@ -266,7 +267,7 @@ Fpu::init(Cpu_number cpu, bool resume)
 
   disable();
 
-  fpu.cpu(cpu).set_owner(0);
+  f.set_owner(0);
 }
 
 IMPLEMENT inline NEEDS ["fpu_state.h", "mem.h", "static_assert.h"]
@@ -285,7 +286,7 @@ Fpu::save_fpu_regs(Fpu_regs *r)
 {
   Mword tmp;
   asm volatile("stc p11, cr0, [%0], #128     \n"
-               "cmp    %1, #0                \n"
+               "cmp    %2, #0                \n"
                "stcnel p11, cr0, [%0], #128  \n"
                : "=r" (tmp) : "0" (r->state), "r" (save_32r));
 }
@@ -296,7 +297,7 @@ Fpu::restore_fpu_regs(Fpu_regs *r)
 {
   Mword tmp;
   asm volatile("ldc    p11, cr0, [%0], #128 \n"
-               "cmp    %1, #0               \n"
+               "cmp    %2, #0               \n"
                "ldcnel p11, cr0, [%0], #128 \n"
                : "=r" (tmp) : "0" (r->state), "r" (save_32r));
 }
-- 
2.39.2