X-Git-Url: https://rtime.felk.cvut.cz/gitweb/l4.git/blobdiff_plain/35719fdd2ff27177690edb32843d32e092a006e3..5658d2ec9c1081516a8868259fa867926e25ab3f:/l4/pkg/drivers-frst/uart/src/uart_s3c2410.cc

diff --git a/l4/pkg/drivers-frst/uart/src/uart_s3c2410.cc b/l4/pkg/drivers-frst/uart/src/uart_s3c2410.cc
index 4748b0025..78503966c 100644
--- a/l4/pkg/drivers-frst/uart/src/uart_s3c2410.cc
+++ b/l4/pkg/drivers-frst/uart/src/uart_s3c2410.cc
@@ -7,6 +7,7 @@
  * Please see the COPYING-GPL-2 file for details.
  */
 #include "uart_s3c2410.h"
+#include "poll_timeout_counter.h"
 
 namespace L4
 {
@@ -28,6 +29,7 @@ namespace L4
     UTXH    = 0x20, // transmit buffer register (little endian, 0x23 for BE)
     URXH    = 0x24, // receive buffer register (little endian, 0x27 for BE)
     UBRDIV  = 0x28, // baud rate divisor register
+    UFRACVAL= 0x2c,
     // 64xx++
     UINTP   = 0x30, // interrupt pending register
     UINTSP  = 0x34, // interrupt source pending register
@@ -83,7 +85,8 @@ namespace L4
   void Uart_s3c::fifo_reset()
   {
     _regs->write<unsigned int>(UFCON, UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET);
-    while (_regs->read<unsigned int>(UFCON) & (UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET))
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFCON) & (UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET)))
       ;
   }
 
@@ -176,13 +179,15 @@ namespace L4
 
   void Uart_s3c2410::wait_for_empty_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & (UFSTAT_2410_Tx_COUNT_MASK | UFSTAT_2410_TxFULL))
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & (UFSTAT_2410_Tx_COUNT_MASK | UFSTAT_2410_TxFULL)))
       ;
   }
 
   void Uart_s3c2410::wait_for_non_full_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & UFSTAT_2410_TxFULL)
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & UFSTAT_2410_TxFULL))
       ;
   }
 
@@ -200,13 +205,15 @@ namespace L4
 
   void Uart_s3c64xx::wait_for_empty_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & (UFSTAT_64XX_Tx_COUNT_MASK | UFSTAT_64XX_TxFULL))
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & (UFSTAT_64XX_Tx_COUNT_MASK | UFSTAT_64XX_TxFULL)))
       ;
   }
 
   void Uart_s3c64xx::wait_for_non_full_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & UFSTAT_64XX_TxFULL)
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & UFSTAT_64XX_TxFULL))
       ;
   }
 
@@ -224,13 +231,15 @@ namespace L4
 
   void Uart_s5pv210::wait_for_empty_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & (UFSTAT_S5PV210_Tx_COUNT_MASK | UFSTAT_S5PV210_TxFULL))
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & (UFSTAT_S5PV210_Tx_COUNT_MASK | UFSTAT_S5PV210_TxFULL)))
       ;
   }
 
   void Uart_s5pv210::wait_for_non_full_tx_fifo() const
   {
-    while (_regs->read<unsigned int>(UFSTAT) & UFSTAT_S5PV210_TxFULL)
+    Poll_timeout_counter i(3000000);
+    while (i.test(_regs->read<unsigned int>(UFSTAT) & UFSTAT_S5PV210_TxFULL))
       ;
   }