X-Git-Url: https://rtime.felk.cvut.cz/gitweb/l4.git/blobdiff_plain/35719fdd2ff27177690edb32843d32e092a006e3..5658d2ec9c1081516a8868259fa867926e25ab3f:/kernel/fiasco/src/lib/uart/uart_s3c2410.cc diff --git a/kernel/fiasco/src/lib/uart/uart_s3c2410.cc b/kernel/fiasco/src/lib/uart/uart_s3c2410.cc index bf91066f4..12ba82378 100644 --- a/kernel/fiasco/src/lib/uart/uart_s3c2410.cc +++ b/kernel/fiasco/src/lib/uart/uart_s3c2410.cc @@ -1,4 +1,5 @@ #include "uart_s3c2410.h" +#include "poll_timeout_counter.h" namespace L4 { @@ -75,7 +76,8 @@ namespace L4 void Uart_s3c::fifo_reset() { _regs->write(UFCON, UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET); - while (_regs->read(UFCON) & (UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET)) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFCON) & (UFCON_RX_FIFO_RESET | UFCON_TX_FIFO_RESET))) ; } @@ -168,13 +170,15 @@ namespace L4 void Uart_s3c2410::wait_for_empty_tx_fifo() const { - while (_regs->read(UFSTAT) & (UFSTAT_2410_Tx_COUNT_MASK | UFSTAT_2410_TxFULL)) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & (UFSTAT_2410_Tx_COUNT_MASK | UFSTAT_2410_TxFULL))) ; } void Uart_s3c2410::wait_for_non_full_tx_fifo() const { - while (_regs->read(UFSTAT) & UFSTAT_2410_TxFULL) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & UFSTAT_2410_TxFULL)) ; } @@ -192,13 +196,15 @@ namespace L4 void Uart_s3c64xx::wait_for_empty_tx_fifo() const { - while (_regs->read(UFSTAT) & (UFSTAT_64XX_Tx_COUNT_MASK | UFSTAT_64XX_TxFULL)) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & (UFSTAT_64XX_Tx_COUNT_MASK | UFSTAT_64XX_TxFULL))) ; } void Uart_s3c64xx::wait_for_non_full_tx_fifo() const { - while (_regs->read(UFSTAT) & UFSTAT_64XX_TxFULL) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & UFSTAT_64XX_TxFULL)) ; } @@ -216,13 +222,15 @@ namespace L4 void Uart_s5pv210::wait_for_empty_tx_fifo() const { - while (_regs->read(UFSTAT) & (UFSTAT_S5PV210_Tx_COUNT_MASK | UFSTAT_S5PV210_TxFULL)) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & (UFSTAT_S5PV210_Tx_COUNT_MASK | UFSTAT_S5PV210_TxFULL))) ; } void Uart_s5pv210::wait_for_non_full_tx_fifo() const { - while (_regs->read(UFSTAT) & UFSTAT_S5PV210_TxFULL) + Poll_timeout_counter i(3000000); + while (i.test(_regs->read(UFSTAT) & UFSTAT_S5PV210_TxFULL)) ; }