update

[l4.git] / l4 / pkg / valgrind / src / valgrind-3.6.0-svn / cachegrind / cg-arm.c

diff --git a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg-arm.c b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg-arm.c
index 27f5d0da9b8fbef2602ba477f44c7bfb3527315f..28edb5766284ec4947e1434b0d8a9782abe477b8 100644 (file)
--- a/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg-arm.c
+++ b/l4/pkg/valgrind/src/valgrind-3.6.0-svn/cachegrind/cg-arm.c
@@ -37,18 +37,18 @@
 
 #include "cg_arch.h"
 
-void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* L2c,
+void VG_(configure_caches)(cache_t* I1c, cache_t* D1c, cache_t* LLc,
                            Bool all_caches_clo_defined)
 {
    // Set caches to default (for Cortex-A8 ?)
    *I1c = (cache_t) {  16384, 4, 64 };
    *D1c = (cache_t) {  16384, 4, 64 };
-   *L2c = (cache_t) { 262144, 8, 64 };
+   *LLc = (cache_t) { 262144, 8, 64 };
 
    if (!all_caches_clo_defined) {
       VG_(message)(Vg_DebugMsg, 
                    "Warning: Cannot auto-detect cache config on ARM, using one "
-                   "or more defaults ");
+                   "or more defaults\n");
    }
 }