update

[l4.git] / kernel / fiasco / src / kern / arm / cpu-arm.cpp

diff --git a/kernel/fiasco/src/kern/arm/cpu-arm.cpp b/kernel/fiasco/src/kern/arm/cpu-arm.cpp
index d50a3a491fa96a83e13400718d9f2a0392f2dcee..d860118507f303806558a4b4a60f639b11d54d47 100644 (file)
--- a/kernel/fiasco/src/kern/arm/cpu-arm.cpp
+++ b/kernel/fiasco/src/kern/arm/cpu-arm.cpp
@@ -35,6 +35,7 @@ private:
   unsigned _phys_id;
 };
 
+// ------------------------------------------------------------------------
 INTERFACE [arm && armv5]:
 
 EXTENSION class Cpu
@@ -137,7 +138,7 @@ public:
 
     Cp15_c1_generic         = Cp15_c1_mmu
                               | (Config::Cp15_c1_use_alignment_check ?  Cp15_c1_alignment_check : 0)
-                             //| Cp15_c1_branch_predict
+                             | Cp15_c1_branch_predict
                              | Cp15_c1_high_vector
                              | (Config::Cp15_c1_use_a9_swp_enable ?  Cp15_c1_sw : 0),
 
@@ -339,9 +340,9 @@ Cpu::init_tz()
 
   // enable nonsecure access to vfp coprocessor
   asm volatile("mov r0, #0xc00;"
-               "mcr p15, 0, r0, c1, c1, 2;"
-               : : : "r0"
-               );
+               "mcr p15, 0, r0, c1, c1, 2;"
+               : : : "r0"
+              );
 
   enable_irq_ovrr();
 }
@@ -353,23 +354,23 @@ Cpu::tz_switch_to_ns(Mword *nonsecure_state)
   volatile register Mword r0 asm("r0") = (Mword)nonsecure_state;
   extern char go_nonsecure;
 
-  asm volatile(        "stmdb sp!, {fp}        \n"
-               "stmdb sp!, {r0}        \n"
-               "mov    r2, sp          \n" // copy sp_svc to sp_mon
-               "cps    #0x16           \n" // switch to monitor mode
-               "mov    sp, r2          \n"
-               "adr    r3, 1f          \n" // save return eip
-               "mrs    r4, cpsr        \n" // save return psr
-               "mov    pc, r1          \n" // go nonsecure!
-               "1:                     \n"
-               "mov    r0, sp          \n" // copy sp_mon to sp_svc
-               "cps    #0x13           \n" // switch to svc mode
-               "mov    sp, r0          \n"
-               "ldmia  sp!, {r0}       \n"
-               "ldmia  sp!, {fp}       \n"
-               : : "r" (r0), "r" (&go_nonsecure)
-               : "r2", "r3", "r4", "r5", "r6", "r7",
-                         "r8", "r9", "r10", "r12", "r14", "memory");
+  asm volatile("stmdb sp!, {fp}   \n"
+               "stmdb sp!, {r0}   \n"
+               "mov    r2, sp     \n" // copy sp_svc to sp_mon
+               "cps    #0x16      \n" // switch to monitor mode
+               "mov    sp, r2     \n"
+               "adr    r3, 1f     \n" // save return eip
+               "mrs    r4, cpsr   \n" // save return psr
+               "mov    pc, r1     \n" // go nonsecure!
+               "1:                \n"
+               "mov    r0, sp     \n" // copy sp_mon to sp_svc
+               "cps    #0x13      \n" // switch to svc mode
+               "mov    sp, r0     \n"
+               "ldmia  sp!, {r0}  \n"
+               "ldmia  sp!, {fp}  \n"
+               : : "r" (r0), "r" (&go_nonsecure)
+               : "r2", "r3", "r4", "r5", "r6", "r7",
+                 "r8", "r9", "r10", "r12", "r14", "memory");
 }
 
 PUBLIC static inline
@@ -412,9 +413,9 @@ void
 Cpu::enable_irq_ovrr()
 {
   // set IRQ/FIQ/Abort override bits
-  asm volatile("mov r0, #0x1c0;            \n"
-              "mcr p15, 0, r0, c1, c1, 3; \n"
-               : : : "r0");
+  asm volatile("mov r0, #0x1c0            \n"
+               "mcr p15, 0, r0, c1, c1, 3 \n"
+               : : : "r0");
 }
 
 IMPLEMENTATION [!tz || !armca9]: