#include "apic.h"
#include "boot_info.h"
#include "checksum.h"
-#include "cmdline.h"
#include "config.h"
#include "cpu.h"
#include "initcalls.h"
#include "kernel_uart.h"
#include "kernel_task.h"
#include "kmem.h"
+#include "koptions.h"
#include "logdefs.h"
#include "mem_layout.h"
#include "pic.h"
#include "regdefs.h"
#include "static_init.h"
#include "terminate.h"
-#include "thread.h"
+#include "thread.h"
#include "thread_state.h"
#include "timer.h"
+#include "timer_tick.h"
#include "trap_state.h"
-#include "virq.h"
#include "vkey.h"
#include "watchdog.h"
char Jdb::_connected; // Jdb::init() was done
// explicit single_step command
-Per_cpu<char> DEFINE_PER_CPU Jdb::permanent_single_step;
+DEFINE_PER_CPU Per_cpu<char> Jdb::permanent_single_step;
volatile char Jdb::msr_test; // = 1: trying to access an msr
volatile char Jdb::msr_fail; // = 1: MSR access failed
-Per_cpu<char> DEFINE_PER_CPU Jdb::code_ret; // current instruction is ret/iret
-Per_cpu<char> DEFINE_PER_CPU Jdb::code_call;// current instruction is call
-Per_cpu<char> DEFINE_PER_CPU Jdb::code_bra; // current instruction is jmp/jxx
-Per_cpu<char> DEFINE_PER_CPU Jdb::code_int; // current instruction is int x
+DEFINE_PER_CPU Per_cpu<char> Jdb::code_ret; // current instruction is ret/iret
+DEFINE_PER_CPU Per_cpu<char> Jdb::code_call;// current instruction is call
+DEFINE_PER_CPU Per_cpu<char> Jdb::code_bra; // current instruction is jmp/jxx
+DEFINE_PER_CPU Per_cpu<char> Jdb::code_int; // current instruction is int x
// special single step state
-Per_cpu<Jdb::Step_state> DEFINE_PER_CPU Jdb::ss_state;
-Per_cpu<int> DEFINE_PER_CPU Jdb::ss_level; // current call level
+DEFINE_PER_CPU Per_cpu<Jdb::Step_state> Jdb::ss_state;
+DEFINE_PER_CPU Per_cpu<int> Jdb::ss_level; // current call level
const Unsigned8*Jdb::debug_ctrl_str; // string+length for remote control of
int Jdb::debug_ctrl_len; // Jdb via enter_kdebugger("*#");
Pic::Status Jdb::pic_status;
-Per_cpu<unsigned> DEFINE_PER_CPU Jdb::apic_tpr;
-Per_cpu<int> DEFINE_PER_CPU Jdb::jdb_irqs_disabled;
+DEFINE_PER_CPU Per_cpu<unsigned> Jdb::apic_tpr;
+DEFINE_PER_CPU Per_cpu<int> Jdb::jdb_irqs_disabled;
int (*Jdb::bp_test_log_only)();
int (*Jdb::bp_test_sstep)();
IMPLEMENT FIASCO_INIT FIASCO_NOINLINE
void Jdb::init()
{
- if (strstr (Cmdline::cmdline(), " -nojdb"))
+ if (Koptions::o()->opt(Koptions::F_nojdb))
return;
- if (strstr (Cmdline::cmdline(), " -jdb_never_stop"))
+ if (Koptions::o()->opt(Koptions::F_jdb_never_stop))
never_break = 1;
init_serial_console();
return _connected;
}
+PROTECTED static inline
+template< typename T >
+void
+Jdb::set_monitored_address(T *dest, T val)
+{
+ *dest = val;
+}
+
+PROTECTED static inline
+template< typename T >
+T
+Jdb::monitor_address(unsigned current_cpu, T *addr)
+{
+ if (!*addr && Cpu::cpus.cpu(current_cpu).has_monitor_mwait())
+ {
+ asm volatile ("monitor \n" : : "a"(addr), "c"(0), "d"(0) );
+ Mword irq_sup = Cpu::cpus.cpu(current_cpu).has_monitor_mwait_irq() ? 1 : 0;
+ asm volatile ("mwait \n" : : "a"(0x00), "c"(irq_sup) );
+ }
+
+ return *addr;
+}
+
#if 0
PUBLIC static
}
-static Per_cpu<Proc::Status> DEFINE_PER_CPU jdb_saved_flags;
+DEFINE_PER_CPU static Per_cpu<Proc::Status> jdb_saved_flags;
// disable interrupts before entering the kernel debugger
IMPLEMENT
{
Watchdog::disable();
pic_status = Pic::disable_all_save();
+ if (Config::getchar_does_hlt_works_ok)
+ Timer_tick::disable(0);
}
if (Io_apic::active() && Apic::is_present())
{
apic_tpr.cpu(cpu) = Apic::tpr();
Apic::tpr(APIC_IRQ_BASE - 0x10);
}
-
- if (cpu == 0 && Config::getchar_does_hlt && Config::getchar_does_hlt_works_ok)
+
+ if (cpu == 0 && Config::getchar_does_hlt_works_ok)
{
// set timer interrupt does nothing than wakeup from hlt
- Idt::set_vectors_stop();
- Timer::enable();
+ Timer_tick::set_vectors_stop();
+ Timer_tick::enable(0);
}
}
- if (cpu == 0 && Config::getchar_does_hlt && Config::getchar_does_hlt_works_ok)
+ if (cpu == 0 && Config::getchar_does_hlt_works_ok)
// explicit enable interrupts because the timer interrupt is
// needed to wakeup from "hlt" state in getchar(). All other
// interrupts are disabled at the pic.
}
// reset timer interrupt vector
- if (cpu == 0 && Config::getchar_does_hlt && Config::getchar_does_hlt_works_ok)
+ if (cpu == 0 && Config::getchar_does_hlt_works_ok)
Idt::set_vectors_run();
// reset interrupt flags
}
-PUBLIC
-static int
-Jdb::get_register(char *reg)
-{
- union
- {
- char c[4];
- Unsigned32 v;
- } reg_name;
-
- int i;
-
- putchar(reg_name.c[0] = Jdb_screen::Reg_prefix);
-
- for (i=1; i<3; i++)
- {
- int c = getchar();
- if (c == KEY_ESC)
- return false;
- putchar(reg_name.c[i] = c & 0xdf);
- }
-
- reg_name.c[3] = '\0';
-
- for (i=0; i<9; i++)
- if (reg_name.v == *((unsigned*)(Jdb_screen::Reg_names[i])))
- break;
-
- if (i==9)
- return false;
-
- *reg = i+1;
- return true;
-}
-
struct On_dbg_stack
{
Mword sp;
if (foreach_cpu(On_dbg_stack(sp), false))
return 0;
- if (sp >= boot_stack - 8192 && sp <= boot_stack + 8192)
+ if (!Helping_lock::threading_system_active)
return 0;
return static_cast<Thread*>(context_of((const void*)sp));
else
{
// user address, use temporary mapping
- phys = Address(task->mem_space()->virt_to_phys (addr));
+ phys = Address(task->virt_to_phys (addr));
if (phys == ~0UL)
- phys = task->mem_space()->virt_to_phys_s0 ((void*)addr);
+ phys = task->virt_to_phys_s0((void*)addr);
if (phys == ~0UL)
return -1;
else
{
// user address, use temporary mapping
- phys = Address(task->mem_space()->virt_to_phys (addr));
+ phys = Address(task->virt_to_phys(addr));
if (phys == ~0UL)
- phys = task->mem_space()->virt_to_phys_s0 ((void*)addr);
+ phys = task->virt_to_phys_s0((void*)addr);
if (phys == ~0UL)
return -1;
if (!task)
// phys requested
phys = virt;
- else if (task == Config::kernel_taskno
- || (!Kmem::is_io_bitmap_page_fault(virt)
- && Kmem::is_kmem_page_fault(virt, 0)))
+ else if ( !Kmem::is_io_bitmap_page_fault(virt)
+ && Kmem::is_kmem_page_fault(virt, 0))
// kernel address
phys = Kmem::virt_to_phys((const void*)virt);
else
// user address
- phys = task->mem_space()->virt_to_phys_s0((void*)virt);
+ phys = task->virt_to_phys_s0((void*)virt);
if (phys == ~0UL)
return false;
{
Guessed_thread_state state = s_unknown;
Mword *ktop = (Mword*)((Mword)context_of(t->get_kernel_sp()) +
- Config::thread_block_size);
+ Context::Size);
for (int i=-1; i>-26; i--)
{
}
}
- if (state == s_unknown && (t->state() & Thread_ipc_mask))
+ if (state == s_unknown && (t->state(false) & Thread_ipc_mask))
state = s_ipc;
return state;
&& entry_frame.cpu(cpu)->_trapno >= 10
&& entry_frame.cpu(cpu)->_trapno <= 14)
snprintf(error_buffer.cpu(cpu)+pos, sizeof(error_buffer.cpu(0))-pos,
- "(ERR="L4_PTR_FMT")", entry_frame.cpu(cpu)->_err);
+ "(ERR=" L4_PTR_FMT ")", entry_frame.cpu(cpu)->_err);
return 1;
}
Jdb::handle_nested_trap(Jdb_entry_frame *e)
{
// re-enable interrupts if we need them because they are disabled
- if (Config::getchar_does_hlt && Config::getchar_does_hlt_works_ok)
+ if (Config::getchar_does_hlt_works_ok)
Proc::sti();
switch (e->_trapno)
break;
case 3:
cursor(Jdb_screen::height(), 1);
- printf("\nSoftware breakpoint inside jdb at "L4_PTR_FMT"\n",
- e->ip()-1);
+ printf("\nSoftware breakpoint inside jdb at " L4_PTR_FMT "\n",
+ e->ip()-1);
break;
case 13:
switch (msr_test)
break;
default:
cursor(Jdb_screen::height(), 1);
- printf("\nGeneral Protection (eip="L4_PTR_FMT","
- " err="L4_PTR_FMT") -- jdb bug?\n",
+ printf("\nGeneral Protection (eip=" L4_PTR_FMT ","
+ " err=" L4_PTR_FMT ") -- jdb bug?\n",
e->ip(), e->_err);
break;
}
break;
default:
cursor(Jdb_screen::height(), 1);
- printf("\nInvalid access (trap=%02lx err="L4_PTR_FMT
- " pfa="L4_PTR_FMT" eip="L4_PTR_FMT") "
+ printf("\nInvalid access (trap=%02lx err=" L4_PTR_FMT
+ " pfa=" L4_PTR_FMT " eip=" L4_PTR_FMT ") "
"-- jdb bug?\n",
e->_trapno, e->_err, e->_cr2, e->ip());
break;
Jdb::leave_getchar()
{}
-
//----------------------------------------------------------------------------
IMPLEMENTATION [(ia32 || amd64) && mp]:
void
Jdb::send_nmi(unsigned cpu)
{
- Apic::mp_send_ipi(Cpu::cpus.cpu(cpu).phys_id(), 0, Apic::APIC_IPI_NMI);
+ Apic::mp_send_ipi(Apic::apic.cpu(cpu)->apic_id(), 0, Apic::APIC_IPI_NMI);
}
projects / l4.git / blobdiff