update

[l4.git] / kernel / fiasco / src / kern / arm / ivt.S

diff --git a/kernel/fiasco/src/kern/arm/ivt.S b/kernel/fiasco/src/kern/arm/ivt.S
index 8c4c0bb3944dfe2cc0a0df1c280a210a1a3a1423..9bedb922228b7e8d2ba1d19fdc185790077f9a8e 100644 (file)
--- a/kernel/fiasco/src/kern/arm/ivt.S
+++ b/kernel/fiasco/src/kern/arm/ivt.S
@@ -63,8 +63,11 @@
        sub     lr, lr, #\adjust
 .endif
 #ifdef CONFIG_ARM_V6PLUS
-       clrex
+#ifdef CONFIG_ARM_1136
        // todo: do clrex with strex for CPUs without clrex
+#else
+       clrex
+#endif
 #endif
 .if \atomic_fixup
         atomic_fixup lr 0
@@ -108,7 +111,7 @@
        ldrne   lr, [sp, #RF(SVC_LR, -RF_SIZE)] @ load old kernel lr
        rfedb   sp
 #else
-       msr     spsr, lr                        @ Load SPSR from kernel_lr
+       msr     spsr_cfsx, lr                   @ Load SPSR from kernel_lr
        ldr     lr, [sp, #RF(PC, -RF_SIZE)]     @ copy PC on psr field for
        str     lr, [sp, #RF(PSR, -RF_SIZE)]    @   final ldmdb and proper ksp
         ldrne   lr, [sp, #RF(SVC_LR, -RF_SIZE)]        @ load old kernel lr
@@ -230,7 +233,7 @@ fast_ret_from_irq:
 
        /* Return */
        ldr     lr, [sp, #RF(PSR,0)]
-       msr     spsr, lr
+       msr     spsr_cfsx, lr
 @      ldmia   sp, {sp,lr}^ @ done lazy
        add     sp, sp, #RF_SIZE
        ldr     lr, [sp, #RF(PC, -RF_SIZE)]
@@ -257,8 +260,10 @@ exception_vector:
 /* locations to pass lr and spsr from one mode to the other
    these are globally shared !!! */
 .section       .excp.text,"xa"
+#if !defined(CONFIG_ARM_V6PLUS)
 s_lr:  .word   0
 s_spsr:        .word   0
+#endif
 
 /***************************************************************************
 **
@@ -322,7 +327,11 @@ prefetch_abort: @ A real prefetch abort occured --- handled as a page fault
        mrc     p15, 0, r1, c5, c0, 1   @ Load IFSR into r1
        bic     r1, r1, #0x00ff0000
        orr     r1, r1, #0x00330000     @ Set read bit and prefetch abort
-       ldr     r0, [sp, #RF(PC, 5*4)]  @ get PC from RF and use as pfa
+#if defined(CONFIG_ARM_V6PLUS) && !defined(CONFIG_ARM_1136) && !defined(CONFIG_ARM_MPCORE)
+       mrc     p15, 0, r0, c6, c0, 2   @ Read fault address, for T2: pfa != pc
+#else
+       ldr     r0, [sp, #RF(PC, 5*4)]  @ Get PC from RF and use as pfa
+#endif
        mov     r2, r0
        add     r3, sp, #(5*4)
        stmdb   sp!, {r0, r1}
@@ -528,9 +537,7 @@ irq_entry:
         msr    cpsr_c, #0xd3 // disable IRQs
        add     sp, sp, #20
        return_from_exception
-#if 1  
 1:     .word   irq_handler
-#endif
 
 
 /******************************************************************************
@@ -551,9 +558,7 @@ fiq_entry:
        msr     cpsr_c, #0xd3 // disable IRQs
        add     sp, sp, #20
        return_from_exception
-#if 1  
 1:     .word   irq_handler
-#endif
 
 
 /**************************************************************************/
@@ -599,8 +604,8 @@ sys_call_table:
        .word sys_kdb_ke
        .word sys_kdb_ke
 /*SYSCALL(ipc)*/
-       .word ipc_short_cut_wrapper
-       .word sys_arm_cache_op
+       .word sys_ipc_wrapper
+       .word sys_arm_mem_op
 SYSCALL(invoke_debug)
        .word sys_kdb_ke
        .word sys_kdb_ke
@@ -639,7 +644,8 @@ leave_by_vcpu_upcall:
        /* restore original IP */
        CONTEXT_OF r1, sp
 
-       ldr     r2, [r1, #(OFS__THREAD__VCPU_STATE)]
+       /* access_vcpu() for the local case */
+       ldr     r2, [r1, #(OFS__THREAD__USER_VCPU)]
        add     r2, r2, #(VAL__SIZEOF_TRAP_STATE - RF_SIZE)
 
        ldr     r0, [r1, #(OFS__THREAD__EXCEPTION_IP)]
@@ -678,8 +684,9 @@ leave_by_vcpu_upcall:
        ldr     r0, [r2, #(-8 + OFS__VCPU_STATE__ENTRY_IP)]
 
        str     r0, [sp, #RF(PC, 0)]
+       add     r0, r2, #(-8)
 
-       b __iret
+       b       __iret
 
 
 kernel_prefetch_abort_label: .string "Kernel prefetch abort"
@@ -690,7 +697,7 @@ fiq_label:               .string "FIQ entry"
        kdebug entry
  **********************************************************************/
 
-.macro DEBUGGER_ENTRY errorcode
+.macro DEBUGGER_ENTRY type
 #ifdef CONFIG_JDB
        str     sp, [sp, #(RF(USR_SP, -RF_SIZE))] @ save r[13]
        sub     sp, sp, #(RF_SIZE)
@@ -702,7 +709,8 @@ fiq_label:               .string "FIQ entry"
 
        stmdb   sp!, {r0 - r12}
        mov     r0, #-1                 @ pfa
-       mov     r1, #\errorcode         @ err
+       mov     r1, #0x00e00000         @ err
+       orr     r1, #\type              @ + type
        stmdb   sp!, {r0, r1}
 
        mov     r0, sp
@@ -729,7 +737,12 @@ fiq_label:              .string "FIQ entry"
        .global kern_kdebug_entry
        .align 4
 kern_kdebug_entry:
-       DEBUGGER_ENTRY 0x00e00000
+       DEBUGGER_ENTRY 0
+
+       .global kern_kdebug_sequence_entry
+       .align 4
+kern_kdebug_sequence_entry:
+       DEBUGGER_ENTRY 1
 
 
 #ifdef CONFIG_MP
@@ -737,7 +750,7 @@ kern_kdebug_entry:
        .global kern_kdebug_ipi_entry
        .align 4
 kern_kdebug_ipi_entry:
-       DEBUGGER_ENTRY 0x00f00000
+       DEBUGGER_ENTRY 2
        .previous
 #endif
 
@@ -745,6 +758,14 @@ kern_kdebug_ipi_entry:
 
 #ifdef CONFIG_ARM_TZ
 
+.macro ISB_OP reg
+#ifdef CONFIG_ARM_V7
+       isb
+#else
+       mcr p15, 0, lr, c7, c5, 4       @ cp15isb
+#endif
+.endm
+
 /**********************************************************************
  * Secure and Nonsecure switching stuff
  *
@@ -813,7 +834,7 @@ kern_kdebug_ipi_entry:
        // switch to non-secure world
        mov     r1, #1
        mcr     p15, 0, r1, c1, c1, 0
-       isb
+       ISB_OP  r1
        
        mrc     p15, 0, r1, c2, c0, 0   @ read CP15_TTB0
        stmia   r0!, {r1}
@@ -851,10 +872,23 @@ kern_kdebug_ipi_entry:
        mrc     p15, 0, r1, c13, c0, 1  @ read CP15_CID
        stmia   r0!, {r1}
 
+       // tls regs are banked
+       mrc     p15, 0, r1, c13, c0, 2  @ read CP15_TLS1
+       stmia   r0!, {r1}
+
+       mrc     p15, 0, r1, c13, c0, 3  @ read CP15_TLS2
+       stmia   r0!, {r1}
+
+       mrc     p15, 0, r1, c13, c0, 4  @ read CP15_TLS3
+       stmia   r0!, {r1}
+
+       mrc     p10, 7, r1, cr8, cr0, 0 @ fpexc
+       stmia   r0!, {r1}
+
        // switch to secure world
        mov     r1, #0
        mcr     p15, 0, r1, c1, c1, 0
-       isb
+       ISB_OP  r1
        
        mrc     p15, 0, r1, c5, c0, 0   @ read CP15_DFSR
        stmia   r0!, {r1}
@@ -919,11 +953,11 @@ kern_kdebug_ipi_entry:
        and     r1, r1, #0x1c0
        mcr     p15, 0, r1, c12, c1, 1
 
-#if 0
+#if 1
        // switch to non-secure world
        mov     r1, #1
        mcr     p15, 0, r1, c1, c1, 0
-       isb
+       ISB_OP  r1
 
        ldmia   r0!, {r1}
        mcr     p15, 0, r1, c2, c0, 0   @ write CP15_TTB0
@@ -961,12 +995,23 @@ kern_kdebug_ipi_entry:
        ldmia   r0!, {r1}
        mcr     p15, 0, r1, c13, c0, 1  @ write CP15_CID
 
+       // tls regs are banked
+       ldmia   r0!, {r1}
+       mcr     p15, 0, r1, c13, c0, 2  @ write CP15_TLS1
+
+       ldmia   r0!, {r1}
+       mcr     p15, 0, r1, c13, c0, 3  @ write CP15_TLS2
+
+       ldmia   r0!, {r1}
+       mcr     p15, 0, r1, c13, c0, 4  @ write CP15_TLS3
+
+       ldmia   r0!, {r1}
+        mcr p10, 7, r1, cr8, cr0, 0     @ fpexc
+
        // switch to secure world
        mov     r1, #0
        mcr     p15, 0, r1, c1, c1, 0
-       isb
-
-       xxx
+       ISB_OP  r1
 #endif
 
        // load gen-regs
@@ -1023,13 +1068,13 @@ kern_kdebug_ipi_entry:
 .macro SWITCH_TO_NONSECURE_MODE
        mov     lr, #0xf
        mcr     p15, 0, lr, c1, c1, 0
-       isb
+       ISB_OP  lr
 .endm
 
 .macro SWITCH_TO_SECURE_MODE
        mov     lr, #0x0
        mcr     p15, 0, lr, c1, c1, 0
-       isb
+       ISB_OP  lr
 .endm