update

[l4.git] / kernel / fiasco / src / kern / arm / bsp / kirkwood / pic-arm-kirkwood.cpp

diff --git a/kernel/fiasco/src/kern/arm/bsp/kirkwood/pic-arm-kirkwood.cpp b/kernel/fiasco/src/kern/arm/bsp/kirkwood/pic-arm-kirkwood.cpp
index 3ce543265ae28988bf6e2f36fadaf4cf9985df8f..64837a06dc7d82e431ded06de6bc8769da1aa9ed 100644 (file)
--- a/kernel/fiasco/src/kern/arm/bsp/kirkwood/pic-arm-kirkwood.cpp
+++ b/kernel/fiasco/src/kern/arm/bsp/kirkwood/pic-arm-kirkwood.cpp
@@ -1,42 +1,48 @@
-INTERFACE [arm && kirkwood]:
-
-#include "kmem.h"
-
-class Irq_base;
-
-EXTENSION class Pic
-{
-public:
-  enum
-  {
-    Main_Irq_cause_low_reg     = Mem_layout::Pic_map_base + 0x20200,
-    Main_Irq_mask_low_reg      = Mem_layout::Pic_map_base + 0x20204,
-    Main_Fiq_mask_low_reg      = Mem_layout::Pic_map_base + 0x20208,
-    Endpoint_irq_mask_low_reg  = Mem_layout::Pic_map_base + 0x2020c,
-    Main_Irq_cause_high_reg    = Mem_layout::Pic_map_base + 0x20210,
-    Main_Irq_mask_high_reg     = Mem_layout::Pic_map_base + 0x20214,
-    Main_Fiq_mask_high_reg     = Mem_layout::Pic_map_base + 0x20218,
-    Endpoint_irq_mask_high_reg = Mem_layout::Pic_map_base + 0x2021c,
-
-    Bridge_int_num = 1,
-  };
-};
-
 //-------------------------------------------------------------------
 IMPLEMENTATION [arm && kirkwood]:
 
+#include "assert.h"
 #include "config.h"
 #include "initcalls.h"
 #include "io.h"
 #include "irq_chip_generic.h"
 #include "irq_mgr.h"
+#include "kmem.h"
+#include "mmio_register_block.h"
 
-class Irq_chip_kirkwood : public Irq_chip_gen
+class Irq_chip_kirkwood : public Irq_chip_gen, private Mmio_register_block
 {
+private:
+  enum
+  {
+    Main_Irq_cause_low_reg     = 0x20200,
+    Main_Irq_mask_low_reg      = 0x20204,
+    Main_Fiq_mask_low_reg      = 0x20208,
+    Endpoint_irq_mask_low_reg  = 0x2020c,
+    Main_Irq_cause_high_reg    = 0x20210,
+    Main_Irq_mask_high_reg     = 0x20214,
+    Main_Fiq_mask_high_reg     = 0x20218,
+    Endpoint_irq_mask_high_reg = 0x2021c,
+
+    Bridge_int_num = 1,
+  };
+
 public:
-  Irq_chip_kirkwood() : Irq_chip_gen(64) {}
+  Irq_chip_kirkwood()
+  : Irq_chip_gen(64),
+    Mmio_register_block(Kmem::mmio_remap(Mem_layout::Pic_phys_base))
+  {
+    // Disable all interrupts
+    write<Unsigned32>(0U, Main_Irq_mask_low_reg);
+    write<Unsigned32>(0U, Main_Fiq_mask_low_reg);
+    write<Unsigned32>(0U, Main_Irq_mask_high_reg);
+    write<Unsigned32>(0U, Main_Fiq_mask_high_reg);
+    // enable bridge (chain) IRQ
+    modify<Unsigned32>(1 << Bridge_int_num, 0, Main_Irq_mask_low_reg);
+  }
+
   unsigned set_mode(Mword, unsigned) { return Irq_base::Trigger_level; }
-  void set_cpu(Mword, unsigned) {}
+  void set_cpu(Mword, Cpu_number) {}
   void ack(Mword) { /* ack is empty */ }
 };
 
@@ -45,8 +51,8 @@ void
 Irq_chip_kirkwood::mask(Mword irq)
 {
   assert (cpu_lock.test());
-  Io::clear<Unsigned32>(1 << (irq & 0x1f),
-                       Pic::Main_Irq_mask_low_reg + ((irq & 0x20) >> 1));
+  modify<Unsigned32>(0, 1 << (irq & 0x1f),
+                     Main_Irq_mask_low_reg + ((irq & 0x20) >> 1));
 }
 
 PUBLIC
@@ -63,8 +69,8 @@ void
 Irq_chip_kirkwood::unmask(Mword irq)
 {
   assert(cpu_lock.test());
-  Io::set<Unsigned32>(1 << (irq & 0x1f),
-                      Pic::Main_Irq_mask_low_reg + ((irq & 0x20) >> 1));
+  modify<Unsigned32>(1 << (irq & 0x1f), 0,
+                     Main_Irq_mask_low_reg + ((irq & 0x20) >> 1));
 }
 
 static Static_object<Irq_mgr_single_chip<Irq_chip_kirkwood> > mgr;
@@ -74,14 +80,6 @@ void Pic::init()
 {
   Irq_mgr::mgr = mgr.construct();
 
-  // Disable all interrupts
-  Io::write<Unsigned32>(0U, Main_Irq_mask_low_reg);
-  Io::write<Unsigned32>(0U, Main_Fiq_mask_low_reg);
-  Io::write<Unsigned32>(0U, Main_Irq_mask_high_reg);
-  Io::write<Unsigned32>(0U, Main_Fiq_mask_high_reg);
-
-  // enable bridge (chain) IRQ
-  Io::set<Unsigned32>(1 << Bridge_int_num, Main_Irq_mask_low_reg);
 }
 
 IMPLEMENT inline
@@ -92,15 +90,16 @@ IMPLEMENT inline
 void Pic::restore_all(Status)
 {}
 
-PUBLIC static inline NEEDS["io.h"]
-Unsigned32 Irq_chip_kirkwood::pending()
+PUBLIC inline
+Unsigned32
+Irq_chip_kirkwood::pending()
 {
   Unsigned32 v;
 
-  v = Io::read<Unsigned32>(Pic::Main_Irq_cause_low_reg);
+  v = read<Unsigned32>(Main_Irq_cause_low_reg);
   if (v & 1)
     {
-      v = Io::read<Unsigned32>(Pic::Main_Irq_cause_high_reg);
+      v = read<Unsigned32>(Main_Irq_cause_high_reg);
       for (int i = 1; i < 32; ++i)
        if ((1 << i) & v)
          return 32 + i;
@@ -116,7 +115,7 @@ extern "C"
 void irq_handler()
 {
   Unsigned32 i;
-  while ((i = Irq_chip_kirkwood::pending()) < 64)
+  while ((i = mgr->c.pending()) < 64)
     mgr->c.handle_irq<Irq_chip_kirkwood>(i, 0);
 }