* \return The index into the capability table stored in the capability
* selector (i.e., the most significant bits of the selector).
*/
- unsigned long cap() const { return _raw >> 12; }
+ Cap_index cap() const { return Cap_index(_raw >> 12); }
/**
* Get the operation stored in this selector (see L4_obj_ref::Operation).
* \param op the operation to be encoded in bits 0..3.
*/
explicit L4_obj_ref(Mword cap, Operation op = None) : _raw(cap | op) {}
+ explicit L4_obj_ref(Cap_index cap, Operation op = None)
+ : _raw((cxx::int_value<Cap_index>(cap) << L4_obj_ref::Cap_shift) | op) {}
/**
* Create a capability selector (index 0) with the given operation.
Label_log = -13L, ///< Protocol ID for log / vcon objects.
Label_scheduler = -14L, ///< Protocol ID for scheduler objects.
Label_factory = -15L, ///< Protocol ID for factory objects.
- Label_vm = -16L, ///< Protocol ID for VM objects (used for create
+ Label_vm = -16L, ///< Factory ID for VM objects (used for create
/// operations on a factory).
+ Label_dma_space = -17L, ///< Factory ID for an DMA address space
+ Label_irq_sender = -18L, ///< Protocol for IRQ sender objects.
+ Label_irq_mux = -19L, ///< Protocol for IRQ multiplexer objects.
Label_semaphore = -20L, ///< Protocol ID for semaphore objects.
+ Label_iommu = -22L, ///< Protocol ID for IOMMUs
+ Max_factory_label = Label_iommu,
};
private:
Mword _tag;
* @param clock Current value of kernel clock
* @return The receive timeout in micro seconds.
*/
- Unsigned64 microsecs_abs(Utcb *u) const;
+ Unsigned64 microsecs_abs(Utcb const *u) const;
private:
enum
class L4_exception_ipc
{};
-class L4_semaphore
-{
-public:
- Smword counter;
- Mword flags;
-};
-
/**
* Constants for error codes returned by kernel objects.
*/
EExists = 17, ///< Some object does already exist.
ENodev = 19, ///< Objects of the specified type cannot be created.
EInval = 22, ///< Invalid parameters passed.
+ ERange = 34, ///< Parameter out of range
ENosys = 38, ///< No such operation.
EBadproto = 39, ///< Protocol not supported by object.
EAddrnotavail = 99, ///< The given address is not available.
+ EMsgtooshort = 1001, ///< Incoming IPC message too short
};
};
+class L4_cpu_set_descr
+{
+private:
+ Mword _w;
+
+public:
+ Order granularity() const
+ {
+ Mword g = (_w >> 24) & 0xff;
+ if (g > 24) g = 24; // limit granularity to 2**24
+ return Order(g);
+ }
+
+ Cpu_number offset() const
+ { return cxx::mask_lsb(Cpu_number(_w & 0x00ffffff), granularity()); }
+};
+
+class L4_cpu_set : public L4_cpu_set_descr
+{
+private:
+ Mword _map;
+
+public:
+ bool contains(Cpu_number cpu) const
+ {
+ if (offset() > cpu)
+ return false;
+
+ cpu -= offset();
+ cpu >>= granularity();
+ if (cpu >= Cpu_number(MWORD_BITS))
+ return false;
+
+ return (_map >> cxx::int_value<Cpu_number>(cpu)) & 1;
+ }
+
+ template<typename MAP>
+ Cpu_number first(MAP const &bm, Cpu_number max) const
+ {
+ Cpu_number cpu = offset();
+
+ for (;;)
+ {
+ Cpu_number b = (cpu - offset()) >> granularity();
+ if (cpu >= max || b >= Cpu_number(MWORD_BITS))
+ return max;
+
+ if (!((_map >> cxx::int_value<Cpu_number>(b)) & 1))
+ {
+ cpu += Cpu_number(1) << granularity();
+ continue;
+ }
+
+ if (bm.get(cpu))
+ return cpu;
+
+ ++cpu;
+ }
+ }
+};
+
+struct L4_sched_param
+{
+ L4_cpu_set cpus;
+ Smword sched_class; // legacy prio when positive
+ Mword length; // sizeof (...)
+};
+
+struct L4_sched_param_legacy
+{
+ L4_cpu_set cpus;
+ Smword prio; // must be positive, overlays with sched_class
+ Mword quantum;
+};
+
+
//----------------------------------------------------------------------------
INTERFACE [ia32 || ux]:
enum { Msg_size = 16 };
};
-
//----------------------------------------------------------------------------
INTERFACE [arm]:
EXTENSION class L4_exception_ipc
{
public:
- enum { Msg_size = 20 };
+ enum { Msg_size = 21 };
};
-
//----------------------------------------------------------------------------
INTERFACE [amd64]:
enum { Msg_size = 23 };
};
+//----------------------------------------------------------------------------
INTERFACE [ppc32]:
+
EXTENSION class L4_exception_ipc
{
public:
};
/// The message registers (MRs).
- Mword values[Max_words];
+ union
+ {
+ Mword values[Max_words];
+ Unsigned64 val64[Max_words / (sizeof(Unsigned64) / sizeof(Mword))];
+ } __attribute__((packed));
+
+ static unsigned val64_idx(unsigned validx)
+ { return validx / (sizeof(Unsigned64) / sizeof(Mword)); }
+
+ static unsigned val_idx(unsigned val64_idx)
+ { return val64_idx * (sizeof(Unsigned64) / sizeof(Mword)); }
+
Mword utcb_addr;
/// The buffer descriptor register (BDR).
IMPLEMENT inline NEEDS[<minmax.h>]
Unsigned64
-L4_timeout::microsecs_abs(Utcb *u) const
+L4_timeout::microsecs_abs(Utcb const *u) const
{
int idx = min<int>(_t & 0x3f, Utcb::Max_buffers);
Utcb::Time_val const *top
PUBLIC inline
Unsigned64
-L4_timeout::microsecs(Unsigned64 clock, Utcb *u) const
+L4_timeout::microsecs(Unsigned64 clock, Utcb const *u) const
{
if (is_absolute())
return microsecs_abs(u);
{ _t = (_t & ~Man_mask) | ((w << Man_shift) & Man_mask); }
-
-