update

[l4.git] / kernel / fiasco / src / kern / ia32 / startup-ia32.cpp

diff --git a/kernel/fiasco/src/kern/ia32/startup-ia32.cpp b/kernel/fiasco/src/kern/ia32/startup-ia32.cpp
index 4cd0c14d4b7784ddd401fe7f082c1ead20a20850..049ab2f5fd063856fbc06df218df198cf4503199 100644 (file)
--- a/kernel/fiasco/src/kern/ia32/startup-ia32.cpp
+++ b/kernel/fiasco/src/kern/ia32/startup-ia32.cpp
@@ -18,6 +18,7 @@ IMPLEMENTATION[ia32,amd64]:
 #include "kernel_console.h"
 #include "kernel_task.h"
 #include "kip_init.h"
+#include "kernel_uart.h"
 #include "kmem.h"
 #include "kmem_alloc.h"
 #include "per_cpu_data.h"
@@ -38,19 +39,23 @@ Startup::stage1()
 {
   Boot_info::init();
   Config::init();
+  if (Kernel_uart::init(Kernel_uart::Init_before_mmu))
+    Banner::init();
 }
 
 IMPLEMENT FIASCO_INIT FIASCO_NOINLINE
 void
 Startup::stage2()
 {
-  Banner::init();
   Kip_init::init();
   Kmem_alloc::init();
 
   // initialize initial page tables (also used for other CPUs later)
   Kmem::init_mmu();
 
+  if (Kernel_uart::init(Kernel_uart::Init_after_mmu))
+    Banner::init();
+
   // Initialize cpu-local data management and run constructors for CPU 0
   Per_cpu_data::init_ctors(Kmem_alloc::allocator());
   Per_cpu_data_alloc::alloc(0);
@@ -59,27 +64,12 @@ Startup::stage2()
   // set frequency in KIP to that of the boot CPU
   Kip_init::init_freq(Cpu::cpus.cpu(0));
 
-  if (Io_apic::init())
+  bool use_io_apic = Io_apic::init();
+  if (use_io_apic)
     {
       Config::apic = true;
       Pic::disable_all_save();
       Dirq_io_apic::init();
-
-      // If we use the IOAPIC, we route our timer IRQ to
-      // Config::Apic_timer_vector, even with PIT or RTC
-      enum { Pic_base = 0x20, Pic_irqs = 0x10 };
-
-      if (   Config::scheduler_irq_vector >= Pic_base
-         && Config::scheduler_irq_vector < Pic_base + Pic_irqs)
-       {
-         unsigned const pic_pin
-           = Io_apic::legacy_override(Config::scheduler_irq_vector - Pic_base);
-         // assume the legacy irqs are routet to IO-APIC 0
-         Io_apic_entry e = Io_apic::apic(0)->read_entry(pic_pin);
-         e.vector(Config::Apic_timer_vector);
-         Io_apic::apic(0)->write_entry(pic_pin, e);
-         Config::scheduler_irq_vector = Config::Apic_timer_vector;
-       }
     }
   else
     {
@@ -98,6 +88,31 @@ Startup::stage2()
   Apic::init();
   Ipi::cpu(0).init();
   Timer::init();
+  int timer_irq = Timer::irq_line();
+  if (use_io_apic)
+    {
+      // If we use the IOAPIC, we route our timer IRQ to
+      // Config::Apic_timer_vector, even with PIT or RTC
+      Config::scheduler_irq_vector = Config::Apic_timer_vector;
+
+      if (timer_irq >= 0)
+       {
+         unsigned const pic_pin = Io_apic::legacy_override(timer_irq);
+         // assume the legacy irqs are routet to IO-APIC 0
+         Io_apic_entry e = Io_apic::apic(0)->read_entry(pic_pin);
+         e.vector(Config::Apic_timer_vector);
+         Io_apic::apic(0)->write_entry(pic_pin, e);
+       }
+    }
+  else
+    {
+      if (timer_irq >= 0)
+       Config::scheduler_irq_vector = 0x20 + timer_irq;
+      else
+       Config::scheduler_irq_vector = Config::Apic_timer_vector;
+    }
+
+  Idt::set_vectors_run();
   Timer::master_cpu(0);
   Apic::check_still_getting_interrupts();
 //  Cpu::init_global_features();