update

[l4.git] / kernel / fiasco / src / kern / arm / bsp / tegra2 / Modules

diff --git a/kernel/fiasco/src/kern/arm/bsp/tegra2/Modules b/kernel/fiasco/src/kern/arm/bsp/tegra2/Modules
index 9b474b6d701d5bdc44b9cf7ce0796c74c1c9a678..a72959342e8a1f9daae7c8810bee74047584fc88 100644 (file)
--- a/kernel/fiasco/src/kern/arm/bsp/tegra2/Modules
+++ b/kernel/fiasco/src/kern/arm/bsp/tegra2/Modules
@@ -3,6 +3,7 @@
 PREPROCESS_PARTS        += tegra2 16550 pic_gic mptimer
 CONFIG_KERNEL_LOAD_ADDR := 0x0
 INTERFACES_KERNEL       += gic boot_mp
+MPCORE_PHYS_BASE        := 0x50040000
 
 uart_IMPL             += uart-16550 uart-16550-arm-tegra2
 config_IMPL           += config-arm-tegra2