* GNU General Public License 2.
* Please see the COPYING-GPL-2 file for details.
*/
+#include "debug.h"
#include "hw_device.h"
#include "pci.h"
#include "main.h"
public:
typedef Hw::Pci::Cfg_width Cfg_width;
- Pci_iomem_root_bridge()
- : Pci_root_bridge(this), _iobase_virt(0), _iobase_phys(~0UL),
+ explicit Pci_iomem_root_bridge(unsigned bus_nr = 0)
+ : Pci_root_bridge(bus_nr, this), _iobase_virt(0), _iobase_phys(~0UL),
_dev_start(~0UL), _dev_end(~0UL), _iosize(0)
{
set_discover_bus_if(this);
}
- int cfg_read(unsigned bus, l4_uint32_t devfn, l4_uint32_t reg,
- l4_uint32_t *value, Cfg_width);
-
- int cfg_write(unsigned bus, l4_uint32_t devfn, l4_uint32_t reg,
- l4_uint32_t value, Cfg_width);
+ int cfg_read(Cfg_addr addr, l4_uint32_t *value, Cfg_width);
+ int cfg_write(Cfg_addr addr, l4_uint32_t value, Cfg_width);
void scan_bus();
{
if (_iobase_phys == ~0UL)
{
- printf("ERROR: Pci_root_bridge: 'iobase' not set.\n");
+ d_printf(DBG_ERR, "ERROR: Pci_root_bridge: 'iobase' not set.\n");
return;
}
if (_iosize == 0U)
{
- printf("ERROR: Pci_root_bridge: 'iosize' not set.\n");
+ d_printf(DBG_ERR, "ERROR: Pci_root_bridge: 'iosize' not set.\n");
return;
}
if (_dev_start == ~0UL || _dev_end == ~0UL)
{
- printf("ERROR: Pci_root_bridge: 'dev_start' and/or 'dev_end' not set.\n");
+ d_printf(DBG_ERR, "ERROR: Pci_root_bridge: 'dev_start' and/or 'dev_end' not set.\n");
return;
}
if (!_iobase_virt)
return;
- add_resource(new Adr_resource(Resource::Mmio_res
- | Resource::F_fixed_size
- | Resource::F_fixed_addr,
- _iobase_phys,
- _iobase_phys + _iosize - 1));
+ add_resource(new Resource(Resource::Mmio_res
+ | Resource::F_fixed_size
+ | Resource::F_fixed_addr,
+ _iobase_phys,
+ _iobase_phys + _iosize - 1));
- Adr_resource *r = new Adr_resource_provider(Resource::Mmio_res
- | Resource::F_fixed_size
- | Resource::F_fixed_addr);
+ Resource *r = new Resource_provider(Resource::Mmio_res
+ | Resource::F_fixed_size
+ | Resource::F_fixed_addr);
r->alignment(0xfffff);
r->start_end(_dev_start, _dev_end);
add_resource(r);
- r = new Adr_resource_provider(Resource::Io_res
- | Resource::F_fixed_size
- | Resource::F_fixed_addr);
+ r = new Resource_provider(Resource::Io_res
+ | Resource::F_fixed_size
+ | Resource::F_fixed_addr);
r->start_end(0, 0xffff);
add_resource(r);
}
int
-Pci_iomem_root_bridge::cfg_read(unsigned bus, l4_uint32_t devfn,
- l4_uint32_t reg,
- l4_uint32_t *value, Cfg_width order)
+Pci_iomem_root_bridge::cfg_read(Cfg_addr addr, l4_uint32_t *value, Cfg_width w)
{
using namespace Hw;
if (!_iobase_virt)
return -1;
- l4_uint32_t a = _iobase_virt + pci_conf_addr0(bus, devfn >> 16, devfn & 0xffff, reg);
- switch (order)
+ l4_uint32_t a = _iobase_virt + addr.to_compat_addr();
+ switch (w)
{
- case Pci::Cfg_byte: *value = *(volatile unsigned char *)(a + (reg & 3)); break;
- case Pci::Cfg_short: *value = *(volatile unsigned short *)(a + (reg & 2)); break;
- case Pci::Cfg_long: *value = *(volatile unsigned int *)a; break;
+ case Pci::Cfg_byte: *value = *(volatile l4_uint8_t *)a; break;
+ case Pci::Cfg_short: *value = *(volatile l4_uint16_t *)a; break;
+ case Pci::Cfg_long: *value = *(volatile l4_uint32_t *)a; break;
}
- if (0)
- printf("Pci_iomem_root_bridge::cfg_read(%x, %x, %x, %x, %d)\n",
- bus, devfn, reg, *value, order);
+ d_printf(DBG_ALL, "Pci_iomem_root_bridge::cfg_read(%x, %x, %x, %x, %x, %d)\n",
+ addr.bus(), addr.dev(), addr.fn(), addr.reg(), *value, w);
return 0;
}
int
-Pci_iomem_root_bridge::cfg_write(unsigned bus, l4_uint32_t devfn,
- l4_uint32_t reg,
- l4_uint32_t value, Cfg_width order)
+Pci_iomem_root_bridge::cfg_write(Cfg_addr addr, l4_uint32_t value, Cfg_width w)
{
using namespace Hw;
if (!_iobase_virt)
return -1;
- if (0)
- printf("Pci_iomem_root_bridge::cfg_write(%x, %x, %x, %x, %d)\n",
- bus, devfn, reg, value, order);
+ d_printf(DBG_ALL, "Pci_iomem_root_bridge::cfg_write(%x, %x, %x, %x, %x, %d)\n",
+ addr.bus(), addr.dev(), addr.fn(), addr.reg(), value, w);
- l4_uint32_t a = _iobase_virt + pci_conf_addr0(bus, devfn >> 16, devfn & 0xffff, reg);
- switch (order)
+ l4_uint32_t a = _iobase_virt + addr.to_compat_addr();
+ switch (w)
{
- case Pci::Cfg_byte: *(volatile unsigned char *)(a + (reg & 3)) = value; break;
- case Pci::Cfg_short: *(volatile unsigned short *)(a + (reg & 2)) = value; break;
- case Pci::Cfg_long: *(volatile unsigned int *)a = value; break;
+ case Pci::Cfg_byte: *(volatile l4_uint8_t *)a = value; break;
+ case Pci::Cfg_short: *(volatile l4_uint16_t *)a = value; break;
+ case Pci::Cfg_long: *(volatile l4_uint32_t *)a = value; break;
}
return 0;
}
bool Irq_router_rs::request(Resource *parent, Device *pdev,
Resource *child, Device *cdev)
{
- Adr_resource *cr = dynamic_cast<Adr_resource*>(child);
-
- if (!cr)
- {
- child->parent(parent);
- return true;
- }
-
Hw::Device *cd = dynamic_cast<Hw::Device*>(cdev);
if (!cd)
return false;
- if (cr->start() > 3)
+ if (child->start() > 3)
return false;
- int i = (cr->start() + (cd->adr() >> 16)) & 3;
+ int i = (child->start() + (cd->adr() >> 16)) & 3;
Pci_iomem_root_bridge *pd = dynamic_cast<Pci_iomem_root_bridge *>(pdev);
if (!pd)
return false;
- cr->del_flags(Resource::F_relative);
- cr->start(pd->int_map(i));
- cr->del_flags(Resource::Irq_info_base * 3);
- cr->add_flags(Resource::Irq_level | Resource::Irq_low);
+ child->del_flags(Resource::F_relative);
+ child->start(pd->int_map(i));
+ child->del_flags(Resource::Irq_type_mask);
+ child->add_flags(Resource::Irq_type_level_low);
- cr->parent(parent);
+ child->parent(parent);
return true;
}