+ board->bars[bar].base = v & ~3UL;
+ board->bars[bar].len = 1 << s;
+ board->bars[bar].type = (v & 1) ? Resource::IO_BAR : Resource::MEM_BAR;
+
+ if (scan_only)
+ printf("BAR%d: %04x (sz=%d)\n", bar, v & ~3, 1 << s);
+
+ switch (board->bars[bar].type)
+ {
+ case Resource::IO_BAR:
+ ++num_iobars;
+ if (first_port == -1)
+ first_port = bar;
+ break;
+ case Resource::MEM_BAR:
+ ++num_membars;
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (num_membars <= 1 && num_iobars == 1)
+ {
+ board->first_bar = first_port;
+ board->num_ports = board->bars[first_port].len / 8;
+ board->port_per_bar = false;
+ pci_enable_io(bus, dev, subdev);
+ return 1;
+ }
+
+
+ board->num_ports = 0;
+ board->first_bar = -1;
+
+ for (int bar = 0; bar < NUM_BARS; ++bar)
+ {
+ if (board->bars[bar].type == Resource::IO_BAR && board->bars[bar].len == 8
+ && (board->first_bar == -1
+ || (board->first_bar + board->num_ports) == bar))
+ {
+ ++board->num_ports;
+ if (board->first_bar == -1)
+ board->first_bar = bar;
+ }
+ }
+
+ board->port_per_bar = true;
+ return board->num_ports;
+
+#if 0
+