]> rtime.felk.cvut.cz Git - l4.git/blobdiff - kernel/fiasco/src/kern/arm/bsp/omap3/pic-arm-gic-omap4.cpp
update
[l4.git] / kernel / fiasco / src / kern / arm / bsp / omap3 / pic-arm-gic-omap4.cpp
index e5ab55a9e1a704128a3b56ded9c640a2d1dd081b..a69bf612414b58b38db6e783458cae2120ca2da5 100644 (file)
@@ -2,46 +2,24 @@ INTERFACE [arm && pic_gic && omap4]:
 
 #include "gic.h"
 
-EXTENSION class Pic
-{
-public:
-  enum
-  {
-    Multi_irq_pending = 0,
-    No_irq_pending = 1023,
-  };
-};
-
-//-------------------------------------------------------------------
+// ------------------------------------------------------------------------
 IMPLEMENTATION [arm && pic_gic && omap4]:
 
-#include "config.h"
-#include "initcalls.h"
-#include "irq_chip.h"
-#include "irq_chip_generic.h"
+#include "irq_mgr_multi_chip.h"
 #include "kmem.h"
 
-Gic Gic_pin::_gic[1];
-
-class Irq_chip_omap4 : public Irq_chip_gen
-{
-};
-
-PUBLIC
-void
-Irq_chip_omap4::setup(Irq_base *irq, unsigned irqnum)
-{
-  irq->pin()->replace<Gic_pin>(0, irqnum);
-}
-
 IMPLEMENT FIASCO_INIT
 void
 Pic::init()
 {
-  static Irq_chip_omap4 _ia;
-  Irq_chip::hw_chip = &_ia;
+  typedef Irq_mgr_multi_chip<8> M;
+
+  M *m = new Boot_object<M>(16);
 
-  Gic_pin::_gic[0].init(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
+  gic.construct(Kmem::Gic_cpu_map_base, Kmem::Gic_dist_map_base);
+  m->add_chip(0, gic, gic->nr_irqs());
+
+  Irq_mgr::mgr = m;
 }
 
 IMPLEMENT inline
@@ -52,21 +30,11 @@ IMPLEMENT inline
 void Pic::restore_all(Status)
 {}
 
-PUBLIC static inline
-Unsigned32 Pic::pending()
-{
-  return Gic_pin::_gic[0].pending();
-}
-
-PUBLIC static inline
-Mword Pic::is_pending(Mword &irqs, Mword irq)
-{ return irqs == irq; }
-
-//-------------------------------------------------------------------
+// ------------------------------------------------------------------------
 IMPLEMENTATION [arm && mp && pic_gic && omap4]:
 
 PUBLIC static
 void Pic::init_ap()
 {
-  Gic_pin::_gic[0].init_ap();
+  gic->init_ap();
 }