update

[l4.git] / kernel / fiasco / src / kern / arm / bsp / integrator / pic-arm-integrator.cpp

diff --git a/kernel/fiasco/src/kern/arm/bsp/integrator/pic-arm-integrator.cpp b/kernel/fiasco/src/kern/arm/bsp/integrator/pic-arm-integrator.cpp
index f8b37df2ab9220ef0781588364a24ed29f76d22d..fe90cf93ceb1c96f091e28698b3877e3c35f73bc 100644 (file)
--- a/kernel/fiasco/src/kern/arm/bsp/integrator/pic-arm-integrator.cpp
+++ b/kernel/fiasco/src/kern/arm/bsp/integrator/pic-arm-integrator.cpp
@@ -1,46 +1,49 @@
 // ---------------------------------------------------------------------
-INTERFACE [arm-integrator]:
+IMPLEMENTATION [arm && integrator]:
 
+#include "assert.h"
+#include "initcalls.h"
+#include "irq_chip_generic.h"
+#include "irq_mgr.h"
+#include "mmio_register_block.h"
 #include "kmem.h"
 
-EXTENSION class Pic
+class Irq_chip_arm_integr : public Irq_chip_gen, Mmio_register_block
 {
-public:
+private:
   enum
   {
-    IRQ_STATUS       = Kmem::Pic_map_base + 0x00,
-    IRQ_ENABLE_SET   = Kmem::Pic_map_base + 0x08,
-    IRQ_ENABLE_CLEAR = Kmem::Pic_map_base + 0x0c,
+    IRQ_STATUS       = 0x00,
+    IRQ_ENABLE_SET   = 0x08,
+    IRQ_ENABLE_CLEAR = 0x0c,
 
-    FIQ_ENABLE_CLEAR = Kmem::Pic_map_base + 0x2c,
+    FIQ_ENABLE_CLEAR = 0x2c,
 
     PIC_START = 0,
     PIC_END   = 31,
   };
-};
 
-// ---------------------------------------------------------------------
-IMPLEMENTATION [arm && integrator]:
-
-#include "io.h"
-#include "irq_chip_generic.h"
-#include "irq_mgr.h"
-
-class Irq_chip_arm_integr : public Irq_chip_gen
-{
 public:
-  Irq_chip_arm_integr() : Irq_chip_gen(32) {}
   unsigned set_mode(Mword, unsigned) { return Irq_base::Trigger_level; }
-  void set_cpu(Mword, unsigned) {}
+  void set_cpu(Mword, Cpu_number) {}
   void ack(Mword) { /* ack is empty */ }
 };
 
+PUBLIC
+Irq_chip_arm_integr::Irq_chip_arm_integr()
+: Irq_chip_gen(32),
+  Mmio_register_block(Kmem::mmio_remap(Mem_layout::Pic_phys_base))
+{
+  write<Mword>(0xffffffff, IRQ_ENABLE_CLEAR);
+  write<Mword>(0xffffffff, FIQ_ENABLE_CLEAR);
+}
+
 PUBLIC
 void
 Irq_chip_arm_integr::mask(Mword irq)
 {
   assert(cpu_lock.test());
-  Io::write(1 << (irq - Pic::PIC_START), Pic::IRQ_ENABLE_CLEAR);
+  write<Mword>(1 << (irq - PIC_START), IRQ_ENABLE_CLEAR);
 }
 
 PUBLIC
@@ -48,7 +51,7 @@ void
 Irq_chip_arm_integr::mask_and_ack(Mword irq)
 {
   assert(cpu_lock.test());
-  Io::write(1 << (irq - Pic::PIC_START), Pic::IRQ_ENABLE_CLEAR);
+  write<Mword>(1 << (irq - PIC_START), IRQ_ENABLE_CLEAR);
   // ack is empty
 }
 
@@ -57,7 +60,7 @@ void
 Irq_chip_arm_integr::unmask(Mword irq)
 {
   assert(cpu_lock.test());
-  Io::write(1 << (irq - Pic::PIC_START), Pic::IRQ_ENABLE_SET);
+  write<Mword>(1 << (irq - PIC_START), IRQ_ENABLE_SET);
 }
 
 static Static_object<Irq_mgr_single_chip<Irq_chip_arm_integr> > mgr;
@@ -66,9 +69,6 @@ IMPLEMENT FIASCO_INIT
 void Pic::init()
 {
   Irq_mgr::mgr = mgr.construct();
-
-  Io::write(0xffffffff, IRQ_ENABLE_CLEAR);
-  Io::write(0xffffffff, FIQ_ENABLE_CLEAR);
 }
 
 IMPLEMENT inline
@@ -82,10 +82,10 @@ IMPLEMENT inline
 void Pic::restore_all(Status)
 {}
 
-PUBLIC static inline NEEDS["io.h"]
+PUBLIC inline
 Unsigned32 Irq_chip_arm_integr::pending()
 {
-  return Io::read<Mword>(Pic::IRQ_STATUS);
+  return read<Mword>(IRQ_STATUS);
 }
 
 extern "C"