1 INTERFACE [arm && tegra2]:
3 EXTENSION class Mem_layout
6 enum Virt_layout_tegra2 : Address
8 Mp_scu_map_base = Devices2_map_base + 0x00040000,
9 L2cxx0_map_base = Devices2_map_base + 0x00043000,
11 Gic_cpu_map_base = Devices2_map_base + 0x00040100,
12 Gic_dist_map_base = Devices2_map_base + 0x00041000,
13 Gic2_cpu_map_base = Devices2_map_base + 0x00020000,
14 Gic2_dist_map_base = Devices2_map_base + 0x00021000,
16 Uart_base = Devices0_map_base + 0x00006300,
17 Clock_reset_map_base = Devices1_map_base + 0x00006000,
20 enum Phys_layout_tegra2 : Address {
21 Devices0_phys_base = 0x70000000,
22 Devices1_phys_base = 0x60000000,
23 Devices2_phys_base = 0x50000000,
24 Sdram_phys_base = 0x0,