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[l4.git] / kernel / fiasco / src / kern / arm / bsp / tegra2 / Modules
1 # vim:set ft=make:
2
3 PREPROCESS_PARTS        += tegra2 16550 pic_gic mptimer generic_tickless_idle
4 CONFIG_KERNEL_LOAD_ADDR := 0x0
5 INTERFACES_KERNEL       += gic
6 MPCORE_PHYS_BASE        := 0x50040000
7
8 uart_IMPL             += uart-16550 uart-16550-arm-tegra2
9 config_IMPL           += config-arm-tegra2
10 mem_layout_IMPL       += mem_layout-arm-tegra2
11 pic_IMPL              += pic-gic pic-arm-tegra2
12 bootstrap_IMPL        += bootstrap-arm-tegra2
13 timer_IMPL            += timer-arm-tegra2 timer-arm-mptimer
14 timer_tick_IMPL       += timer_tick-single-vector
15 kernel_uart_IMPL      += kernel_uart-arm-tegra2
16 reset_IMPL            += reset-arm-tegra2
17 clock_IMPL            += clock-generic
18 platform_control_IMPL += platform_control-arm-tegra2
19 outer_cache_IMPL      += outer_cache-arm-tegra2