1 // ------------------------------------------------------------------------
2 IMPLEMENTATION [arm && realview && outer_cache_l2cxx0 && armca9]:
6 Outer_cache::platform_init(Mword aux_control)
8 Io::write<Mword>(0 , TAG_RAM_CONTROL);
9 Io::write<Mword>(0 , DATA_RAM_CONTROL);
10 aux_control &= 0xc0000fff;
11 aux_control |= 1 << 17; // 16kb way size
12 aux_control |= 1 << 20; // event monitor bus enable
13 aux_control |= 1 << 22; // shared attribute ovr enable
14 aux_control |= 1 << 28; // data prefetch
15 aux_control |= 1 << 29; // insn prefetch
19 // ------------------------------------------------------------------------
20 IMPLEMENTATION [arm && realview && outer_cache_l2cxx0 && mpcore]:
24 Outer_cache::platform_init(Mword aux_control)
26 aux_control &= 0xfe000fff; // keep latencies, keep reserved, keep NS bits
27 aux_control |= 8 << 13; // 8-way associative
28 aux_control |= 4 << 17; // 128kb Way size
29 aux_control |= 1 << 22; // shared bit ignore