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[l4.git] / kernel / fiasco / src / kern / arm / bsp / realview / outer_cache-arm-realview.cpp
1 // ------------------------------------------------------------------------
2 IMPLEMENTATION [arm && realview && outer_cache_l2cxx0 && armca9]:
3
4 IMPLEMENT
5 Mword
6 Outer_cache::platform_init(Mword aux_control)
7 {
8   Io::write<Mword>(0 , TAG_RAM_CONTROL);
9   Io::write<Mword>(0 , DATA_RAM_CONTROL);
10   aux_control &= 0xc0000fff;
11   aux_control |= 1 << 17; // 16kb way size
12   aux_control |= 1 << 20; // event monitor bus enable
13   aux_control |= 1 << 22; // shared attribute ovr enable
14   aux_control |= 1 << 28; // data prefetch
15   aux_control |= 1 << 29; // insn prefetch
16   return aux_control;
17 }
18
19 // ------------------------------------------------------------------------
20 IMPLEMENTATION [arm && realview && outer_cache_l2cxx0 && mpcore]:
21
22 IMPLEMENT
23 Mword
24 Outer_cache::platform_init(Mword aux_control)
25 {
26   aux_control &= 0xfe000fff; // keep latencies, keep reserved, keep NS bits
27   aux_control |= 8 << 13; // 8-way associative
28   aux_control |= 4 << 17; // 128kb Way size
29   aux_control |= 1 << 22; // shared bit ignore
30   return aux_control;
31 }