kernel/fiasco/src/kern/ia32/irq_chip_pic.cpp

   1 INTERFACE:
   2
   3 #include "irq_chip_ia32.h"
   4
   5 /**
   6  * IRQ Chip based on the IA32 legacy PIC.
   7  *
   8  * Vectors for the PIC are from 0x20 to 0x2f statically assigned.
   9  */
  10 class Irq_chip_ia32_pic : public Irq_chip_ia32
  11 {
  12 public:
  13   char const *chip_type() const { return "PIC"; }
  14 };
  15
  16
  17 IMPLEMENTATION:
  18
  19 #include <cassert>
  20
  21 #include "boot_alloc.h"
  22 #include "cpu_lock.h"
  23 #include "globalconfig.h"
  24 #include "globals.h"
  25 #include "irq_mgr.h"
  26 #include "pic.h"
  27
  28 PUBLIC inline
  29 Irq_chip_ia32_pic::Irq_chip_ia32_pic() : Irq_chip_ia32(16)
  30 {}
  31
  32 PUBLIC
  33 bool
  34 Irq_chip_ia32_pic::alloc(Irq_base *irq, Mword irqn)
  35 {
  36   // no mor than 16 IRQs
  37   if (irqn > 0xf)
  38     return false;
  39
  40   // PIC uses vectors from 0x20 to 0x2f statically
  41   unsigned vector = 0x20 + irqn;
  42
  43   return valloc(irq, irqn, vector);
  44 }
  45
  46
  47 PUBLIC
  48 void
  49 Irq_chip_ia32_pic::mask(Mword irq)
  50 {
  51   Pic::disable_locked(irq);
  52 }
  53
  54
  55 PUBLIC
  56 void
  57 Irq_chip_ia32_pic::mask_and_ack(Mword irq)
  58 {
  59   Pic::disable_locked(irq);
  60   Pic::acknowledge_locked(irq);
  61 }
  62
  63 PUBLIC
  64 void
  65 Irq_chip_ia32_pic::ack(Mword irq)
  66 {
  67   Pic::acknowledge_locked(irq);
  68 }
  69
  70 PUBLIC
  71 unsigned
  72 Irq_chip_ia32_pic::set_mode(Mword, unsigned)
  73 { return Irq_base::Trigger_level | Irq_base::Polarity_low; }
  74
  75 PUBLIC
  76 void
  77 Irq_chip_ia32_pic::unmask(Mword irq)
  78 {
  79   Pic::enable_locked(irq, 0xa); //prio);
  80 #if 0
  81   unsigned long prio;
  82
  83   if (EXPECT_FALSE(!Irq::self(this)->owner()))
  84     return;
  85   if (Irq::self(this)->owner() == (Receiver*)-1)
  86     prio = ~0UL; // highes prio for JDB IRQs
  87   else
  88     prio = Irq::self(this)->owner()->sched()->prio();
  89 #endif
  90
  91 }
  92
  93 PUBLIC
  94 void
  95 Irq_chip_ia32_pic::set_cpu(Mword, unsigned)
  96 {}
  97
  98
  99 class Pic_irq_mgr : public Irq_mgr
 100 {
 101 private:
 102   mutable Irq_chip_ia32_pic _pic;
 103 };
 104
 105 PUBLIC Irq_mgr::Irq
 106 Pic_irq_mgr::chip(Mword irq) const
 107 {
 108   if (irq < 16)
 109     return Irq(&_pic, irq);
 110
 111   return Irq();
 112 }
 113
 114 PUBLIC
 115 unsigned
 116 Pic_irq_mgr::nr_irqs() const
 117 {
 118   return 16;
 119 }
 120
 121 PUBLIC
 122 unsigned
 123 Pic_irq_mgr::nr_msis() const
 124 { return 0; }
 125
 126
 127 // ------------------------------------------------------------------------
 128 IMPLEMENTATION [ux]:
 129
 130 PUBLIC static FIASCO_INIT
 131 void
 132 Irq_chip_ia32_pic::init()
 133 {
 134   Irq_mgr::mgr = new Boot_object<Pic_irq_mgr>();
 135 }
 136
 137 // ------------------------------------------------------------------------
 138 IMPLEMENTATION [!ux]:
 139
 140 PUBLIC static FIASCO_INIT
 141 void
 142 Irq_chip_ia32_pic::init()
 143 {
 144   Irq_mgr::mgr = new Boot_object<Pic_irq_mgr>();
 145   //
 146   // initialize interrupts
 147   //
 148   Irq_mgr::mgr->reserve(2);             // reserve cascade irq
 149   Irq_mgr::mgr->reserve(7);             // reserve spurious vect
 150   Irq_mgr::mgr->reserve(0xf);           // reserve spurious vect
 151
 152   Pic::enable_locked(2);                // allow cascaded irqs
 153 }