1 INTERFACE [arm && imx]: //----------------------------------------------
3 EXTENSION class Mem_layout
6 enum Phys_layout : Address {
7 Sdram_phys_base = CONFIG_PF_IMX_RAM_PHYS_BASE,
8 Flush_area_phys_base = 0xe0000000,
12 INTERFACE [arm && imx && imx21]: // ---------------------------------------
14 EXTENSION class Mem_layout
17 enum Virt_layout_imx21 : Address {
18 Uart_map_base = Devices1_map_base + 0x0a000,
19 Timer_map_base = Devices1_map_base + 0x03000,
20 Pll_map_base = Devices1_map_base + 0x27000,
21 Watchdog_map_base = Devices1_map_base + 0x02000,
22 Pic_map_base = Devices1_map_base + 0x40000,
23 Uart_base = Uart_map_base,
26 enum Phys_layout_imx21 : Address {
27 Devices1_phys_base = 0x10000000,
28 Devices2_phys_base = Invalid_address,
29 Devices3_phys_base = Invalid_address,
33 INTERFACE [arm && imx && imx35]: // ---------------------------------------
35 EXTENSION class Mem_layout
38 enum Virt_layout_imx35 : Address {
39 Uart_map_base = Devices1_map_base + 0x90000, // uart1
40 Timer_map_base = Devices2_map_base + 0x94000, // epit1
41 Watchdog_map_base = Devices2_map_base + 0xdc000, // wdog
42 Pic_map_base = Devices3_map_base + 0x0,
43 Uart_base = Uart_map_base,
46 enum Phys_layout_imx35 : Address {
47 Devices1_phys_base = 0x43f00000,
48 Devices2_phys_base = 0x53f00000,
49 Devices3_phys_base = 0x68000000,
54 INTERFACE [arm && imx && imx51]: // ---------------------------------------
56 EXTENSION class Mem_layout
59 enum Virt_layout_imx51 : Address {
60 Timer_map_base = Devices1_map_base + 0xac000, // epit1
61 Uart_map_base = Devices1_map_base + 0xbc000, // uart1
62 Watchdog_map_base = Devices1_map_base + 0x98000, // wdog1
63 Gic_cpu_map_base = Invalid_address,
64 Gic_dist_map_base = Devices2_map_base + 0x00000,
65 Uart_base = Uart_map_base,
68 enum Phys_layout_imx51 : Address {
69 Devices1_phys_base = 0x73f00000,
70 Devices2_phys_base = 0xe0000000,
71 Devices3_phys_base = Invalid_address,
75 INTERFACE [arm && imx && imx53]: // ---------------------------------------
77 EXTENSION class Mem_layout
80 enum Virt_layout_imx53 : Address {
81 Timer_map_base = Devices1_map_base + 0xac000, // epit1
82 Uart_map_base = Devices1_map_base + 0xbc000, // uart1
83 Watchdog_map_base = Devices1_map_base + 0x98000, // wdog1
84 Gic_cpu_map_base = Invalid_address,
85 Gic_dist_map_base = Devices2_map_base + 0xfc000,
86 Uart_base = Uart_map_base,
89 enum Phys_layout_imx53 : Address {
90 Devices1_phys_base = 0x53f00000,
91 Devices2_phys_base = 0x0ff00000,
92 Devices3_phys_base = Invalid_address,
96 INTERFACE [arm && imx && imx6]: // -----------------------------------------
98 EXTENSION class Mem_layout
101 enum Virt_layout_imx6 : Address {
102 Mp_scu_map_base = Devices1_map_base,
103 Gic_cpu_map_base = Mp_scu_map_base + 0x00100,
104 Gic_dist_map_base = Mp_scu_map_base + 0x01000,
105 L2cxx0_map_base = Mp_scu_map_base + 0x02000,
107 Uart1_map_base = Devices2_map_base + 0x20000, // uart1
108 Uart2_map_base = Devices3_map_base + 0xe8000, // uart2
109 Watchdog_map_base = Devices2_map_base + 0xbc000, // wdog1
110 Gpt_map_base = Devices2_map_base + 0x98000,
111 Src_map_base = Devices2_map_base + 0xd8000,
112 Uart_base = Uart2_map_base,
115 enum Phys_layout_imx6 : Address {
116 Devices1_phys_base = 0x00a00000,
117 Devices2_phys_base = 0x02000000,
118 Devices3_phys_base = 0x02100000,