summary |
shortlog |
log |
commit | commitdiff |
tree
raw |
patch |
inline | side by side (from parent 1:
ddc4a66)
There is no point in updating the SPI routing on cell destruction: all
CPUs the cell owned will be given back to the root cell. So any
previously written valid target configuration remain valid.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
{
paging_destroy(&cell->arch.mm, (unsigned long)gicc_base, gicc_size,
PAGING_NON_COHERENT);
{
paging_destroy(&cell->arch.mm, (unsigned long)gicc_base, gicc_size,
PAGING_NON_COHERENT);
- /* Reset interrupt routing of the cell's spis */
- gic_target_spis(cell, &root_cell);
}
static int gic_send_sgi(struct sgi *sgi)
}
static int gic_send_sgi(struct sgi *sgi)
-static void gic_cell_exit(struct cell *cell)
-{
- /* Reset interrupt routing of the cell's spis*/
- gic_route_spis(cell, &root_cell);
-}
-
static int gic_send_sgi(struct sgi *sgi)
{
u64 val;
static int gic_send_sgi(struct sgi *sgi)
{
u64 val;
.cpu_init = gic_cpu_init,
.cpu_reset = gic_cpu_reset,
.cell_init = gic_cell_init,
.cpu_init = gic_cpu_init,
.cpu_reset = gic_cpu_reset,
.cell_init = gic_cell_init,
- .cell_exit = gic_cell_exit,
.send_sgi = gic_send_sgi,
.handle_irq = gic_handle_irq,
.inject_irq = gic_inject_irq,
.send_sgi = gic_send_sgi,
.handle_irq = gic_handle_irq,
.inject_irq = gic_inject_irq,
- irqchip.cell_exit(cell);
+ if (irqchip.cell_exit)
+ irqchip.cell_exit(cell);
}
void irqchip_root_cell_shrink(struct cell *cell)
}
void irqchip_root_cell_shrink(struct cell *cell)