x86: Switch between host and guest PAT

x86: Switch between host and guest PAT

Do not allow the guest to mess with the PAT MSR in a was that also
affects the host. This may cause the host to run in uncached mode,
slowing it down, or - even worse- access MMIO with caches enabled which
will cause inconsistencies.

On Intel, we have to require and enable the related save/restore
feature. On AMD, we need to intercept the MSR accesses and map them on
the g_pat field of the VMCB.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>