x86: Add handler of accesses to PCI configuration space via I/O ports

x86: Add handler of accesses to PCI configuration space via I/O ports

Guest attempts to access ports 0xcf8 and 0xcfc are processed. String
and REP-prefixed instructions are not supported for this space. Ownership
of a device a cell tries to access to is checked. If the cell doesn't own it,
then hypervisor returns 0xFFFFFFFF to it. All read accesses to owned device are
not restricted. Writes all 1's to specific registers such as BARs or expansion
ROM address are not currently supported.
Writes to registers are moderated by white lists.

Signed-off-by: Ivan Kolchin <ivan.kolchin@siemens.com>
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>