/* First, extract the first interrupt affected by this access */
unsigned int first_irq = reg_index * irqs_per_reg;
- for (irq = first_irq; irq < first_irq + irqs_per_reg; irq++) {
- unsigned int bit_nr = (irq - first_irq) * bits_per_irq;
-
- if ((is_spi(irq) && spi_in_cell(cell, irq - 32)) ||
- irq == SGI_INJECT || irq == SGI_CPU_OFF ||
- irq == MAINTENANCE_IRQ)
- access_mask |= irq_bits << bit_nr;
- }
+ for (irq = 0; irq < irqs_per_reg; irq++)
+ if (irqchip_irq_in_cell(cell, first_irq + irq))
+ access_mask |= irq_bits << (irq * bits_per_irq);
if (!mmio->is_write) {
/* Restrict the read value */
* GICv2 uses 8bit values for each IRQ in the ITARGETRs registers
*/
static enum mmio_result handle_irq_target(struct mmio_access *mmio,
- unsigned int reg)
+ unsigned int irq)
{
/*
* ITARGETSR contain one byte per IRQ, so the first one affected by this
*/
struct cell *cell = this_cell();
unsigned int i, cpu;
- unsigned int spi = reg - 32;
unsigned int offset;
u32 access_mask = 0;
u8 targets;
* Let the guest freely access its SGIs and PPIs, which may be used to
* fill its CPU interface map.
*/
- if (!is_spi(reg)) {
+ if (!is_spi(irq)) {
mmio_perform_access(gicd_base, mmio);
return MMIO_HANDLED;
}
/*
* The registers are byte-accessible, but we always do word accesses.
*/
- offset = spi % 4;
+ offset = irq % 4;
mmio->address &= ~0x3;
mmio->value <<= 8 * offset;
mmio->size = 4;
- spi -= offset;
+ irq &= ~0x3;
- for (i = 0; i < 4; i++, spi++) {
- if (spi_in_cell(cell, spi))
+ for (i = 0; i < 4; i++, irq++) {
+ if (irqchip_irq_in_cell(cell, irq))
access_mask |= 0xff << (8 * i);
else
continue;
if (per_cpu(cpu)->cell == cell)
continue;
- printk("Attempt to route SPI%d outside of cell\n", spi);
+ printk("Attempt to route IRQ%d outside of cell\n", irq);
return MMIO_ERROR;
}
}
if (mmio->is_write) {
spin_lock(&dist_lock);
u32 itargetsr =
- mmio_read32(gicd_base + GICD_ITARGETSR + reg + offset);
+ mmio_read32(gicd_base + GICD_ITARGETSR + irq + offset);
mmio->value &= access_mask;
/* Combine with external SPIs */
mmio->value |= (itargetsr & ~access_mask);
itargetsr += 4 * 8;
for (i = 0; i < 64; i++, shift = (shift + 8) % 32) {
- if (spi_in_cell(config_cell, i)) {
+ if (irqchip_irq_in_cell(config_cell, 32 + i)) {
mask |= (0xff << shift);
bits |= (cpu_itf << shift);
}