* Jailhouse, a Linux-based partitioning hypervisor
*
* Copyright (c) Siemens AG, 2013
+ * Copyright (c) Valentine Sinitsyn, 2014
*
* Authors:
* Jan Kiszka <jan.kiszka@siemens.com>
+ * Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
*
* This work is licensed under the terms of the GNU GPL, version 2. See
* the COPYING file in the top-level directory.
#include <jailhouse/paging.h>
#include <jailhouse/cell-config.h>
-#include <jailhouse/hypercall.h>
-struct pci_device;
+struct cell_ioapic;
-/**
- * struct cell - cell-related state information
- * ...
- * @pci_addr_port_val: virtual address port for PCI config space
- * ...
- */
-/* TODO: factor out arch-independent bits, define struct arch_cell */
-struct cell {
- struct {
- /* should be first as it requires page alignment */
- u8 __attribute__((aligned(PAGE_SIZE))) io_bitmap[2*PAGE_SIZE];
- struct paging_structures ept_structs;
- } vmx;
-
- struct {
- struct paging_structures pg_structs;
- } vtd;
-
- unsigned int id;
- unsigned int data_pages;
- struct jailhouse_cell_desc *config;
-
- struct cpu_set *cpu_set;
- struct cpu_set small_cpu_set;
+/** x86-specific cell states. */
+struct arch_cell {
+ /** Buffer for the EPT/NPT root-level page table. */
+ u8 __attribute__((aligned(PAGE_SIZE))) root_table_page[PAGE_SIZE];
- bool loadable;
+ union {
+ struct {
+ /** PIO access bitmap. */
+ u8 *io_bitmap;
+ /** Paging structures used for cell CPUs. */
+ struct paging_structures ept_structs;
+ } vmx; /**< Intel VMX-specific fields. */
+ struct {
+ /** I/O Permissions Map. */
+ u8 *iopm;
+ /** Paging structures used for cell CPUs and IOMMU. */
+ struct paging_structures npt_iommu_structs;
+ } svm; /**< AMD SVM-specific fields. */
+ };
- struct cell *next;
+ union {
+ struct {
+ /** Paging structures used for DMA requests. */
+ struct paging_structures pg_structs;
+ /** True if interrupt remapping support is emulated for this
+ * cell. */
+ bool ir_emulation;
+ } vtd; /**< Intel VT-d specific fields. */
+ };
- struct pci_device *pci_devices;
+ /** Shadow value of PCI config space address port register. */
u32 pci_addr_port_val;
- u32 ioapic_index_reg_val;
- u64 ioapic_pin_bitmap;
+ /** List of IOAPICs assigned to this cell. */
+ struct cell_ioapic *ioapics;
+ /** Number of assigned IOAPICs. */
+ unsigned int num_ioapics;
- union {
- struct jailhouse_comm_region comm_region;
- u8 padding[PAGE_SIZE];
- } __attribute__((aligned(PAGE_SIZE))) comm_page;
+ /** Class Of Service for cache allocation (Intel only). */
+ u32 cos;
+ /** Allocated L3 cache region (Intel only). */
+ u64 cat_mask;
};
-extern struct cell root_cell;
-
#endif /* !_JAILHOUSE_ASM_CELL_H */