static int gic_init(void)
{
- int err;
+ /* TODO: need to validate more? */
+ if (!(mmio_read32(gicd_base + GICD_CTLR) & GICD_CTLR_ARE_NS))
+ return trace_error(-EIO);
/* FIXME: parse a dt */
gicr_base = GICR_BASE;
gicr_size = GICR_SIZE;
/* Let the per-cpu code access the redistributors */
- err = arch_map_device(gicr_base, gicr_base, gicr_size);
-
- return err;
+ return arch_map_device(gicr_base, gicr_base, gicr_size);
}
static void gic_clear_pending_irqs(void)
arm_write_sysreg(ICC_DIR_EL1, i);
}
+ /* Ensure all IPIs and the maintenance PPI are enabled. */
+ mmio_write32(gicr + GICR_ISENABLER,
+ 0x0000ffff | (1 << MAINTENANCE_IRQ));
+
/*
- * Disable all PPIs, ensure IPIs are enabled.
- * On shutdown, the root cell expects to find all its PPIs still enabled
- * when returning to the driver.
+ * Disable PPIs, except for the maintenance interrupt.
+ * On shutdown, the root cell expects to find all its PPIs still
+ * enabled - except for the maintenance interrupt we used.
*/
- if (!root_shutdown)
- mmio_write32(gicr + GICR_ICENABLER, 0xffff0000);
- mmio_write32(gicr + GICR_ISENABLER, 0x0000ffff);
+ mmio_write32(gicr + GICR_ICENABLER,
+ root_shutdown ? 1 << MAINTENANCE_IRQ :
+ 0xffff0000 & ~(1 << MAINTENANCE_IRQ));
if (root_shutdown) {
/* Restore the root config */
return -ENODEV;
}
- /* Ensure all IPIs are enabled */
- mmio_write32(redist_base + GICR_SGI_BASE + GICR_ISENABLER, 0x0000ffff);
+ /* Ensure all IPIs and the maintenance PPI are enabled. */
+ mmio_write32(redist_base + GICR_SGI_BASE + GICR_ISENABLER,
+ 0x0000ffff | (1 << MAINTENANCE_IRQ));
/*
* Set EOIMode to 1
return 0;
}
-static void gic_route_spis(struct cell *config_cell, struct cell *dest_cell)
+static void gic_adjust_irq_target(struct cell *cell, u16 irq_id)
{
- int i;
- void *irouter = gicd_base + GICD_IROUTER;
- unsigned int first_cpu;
+ void *irouter = gicd_base + GICD_IROUTER + irq_id;
+ u32 route = mmio_read32(irouter);
- /* Use the core functions to retrieve the first physical id */
- for_each_cpu(first_cpu, dest_cell->cpu_set)
- break;
-
- for (i = 0; i < 64; i++, irouter += 8) {
- if (spi_in_cell(config_cell, i))
- mmio_write64(irouter, first_cpu);
- }
+ if (!cell_owns_cpu(cell, route))
+ mmio_write32(irouter, first_cpu(cell->cpu_set));
}
static enum mmio_result gic_handle_redist_access(void *arg,
return MMIO_HANDLED;
}
}
- arm_mmio_perform_access((unsigned long)phys_redist, mmio);
+ mmio_perform_access(phys_redist, mmio);
return MMIO_HANDLED;
}
static int gic_cell_init(struct cell *cell)
{
- gic_route_spis(cell, cell);
-
mmio_region_register(cell, (unsigned long)gicd_base, gicd_size,
gic_handle_dist_access, NULL);
mmio_region_register(cell, (unsigned long)gicr_base, gicr_size,
return 0;
}
-static void gic_cell_exit(struct cell *cell)
-{
- /* Reset interrupt routing of the cell's spis*/
- gic_route_spis(cell, &root_cell);
-}
-
static int gic_send_sgi(struct sgi *sgi)
{
u64 val;
gic_handle_sgir_write(&sgi, true);
}
+/*
+ * GICv3 uses a 64bit register IROUTER for each IRQ
+ */
+enum mmio_result gic_handle_irq_route(struct mmio_access *mmio,
+ unsigned int irq)
+{
+ struct cell *cell = this_cell();
+ unsigned int cpu;
+
+ /* Ignore aff3 on AArch32 (return 0) */
+ if (mmio->size == 4 && (mmio->address % 8))
+ return MMIO_HANDLED;
+
+ /* SGIs and PPIs are res0 */
+ if (!is_spi(irq))
+ return MMIO_HANDLED;
+
+ /*
+ * Ignore accesses to SPIs that do not belong to the cell. This isn't
+ * forbidden, because the guest driver may simply iterate over all
+ * registers at initialisation
+ */
+ if (!irqchip_irq_in_cell(cell, irq))
+ return MMIO_HANDLED;
+
+ /* Translate the virtual cpu id into the physical one */
+ if (mmio->is_write) {
+ mmio->value = arm_cpu_virt2phys(cell, mmio->value);
+ if (mmio->value == -1) {
+ printk("Attempt to route IRQ%d outside of cell\n", irq);
+ return MMIO_ERROR;
+ }
+ mmio_perform_access(gicd_base, mmio);
+ } else {
+ cpu = mmio_read32(gicd_base + GICD_IROUTER + 8 * irq);
+ mmio->value = arm_cpu_phys2virt(cpu);
+ }
+ return MMIO_HANDLED;
+}
+
static void gic_eoi_irq(u32 irq_id, bool deactivate)
{
arm_write_sysreg(ICC_EOIR1_EL1, irq_id);
arm_write_sysreg(ICC_DIR_EL1, irq_id);
}
-static int gic_inject_irq(struct per_cpu *cpu_data, struct pending_irq *irq)
+static int gic_inject_irq(struct per_cpu *cpu_data, u16 irq_id)
{
int i;
int free_lr = -1;
* A strict phys->virt id mapping is used for SPIs, so this test
* should be sufficient.
*/
- if ((u32)lr == irq->virt_id)
- return -EINVAL;
+ if ((u32)lr == irq_id)
+ return -EEXIST;
}
- if (free_lr == -1) {
- u32 hcr;
- /*
- * All list registers are in use, trigger a maintenance
- * interrupt once they are available again.
- */
- arm_read_sysreg(ICH_HCR_EL2, hcr);
- hcr |= ICH_HCR_UIE;
- arm_write_sysreg(ICH_HCR_EL2, hcr);
-
+ if (free_lr == -1)
+ /* All list registers are in use */
return -EBUSY;
- }
- lr = irq->virt_id;
+ lr = irq_id;
/* Only group 1 interrupts */
lr |= ICH_LR_GROUP_BIT;
lr |= ICH_LR_PENDING;
- if (irq->hw) {
+ if (!is_sgi(irq_id)) {
lr |= ICH_LR_HW_BIT;
- lr |= (u64)irq->type.irq << ICH_LR_PHYS_ID_SHIFT;
- } else if (irq->type.sgi.maintenance) {
- lr |= ICH_LR_SGI_EOI;
+ lr |= (u64)irq_id << ICH_LR_PHYS_ID_SHIFT;
}
gic_write_lr(free_lr, lr);
return 0;
}
+static void gicv3_enable_maint_irq(bool enable)
+{
+ u32 hcr;
+
+ arm_read_sysreg(ICH_HCR_EL2, hcr);
+ if (enable)
+ hcr |= ICH_HCR_UIE;
+ else
+ hcr &= ~ICH_HCR_UIE;
+ arm_write_sysreg(ICH_HCR_EL2, hcr);
+}
+
unsigned int irqchip_mmio_count_regions(struct cell *cell)
{
return 2;
}
-struct irqchip_ops gic_irqchip = {
+struct irqchip_ops irqchip = {
.init = gic_init,
.cpu_init = gic_cpu_init,
.cpu_reset = gic_cpu_reset,
.cell_init = gic_cell_init,
- .cell_exit = gic_cell_exit,
+ .adjust_irq_target = gic_adjust_irq_target,
.send_sgi = gic_send_sgi,
.handle_irq = gic_handle_irq,
.inject_irq = gic_inject_irq,
+ .enable_maint_irq = gicv3_enable_maint_irq,
.eoi_irq = gic_eoi_irq,
};
projects / jailhouse.git / blobdiff