]> rtime.felk.cvut.cz Git - jailhouse.git/blobdiff - hypervisor/arch/x86/include/asm/processor.h
Merge remote-tracking branch 'kiszka/master'
[jailhouse.git] / hypervisor / arch / x86 / include / asm / processor.h
index 5fbf50bfb4114839d6b17232d6192d8643c13b8f..85e41b35b81b01be14aa2d3e63252263e7c329df 100644 (file)
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
+ *
+ * This file is based on linux/arch/x86/include/asm/special_insn.h and other
+ * kernel headers:
+ *
+ * Copyright (c) Linux kernel developers, 2013
  */
 
 #ifndef _JAILHOUSE_ASM_PROCESSOR_H
 
 #include <jailhouse/types.h>
 
+/* leaf 0x01, ECX */
 #define X86_FEATURE_VMX                                        (1 << 5)
+#define X86_FEATURE_XSAVE                              (1 << 26)
+#define X86_FEATURE_HYPERVISOR                         (1 << 31)
+
+/* leaf 0x07, subleaf 0, EBX */
+#define X86_FEATURE_CAT                                        (1 << 15)
+
+/* leaf 0x80000001, ECX */
+#define X86_FEATURE_SVM                                        (1 << 2)
+
+/* leaf 0x80000001, EDX */
 #define X86_FEATURE_GBPAGES                            (1 << 26)
 #define X86_FEATURE_RDTSCP                             (1 << 27)
 
-#define X86_FEATURE_SVM                                        (1 << 2)
+/* leaf 0x8000000a, EDX */
 #define X86_FEATURE_NP                                 (1 << 0)
 #define X86_FEATURE_FLUSH_BY_ASID                      (1 << 6)
 #define X86_FEATURE_DECODE_ASSISTS                     (1 << 7)
 #define MSR_IA32_APICBASE                              0x0000001b
 #define MSR_IA32_FEATURE_CONTROL                       0x0000003a
 #define MSR_IA32_PAT                                   0x00000277
+#define MSR_IA32_MTRR_DEF_TYPE                         0x000002ff
 #define MSR_IA32_SYSENTER_CS                           0x00000174
 #define MSR_IA32_SYSENTER_ESP                          0x00000175
 #define MSR_IA32_SYSENTER_EIP                          0x00000176
+#define MSR_IA32_PERF_GLOBAL_CTRL                      0x0000038f
 #define MSR_IA32_VMX_BASIC                             0x00000480
 #define MSR_IA32_VMX_PINBASED_CTLS                     0x00000481
 #define MSR_IA32_VMX_PROCBASED_CTLS                    0x00000482
@@ -71,6 +89,8 @@
 #define MSR_X2APIC_BASE                                        0x00000800
 #define MSR_X2APIC_ICR                                 0x00000830
 #define MSR_X2APIC_END                                 0x0000083f
+#define MSR_IA32_PQR_ASSOC                             0x00000c8f
+#define MSR_IA32_L3_MASK_0                             0x00000c90
 #define MSR_EFER                                       0xc0000080
 #define MSR_STAR                                       0xc0000081
 #define MSR_LSTAR                                      0xc0000082
 #define FEATURE_CONTROL_LOCKED                         (1 << 0)
 #define FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX      (1 << 2)
 
+#define PAT_RESET_VALUE                                        0x0007040600070406UL
+
+#define MTRR_ENABLE                                    (1UL << 11)
+
 #define EFER_LME                                       0x00000100
 #define EFER_LMA                                       0x00000400
 #define EFER_NXE                                       0x00000800
 
+#define PQR_ASSOC_COS_SHIFT                            32
+
+#define CAT_RESID_L3                                   1
+
+#define CAT_CBM_LEN_MASK                               BIT_MASK(4, 0)
+#define CAT_COS_MAX_MASK                               BIT_MASK(15, 0)
+
 #define GDT_DESC_NULL                                  0
 #define GDT_DESC_CODE                                  1
 #define GDT_DESC_TSS                                   2
 #define X86_OP_MOV_TO_MEM                              0x89
 #define X86_OP_MOV_FROM_MEM                            0x8b
 
+#define DB_VECTOR                                      1
 #define NMI_VECTOR                                     2
 #define PF_VECTOR                                      14
+#define AC_VECTOR                                      17
 
 #define DESC_TSS_BUSY                                  (1UL << (9 + 32))
 #define DESC_PRESENT                                   (1UL << (15 + 32))
  * @{
  */
 
-struct registers {
-       unsigned long r15;
-       unsigned long r14;
-       unsigned long r13;
-       unsigned long r12;
-       unsigned long r11;
-       unsigned long r10;
-       unsigned long r9;
-       unsigned long r8;
-       unsigned long rdi;
-       unsigned long rsi;
-       unsigned long rbp;
-       unsigned long unused;
-       unsigned long rbx;
-       unsigned long rdx;
-       unsigned long rcx;
-       unsigned long rax;
+union registers {
+       struct {
+               unsigned long r15;
+               unsigned long r14;
+               unsigned long r13;
+               unsigned long r12;
+               unsigned long r11;
+               unsigned long r10;
+               unsigned long r9;
+               unsigned long r8;
+               unsigned long rdi;
+               unsigned long rsi;
+               unsigned long rbp;
+               unsigned long unused;
+               unsigned long rbx;
+               unsigned long rdx;
+               unsigned long rcx;
+               unsigned long rax;
+       };
+       unsigned long by_index[16];
 };
 
 struct desc_table_reg {
@@ -173,8 +209,8 @@ static inline void memory_load_barrier(void)
        asm volatile("lfence" : : : "memory");
 }
 
-static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
-                          unsigned int *ecx, unsigned int *edx)
+static inline void cpuid(unsigned int *eax, unsigned int *ebx,
+                        unsigned int *ecx, unsigned int *edx)
 {
        /* ecx is often an input as well as an output. */
        asm volatile("cpuid"
@@ -183,21 +219,15 @@ static inline void __cpuid(unsigned int *eax, unsigned int *ebx,
            : "memory");
 }
 
-static inline void cpuid(unsigned int op, unsigned int *eax, unsigned int *ebx,
-                        unsigned int *ecx, unsigned int *edx)
-{
-       *eax = op;
-       *ecx = 0;
-       __cpuid(eax, ebx, ecx, edx);
-}
-
-#define CPUID_REG(reg)                                         \
-static inline unsigned int cpuid_##reg(unsigned int op)                \
-{                                                              \
-       unsigned int eax, ebx, ecx, edx;                        \
-                                                               \
-       cpuid(op, &eax, &ebx, &ecx, &edx);                      \
-       return reg;                                             \
+#define CPUID_REG(reg)                                                 \
+static inline unsigned int cpuid_##reg(unsigned int op, unsigned int sub) \
+{                                                                      \
+       unsigned int eax, ebx, ecx, edx;                                \
+                                                                       \
+       eax = op;                                                       \
+       ecx = sub;                                                      \
+       cpuid(&eax, &ebx, &ecx, &edx);                                  \
+       return reg;                                                     \
 }
 
 CPUID_REG(eax)
@@ -268,6 +298,17 @@ static inline void write_msr(unsigned int msr, unsigned long val)
                : "memory");
 }
 
+static inline void set_rdmsr_value(union registers *regs, unsigned long val)
+{
+       regs->rax = (u32)val;
+       regs->rdx = val >> 32;
+}
+
+static inline unsigned long get_wrmsr_value(union registers *regs)
+{
+       return (u32)regs->rax | (regs->rdx << 32);
+}
+
 static inline void read_gdtr(struct desc_table_reg *val)
 {
        asm volatile("sgdtq %0" : "=m" (*val));