Merge remote-tracking branch 'kiszka/master'

[jailhouse.git] / hypervisor / arch / x86 / include / asm / cell.h

diff --git a/hypervisor/arch/x86/include/asm/cell.h b/hypervisor/arch/x86/include/asm/cell.h
index 2ff13d23abf688914d5b8a5017c69e8f43ac9c62..2223532a39c93f13cd7f771e646ea3da276b742e 100644 (file)
--- a/hypervisor/arch/x86/include/asm/cell.h
+++ b/hypervisor/arch/x86/include/asm/cell.h
@@ -2,9 +2,11 @@
  * Jailhouse, a Linux-based partitioning hypervisor
  *
  * Copyright (c) Siemens AG, 2013
+ * Copyright (c) Valentine Sinitsyn, 2014
  *
  * Authors:
  *  Jan Kiszka <jan.kiszka@siemens.com>
+ *  Valentine Sinitsyn <valentine.sinitsyn@gmail.com>
  *
  * This work is licensed under the terms of the GNU GPL, version 2.  See
  * the COPYING file in the top-level directory.
@@ -13,33 +15,54 @@
 #ifndef _JAILHOUSE_ASM_CELL_H
 #define _JAILHOUSE_ASM_CELL_H
 
-#include <asm/types.h>
-#include <asm/paging.h>
+#include <jailhouse/paging.h>
 
 #include <jailhouse/cell-config.h>
 
-struct cell {
-       struct {
-               /* should be first as it requires page alignment */
-               u8 __attribute__((aligned(PAGE_SIZE))) io_bitmap[2*PAGE_SIZE];
-               pgd_t *ept;
-       } vmx;
+struct cell_ioapic;
 
-       struct {
-               pgd_t *page_table;
-       } vtd;
+/** x86-specific cell states. */
+struct arch_cell {
+       /** Buffer for the EPT/NPT root-level page table. */
+       u8 __attribute__((aligned(PAGE_SIZE))) root_table_page[PAGE_SIZE];
 
-       char name[JAILHOUSE_CELL_NAME_MAXLEN+1];
-       unsigned int id;
+       union {
+               struct {
+                       /** PIO access bitmap. */
+                       u8 *io_bitmap;
+                       /** Paging structures used for cell CPUs. */
+                       struct paging_structures ept_structs;
+               } vmx; /**< Intel VMX-specific fields. */
+               struct {
+                       /** I/O Permissions Map. */
+                       u8 *iopm;
+                       /** Paging structures used for cell CPUs and IOMMU. */
+                       struct paging_structures npt_iommu_structs;
+               } svm; /**< AMD SVM-specific fields. */
+       };
 
-       struct cpu_set *cpu_set;
-       struct cpu_set small_cpu_set;
+       union {
+               struct {
+                       /** Paging structures used for DMA requests. */
+                       struct paging_structures pg_structs;
+                       /** True if interrupt remapping support is emulated for this
+                        * cell. */
+                       bool ir_emulation;
+               } vtd; /**< Intel VT-d specific fields. */
+       };
 
-       unsigned long page_offset;
+       /** Shadow value of PCI config space address port register. */
+       u32 pci_addr_port_val;
 
-       struct cell *next;
-};
+       /** List of IOAPICs assigned to this cell. */
+       struct cell_ioapic *ioapics;
+       /** Number of assigned IOAPICs. */
+       unsigned int num_ioapics;
 
-extern struct cell *cell_list;
+       /** Class Of Service for cache allocation (Intel only). */
+       u32 cos;
+       /** Allocated L3 cache region (Intel only). */
+       u64 cat_mask;
+};
 
 #endif /* !_JAILHOUSE_ASM_CELL_H */